BGA焊点失效分析

文章通过对BGA焊点失效实例的分析,介绍了对BGA焊接失效的分析过程与分析方法,同时得出了引起该BGA焊点失效的主要原因,展现了失效分析对BGA封装的质量控制作用。     

振动载荷下电路板级焊点失效信号表征及分析

针对板级焊点在振动载荷下的失效问题,搭建了具有焊点电信号监测功能的振动加速失效实验平台,在定频定幅简谐振动实验的基础上,对表征信号进行分析,通过电阻信号峰值标定焊点的失效程度.实验结果表明,焊点失效初期呈现为3个阶段,每个阶段包含电阻变化的平缓区间和陡变区间.随着3个阶段的改变,焊点低阻值区间振动循环数递减,焊点高阻值区间振动循环数递增.在此基础上,以电阻均值表征焊点平均失效程度,建立了表征焊点振动疲劳寿命的多项式模型,可以描述不同阶段焊点阻值和振动循环数的关系.     

PBGA器件焊点的可靠性分析研究

根据PBGA器件组装特点,分析了器件焊点的失效机理,并针对实际应用中失效的PBGA器件在温度循环前后,分别使用染色试验、切片分析、X-射线分析等方法进行失效分析.分析结果显示样品PBGA焊点存在不同程度的焊接问题,并且焊接质量的好坏直接影响器件焊点抵抗外界应变应力的能力.最后,开展了PBGA器件焊接工艺研究和可靠性试验,试验结果显示焊接工艺改进后焊点的可靠性良好.     

倒装焊陶瓷封装失效模式分析及失效机理研究

随着封装技术的发展,倒装焊技术得到广泛的应用,倒装焊的研究也越来越广泛深入。文章阐述了倒装焊封装的失效模式,主要有焊点疲劳失效、填充胶分层开裂失效、电迁移失效、腐蚀失效、机械应力失效等。并分析了陶瓷基板倒装焊温度循环试验后的失效模式,陶瓷倒装焊封装失效的机理主要是倒装芯片焊点与UBM界面金属间化合物应力开裂失效。根据失效机理分析,进行陶瓷倒装焊工艺优化改进,试验达到了JESD22-A104C标准规定的温度循环:-65℃～+150℃、500次循环、3只样品无失效的要求。     

CQFP器件焊点开裂失效分析

CQFP器件由于其可靠性高的优势已经广泛应用于军事、航天航空领域,但是在实际使用中,特别是在温度和力学条件下容易出现焊点脱落和引脚断裂等问题。针对在工作中遇到的一次典型焊点开裂失效案例进行分析,对问题产生的根源进行了定位,对焊点开裂的失效机理进行了分析,最后简要介绍了提高CQFP器件焊接可靠性的一些工艺措施。     

向后兼容混合焊点的可靠性分析

在从有铅向无铅转换过程中,电子产品制造商不可避免会碰到同一组装过程中有铅和无铅的混合情况.因此,有必要对形成的混合焊点进行可靠性分析.对混合焊点的失效形式和混合焊点的失效机理进行了分析,并进一步介绍了影响这类焊点可靠性的因素.     

BGA封装倒装焊点不同接触面跌落失效的研究

采用自由跌落的试验方法,研究了BGA(球栅阵列)封装自由跌落到不同材质基板后的可靠性,对比分析焊点裂纹产生、扩展直至断裂的机理。对失效封装芯片进行了染色处理,观察BGA封装中焊点的失效位置和焊点内部裂纹的形貌。结果表明,不同接触面上焊球裂纹都经历稳态-扩展-失效的过程,石质接触面上裂纹出现最早,裂纹扩展最快,失效最快,钢质接触面次之,最后是木质接触面。木质接触面的焊点失效模式主要是焊盘失效;钢质和石质接触面的焊点的失效模式以金属间化合物失效为主。比例风险模型(PHM)估计得到的寿命值与试验结果误差较小,能有效预测焊点自由跌落条件下的寿命。     

无铅焊点的可靠性研究

电子产品的质量很大程度上取决于焊点的质量与可靠性。在无铅化进程中，由于无铅焊点焊料的不同和焊接工艺参数的调整，必然会给焊点可靠性带来许多新的影响。本文进行了焊点的失效分析，并从PCB和模板设计、表面组装材料、及工艺角度分析了影响无铅焊点可靠性的因素，最后分析了焊点的常见的可靠性问题的产生原因及解决办法等。     

银含量对随机振动条件下无铅焊点可靠性的影响

为了探究银含量对无铅焊点在随机振动条件下的可靠性的影响,对Sn-3.0Ag-0.5Cu、Sn-1.0Ag-0.5Cu和Sn-0.3Ag-0.7Cu三种不同Ag含量材料的焊点做窄带范围内的随机振动疲劳实验,并对失效焊点进行分析。结果表明:三种材料焊点的失效位置基本都在靠近PCB侧,最外围焊点最容易失效,失效模式均为脆性断裂,并且随着Ag含量的降低,金属间化合物的厚度逐渐减小,焊点的疲劳寿命逐渐延长。     

倒装焊结构的大规模集成电路焊点失效机理研究

在倒装焊结构的球栅阵列（BGA）封装大规模集成电路（LSIC）的服役过程中,由于BGA焊球、基板材料和PCB材料的热膨胀系数不同,焊点失效成为倒装焊结构LSIC的主要失效模式。焊点失效与焊料性质、焊接时间和温度、制造中的缺陷等密切相关。结合焊点失效的常见形貌及实例,研究倒装焊结构的LSIC的焊点失效模式及失效机理。针对可能引发失效的因素,提出从工艺到应用的一系列预防措施,对提升该类型电路的可靠性具有指导意义。     

硅基梳齿式MEMS器件及封装的失效调查

对典型硅基梳齿式MEMS器件进行失效调查和分析,验证其主要失效模式,分析其失效机理.利用电子扫描显微镜(SEM),X射线透视系统、扫描声学显微镜(SAM),X射线能谱成份分析(EDX)、金相切片分析、封装气体分析及电性能测试等分析技术,发现在工艺制造中的机械失效是造成此类器件失效的主要原因.另外,此类器件的封装失效主要表现为气密性失效和装配工艺失效.     

沉锡PCB焊接失效分析方法介绍

根据多例沉锡焊接失效案例,对导致沉锡PCB焊接失效的原因进行了分析,并详细的介绍了多种沉锡PCB焊接失效分析方法。     

集成电路陶瓷外壳析出物失效模式分析

为了集成电路的可靠性保证,往往需要对集成电路外壳进行验收。验收项目中,有一个耐湿试验分组,用来加速评定外壳的抗腐蚀性能及相应的质量可靠性能。在该试验分组中发现,陶瓷外壳失效除了已有的常规模式外,还有一种很严重的析出物失效模式。发现焊框与陶瓷结合处有胶体状析出物,析出物以流质状态析出,然后凝固,严重的还会造成焊框漏气,从而引起外壳失效。     

Correlation of electromigration lifetime distribution to failure mode in dual Damascene Cu/SiLK interconnects

The electromigration cumulative percent lifetime probability of dual Damascene Cu/SiLK interconnects was fitted using three, individual lognormal functions where the functional populations were grouped by void growth location determined from focused ion beam failure analysis of all 54 of the stressed structures. The early, first mode failures were characterized by small voids in the bottom of the vias. The intermediate mode failures had voids in the line and via bottom while the late mode failures had voids that formed in the line only. The three, individual lognormal functions provided good fits of the data. Failure mode population separation using comprehensive failure analysis suggested that only the first mode failures should be used in the prediction of the chip design current.     

The common thread for operational reliability and failure physics

Operational reliability and failure physics constitute the two extreme ends of the reliability engineering spectrum. One critical common thread that ties these two extremes together is stress. Studies that relate failures and failure mechanisms to operational reliability through this common thread have been near non-existent. This paper is an attempt to stimulate interest to fill the gap for electronic systems. Flaws exist in a piece of electronic equipment at the time of manufacture, and stresses exacerbate these flaws to the point of equipment failure. There are no random failures. Every failure is relatable to certain stresses. Estimated flaw population distributions and stress versus time-to-failure characteristics show that electronic equipment failure rates should decrease with respect to time of stress application, such as operating time. Failure rate expressions have been developed for selected stresses (i.e., high temperature, thermal cycling, electrical stresses and vibration) and are discussed in detail in the text. Much more work is still required in equating the quantitative measures of stress to failure rates and operational reliability. This paper will help in paving the way towards that end.     

A study on electrochemical effects in external capacitor packages

Exposing semiconductor devices with external capacitors to harsh environmental conditions may lead to electrical failures with the formation of conductive paths. This paper presents examples of the analysis of modules with the purpose to understand the respective failure modes. Appropriate sample preparation, sensitive analytical methods like micro-X-ray fluorescence spectroscopy (μXRF), ToF-SIMS, SEM/EDX, X-ray-microscopy as well as micro computed X-ray-tomography (μCT) have been applied to identify the root causes of the electrical failures.As a main conclusion of these investigations, we found that electrolytes can easily penetrate thermoplastic overmold materials which are typically used by module manufacturers. This can lead to either reversible electrical failures which can be eliminated by drying or irreversible electrical failures because of material migration. The effective failure mode depends on mechanical and climate conditions inside the module which could not be simulated up to now under laboratory but only under application conditions.     

Using charged device model testing to eliminate real-world ESD failures

Of 30 bipolar, BiCMOS, and CMOS monolithic, integrated circuit products that were ESD classified to the socketed Charged Device Model (CDM), 27 had ≥500 V withstand voltages and experienced no real-world CDM failures. Two of the three focus products with < 500 V withstand voltages initially had numerous manufacturing-induced CDM failures. Analysis of these two products showed that both socketed and non-socketed CDM testing induced damage at the same failure sites as identified on real-world CDM failures. However, only non-socketed CDM testing consistently reproduced the subtle damage observed on the real-world failures. On one of the focus products, the more severe damage induced by socketed CDM testing resulted in an open circuit rather than the resistive short that occurred on both the non-socketed and real-world CDM failures.Once the physics of CDM failure on the three focus products were fully understood, the ESD redesigns were relatively straightforward. On all three products, diffused series resistors and/or clamping devices with fast response times were added to the pins with inadequate CDM robustness. For each product, these redesigns boosted the socketed CDM withstand voltages for the previously susceptible pins to ≥1500 V and eliminated real-world CDM failures.Based on this work, a combined socketed and non-socketed CDM test approach is proposed for classifying/evaluating products and driving CDM robustness improvements. Guidelines for CDM testing and CDM improvement programs are also provided.     

Scalable Approach to Failure Analysis of High‐Performance Computing Systems

Failure analysis is necessary to clarify the root cause of a failure, predict the next time a failure may occur, and improve the performance and reliability of a system. However, it is not an easy task to analyze and interpret failure data, especially for complex systems. Usually, these data are represented using many attributes, and sometimes they are inconsistent and ambiguous. In this paper, we present a scalable approach for the analysis and interpretation of failure data of high‐performance computing systems. The approach employs rough sets theory (RST) for this task. The application of RST to a large publicly available set of failure data highlights the main attributes responsible for the root cause of a failure. In addition, it is used to analyze other failure characteristics, such as time between failures, repair times, workload running on a failed node, and failure category. Experimental results show the scalability of the presented approach and its ability to reveal dependencies among different failure characteristics.     

厚膜混合集成电路可靠性技术

总结了混合集成电路的主要失效模式,在此基础上,主要从混合集成电路的设计和工艺两方面分析了其产生的原因,通过设计、工艺、原材料和元器件等方面采取对策和措施,达到提高混合集成电路可靠性的目的.