共查询到20条相似文献,搜索用时 31 毫秒
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A Josephson comparator based on a nonhysteric one-junction superconducting quantum interference device (SQUID) for use in a periodic-threshold A/D (analog-to-digital) converter is discussed. Simulations show that a 4-bit A/D converter using this comparator could have a sampling rate of >20 GHz with an analog signal bandwidth of >10 GHz. This performance represents a factor-of-greater-than-five improvement over that of other periodic-threshold A/D converters, which are based on two- or three-junction SQUIDs 相似文献
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Yang C.-K.K. Stojanovic V. Modjtahedi S. Horowitz M.A. Ellersick W.F. 《Solid-State Circuits, IEEE Journal of》2001,36(11):1684-1692
This paper presents a transceiver that uses a 4-bit flash analog-to-digital converter (ADC) for the receiver and an 8-bit current-steering digital-to-analog converter (DAC) for the transmitter. The 8-GSamples/s converters are 8-way time interleaved. Digital compensation reduces the input offset of the ADC comparators to less than 0.6 LSB, improves the accuracy of the interleaved sampling clocks to within 10 ps, and reduces systematic coupling noise to less than 18 mV on the 800-mV signal swing. 1.1-nH bondwire inductors distribute the parasitic capacitances at the transceiver input and output, reducing attenuation by 10 dB at 4 GHz. Equalization algorithms using the converters compensate for the 1.5-GHz transceiver bandwidth to allow 8-GSamples/s multilevel data transmission 相似文献
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Ko H.L. Lee G.S. Barfknecht A.T. 《Applied Superconductivity, IEEE Transactions on》1993,3(4):3082-3094
Work towards a high-resolution multi-gigahertz sampling rate A/D converter is presented. A brief review of the overall architecture which consists of a coarse section and an interpolator section is given. Experiments on two designs for the coarse sections are discussed. One is a 6-bit A/D converter built with two-leaf phase tree periodic comparators. Asynchronous beat frequency tests at 2.01 GHz sampling rates indicate this circuit is capable of 6 bits of resolution at 2 GHz input bandwidth. The resolution falls off to about 5 bits at 4 GHz and 4 bits at 6 GHz. The other approach involves two related novel single threshold comparators with large dynamic range. For one of the comparators, dynamic range in excess of 60 db is demonstrated by transfer characteristic and input current noise measurements, while the other showed 54 db of dynamic range. A chain of 15 comparators based on one of the designs has been designed and tested. Asynchronous beat frequency tests at 2.01 GHz sampling rates show a monotonic response for input frequencies up to 8 GHz. Threshold offsets due to flux trapping limited the resolution in this set of experiments to about 5 bits. Experiments on a periodic interpolator circuit based on the two-leaf phase tree comparator are also presented. The results suggest that it should be possible to obtain 10-bits of resolution with this approach 相似文献
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A CMOS analog to digital converter based on the folding and interpolating technique is presented. This technique is successfully applied in bipolar A/D converters and now also becomes available in CMOS technology. The analog bandwidth of the A/D converter is increased by using a transresistance amplifier at the outputs of the folding amplifiers and, due to careful circuit design, the comparators need no offset compensation. The result is a small area (0.7 mm2 in 0.8 μm CMOS), high speed (70 MS/s), and low-power (110 mW at 5 V supply, including reference ladder) A/D converter. A 3.3 V supply version of the circuit runs at 45 MS/s and dissipates 45 mW 相似文献
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《Solid-State Circuits, IEEE Journal of》1975,10(6):392-399
Describes a monolithic circuit consisting of an array of 8 voltage comparators, a resistive voltage divider, and associated logic circuits. Intended as an encoding component for high-speed parallel A/D converters, this `3-bit quantizer' uses regeneration for voltage gain and signal storage. A Gray-code output minimizes the problem of comparator indecision. The principal error sources are an asymmetry-induced comparator offset with 2-mV standard deviation and a thermally induced offset of a much as /spl plusmn/2.5 mV, dependent on signal history. The quantizer has been incorporated in an experimental 6-bit 200 megasample/s (MS/s) A/D converter. 相似文献
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Time interleaved converter arrays 总被引:4,自引:0,他引:4
《Solid-State Circuits, IEEE Journal of》1980,15(6):1022-1029
High-speed monolithic converters normally use a variation of the flash technique, which 2/SUP n/ comparators in parallel to obtain a fast n-bit conversion. Although this method allows for high converter bandwidth, it is not very area efficient, and results in large die sizes for even modest resolution converters. In the technique presented here, a number of small but area efficient converters are operated in a time-interleaved fashion to achieve the bandwidth of a flash circuit, but in a substantially smaller area. This technique is analyzed with respect to noise and distortion resulting from nonideal array characteristics, and is demonstrated by way of a four-way array test-chip. This chip consists of four time-interleaved 7-bit weighted-capacitor A/D converters fabricated in a 10 /spl mu/m metal-gate CMOS process. Full 7-bit linearity is maintained up to a 2.5 MHz conversion rate, with operation at reduced linearity continuing to approximately 4 MHz. The design of this chip, and anticipated characteristics if fabricated in a modern 4-5 /spl mu/m process are described. 相似文献
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Lee G.S. Peterson D.A. 《Proceedings of the IEEE. Institute of Electrical and Electronics Engineers》1989,77(8):1264-1273
A number of superconductive A/D (analog/digital) converter designs that show promise for superiority in high-bandwidth or high-resolution applications are known. On the high-resolution side, counting-type converters appear quite attractive. Voltage-to-frequency and tracking A/D converters are reviewed in this category. On the ultra-high-bandwidth side (greater than about 1 GHz) the parallel-type A/D converters seem to be advantageous. A number of parallel periodic-threshold A/D converters that have been attempted over the years as well as a fully parallel (2N-1 comparators) A/D converter are reviewed 相似文献
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Traditionally, circuit designers have adopted analog techniques to overcome comparator offset in flash converters. These schemes have an adverse effect on area and power consumption and, more seriously, do not scale easily to low-voltage processes. We describe a digital technique which removes the accuracy constraints from the comparators. With no analog matching requirements, the comparators can be small, fast, and power efficient. A 6-bit prototype converter built in a standard 0.25-μm digital CMOS process occupies 1.2 mm2 and dissipates 150 mW from a 2.2-V supply at 400 MS/s 相似文献
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A modified RSD algorithm has been implemented in a switched-current pipelined A/D converter. The offset insensitivity of the RSD Converter reduces the effect of several nonidealities proper to current copier cells. Moreover, the benefits resulting from the large tolerances inherent to the RSD algorithm and the pipelined architecture result in an improved conversion rate. Measurements on a first prototype give an integral nonlinearity error less than 0.8 LSB for 10-bit accuracy. Power dissipation is 20 mW and silicon area is 2.5 mm2 . The measured sampling rate is 550 kS/s. It is an improvement by a factor of twenty compared to known equivalent CMOS switched-current converters. It is nevertheless still well below the predicted conversion rate of 4.5 MHz, which should be obtained once this A/D converter is integrated into an analog front-end. Full compatibility with standard digital technologies makes this kind of converter attractive for low power, medium-fast converters with 10-bit accuracy 相似文献
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《Solid-State Circuits, IEEE Journal of》1981,16(3):151-155
Describes a monolithic, fully parallel 5-bit A/D converter. The chip is fabricated using a standard metal-gate enhancement depletion NMOS technology with 7 /spl mu/m minimum features. The chip contains 31 strobed comparators, latches, combinational logic, a 5/spl times/31 bit ROM, TTL buffers and a 4-bit DAC. This makes it a building block for two-step parallel 8-bit A/D converters. Maximum conversion rate is 20 MHz and DC linearity is better than /SUP 1///SUB 4/ LSB for 80 mV quantization step size. 相似文献
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A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology is presented.The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter,which are based on well-designed calibration reference, calibration DAC and comparators.The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input. 相似文献
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《Electron Device Letters, IEEE》1980,1(5):92-94
The design and performance of a 6-bit superconducting A/D converter are described. The converter is based on double junction interferometers used as current comparators. The unique periodic response of these comparators makes possible a fully parallel N-bit converter requiring only N comparators. Conversion rates up to 2 × 109samples per second have been demonstrated. 相似文献
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Takashi Okuda Toshio Kumamoto Masao Ito Takahiro Miki Keisuke Okada Tadashi Sumi 《Analog Integrated Circuits and Signal Processing》1996,11(2):163-171
An 8- to 10-bit CMOS A/D converter with a conversion rate of more than 16 megasample/second is required in consumer video systems. Subranging architecture is widely used to realize such A/D converters. This architecture, however, exhibits a reference voltage error caused by resistor ladder loadings. The error has been discussed with respect to a flash A/D converter by Dingwall. However, it can not be applied for a subranging A/D converter as it is. The analysis of this error is very important in realizing the desired accuracy of a subranging A/D converter. This paper describes a static analysis to improve the linearity, and reports the results of this analysis for two typical types, one with individual comparator arrays for coarse and fine A/D conversions, and the other with the same comparator array for both conversions. This analysis makes it clear that a subranging A/D converter has unique saw-tooth characteristic in fine linearity errors. Furthermore, this analysis clarifies what conditions are necessary to achieve the desired accuracy. It is necessary, for example, that the product of the total input capacitance of the comparators C, the conversion rate f
sand the total ladder resistance R is less than 0.03 in A/D converters with individual comparator arrays and 0.016 in A/D converters with the same comparator array in order to achieve 10-bit accuracy. 相似文献
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《Solid-State Circuits, IEEE Journal of》1979,14(6):932-937
The design and measured performance of a fully parallel monolithic 8-bit A/D converter is reported. The required comparators and combining logic were designed and fabricated with a standard high-performance triple-diffused technology. A bipolar comparator circuit giving good performance with high input impedance is described. Circuit operation is reported at sample rates up to 30 megasamples per second (MS/s), with analog input signal power at frequencies up to 6 MHz. Full 8-bit linearity was achieved. An SNR of 42-44 dB was observed at input signal frequencies up to 5.3 MHz. 相似文献
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A gigahertz-sampling-rate flash A/D (analog/digital)-conversion LSI using high-speed Si bipolar technology (SST-1B) is investigated. To improve comparator speed, a circuit technology to minimize the comparator-speed limiting factors with minimum power is investigated and applied. To enhance the dynamic accuracy, speed mismatch among comparators is also minimized using this circuit technology. To improve encoder speed, a quasi-Gray code is adopted and glitch noise is reduced with this code. The LSI performance at 1-GHz sampling rate is measured with a gigahertz-operation data acquisition system developed with the SST MSI family, and effective bits of 5.8 at an input frequency of 100 MHz and 4.8 at 500 MHz are achieved. This LSI also demonstrates the feasibility of a single-chip flash A/D converter with a gigahertz sampling rate using Si bipolar technology 相似文献