NR Decoding Method for DTMB System

在分析国标数字电视传输系统NR编码的基础上,提出一种以节省硬件资源为目标的NR译码方法.首先根据DTMB系统中(16,8,6)NR编码关系式,推导出由衍生比特表示信息比特的生成关系式;进而,结合信息比特表示衍生比特的生成关系式、衍生比特表示信息比特的生成关系式和(16,8,6)NR码至多可以纠正2位误码的特点,通过逻辑分析,给出了NR译码方法;然后,根据译码方法,设计了硬件实现结构;最后,通过实例分析了本文方法的译码过程及可行性,并分析了硬件实现资源情况.本文方法能够达到(16,8,6)NR码纠2位误码的纠错极限,与传统的最大似然估计算法相比,实现简单,极大降低了译码器的复杂度,节省了硬件资源.     

高阶调制系统下LDPC码优化设计

为了提高编码调制系统的整体编码增益,提出一种高阶调制系统下LDPC码的度分布优化方法.根据高阶调制符号中不同比特的误比特特性,将调制符号所经历信道建模为一组对称二进制输入加性高斯信道.在此基础上,推导了高阶调制系统下LDPC码高斯近似密度进化分析方法,并得到译码收敛条件.结合度分布约束关系及译码收敛条件,提出高阶调制系统下LDPC码的度分布优化问题及差分进化实现方法.仿真结果表明,设计的LDPC码在高阶调制系统中的渐进性能和误码性能优于基于比特优化映射的编码调制方案.     

LDPC码的译码算法研究

根据硬件实现的要求,文中研究了LPDC码的译码算法,提出了适合硬件实现的NormaIized Min-Sum译码算法的系数,并在此基础上对该算法的量化范围和量化方案的性能进行了仿真分析,仿真结果表明均匀量化比特5,6和7的选择对于误码性能影响不大,该算法大大降低了计算复杂度和硬件实现难度,具有很好的实用价值.     

基于FPGA的多速率LDPC编码器和译码器设计与实现

低密度奇偶校验码(LDPC)因其性能逼近 Shannon 限而被广泛应用于通信系统。 为满足时变或有干扰的信道上可靠传输的通信要求,本文设计并实现了一种码长固定、码率灵活可变的 LDPC 码。利用近似下三角形式结构的校验矩阵直接编码,通过减少信息位和增加校验位, 实现不同码率的灵活切换。译码基于简化和积译码算法得到的归一化最小和算法,并采用部分并行译码形式,在保证译码效率同时,兼顾 FPGA 资源消耗。硬件实现采用 FPGA 实现码长 12960 比特,码率 2/3,1/3 和 1/6 的 LDPC 码。     

基于LDPC码的BICM系统性能分析和改进

将低密度奇偶校验码(LDPC)与比特交织编码调制(BICM)技术相结合,分别给出了不同码长LDPC码在16QAM调制方式下AWGN信道中的性能,并针对不同星座点对比特保护能力的差异,提出了一种有效的内置交织编码算法,即首先对LDPC编码后的码字进行相应的内置交织变换,然后将LDPC码中的信息位调制到星座点中保护能力强的比特位上,在译码端进行相应的矩阵变换译码,计算机仿真结果表明,新方案在信噪比较低时优于传统的16QAM调制方案。     

基于分布式奇偶校验码的低复杂度极化码SCLF译码算法

针对极化码串行抵消列表比特翻转(Successive Cancellation List Bit-Flip, SCLF)译码算法复杂度较高的问题,提出一种基于分布式奇偶校验码的低复杂度极化码SCLF译码(SCLF Decoding Algorithm for Low-Complexity Polar Codes Based on Distributed Parity Check Codes, DPC-SCLF)算法。与仅采用循环冗余校验(Cyclic Redundancy Check, CRC)码校验的SCLF译码算法不同,该算法首先利用极化信道偏序关系构造关键集,然后采用分布式奇偶校验(Parity Check, PC)码与CRC码结合的方式对错误比特进行检验、识别和翻转,提高了翻转精度,减少了重译码次数。此外,在译码时利用路径剪枝操作,提高了正确路径的竞争力,改善了误码性能,且利用提前终止译码进程操作,减少了译码比特数。仿真结果表明,与D-Post-SCLF译码算法和RCS-SCLF译码算法相比,所提出算法具有更低的译码复杂度且在中高信噪比下具有更好的误码性能。     

基于DTMB的NR解码器算法研究与FPGA实现

针对恶劣信道条件下最小汉明距算法判决效果较差的特点,提出了一种改进算法,与4QAM解映射相结合,应用于DTMB系统的NR解码模块。仿真结果表明,改良后的算法令系统性能提高了近1.5dB;另外,利用NR码字特点,硬件设计中采用对称实现,节约了近一半ROM;定系数乘法器采用CSD编码技术,以节省硬件资源。     

DVB—S简介（四）

3.3 卷积码编码和Viterbi译码 前面介绍的线形分组码是把k比特信息位加上n—k比特校验位组成n比特的码组(在非二进制分组码(比如R—S码)中,则是k个符号加上n—k个校验符组成n个符号输出),这n比特码符是当前     

高码率LDPC码译码器的优化设计与实现

本文以CCSDS推荐的7/8码率LDPC码为例,提出了一种适于高码率LDPC码译码器的硬件结构优化方法。高码率的LDPC码通常也伴随着行重与列重的比例较高的问题。本方法是在拆分校验矩阵的基础上,优化常用的部分并行译码结构,降低了高码率LDPC码译码时存在的校验节点运算单元(CNU)与变量节点运算单元(VNU)之间的复杂度不平衡,并由此提高了译码器的时钟性能。实验证明,本文方案提供的结构与常用的部分并行译码结构相比,节省硬件资源为41％;采用与本文方案相同的硬件资源而未经矩阵拆分的部分并行译码方案的码速率为本文方案的75％。     

一种带辅助译码比特的Polar码译码方法

在传统的Polar码译码的基础上,引入辅助译码比特,构造了一个辅助的Polar码字以提高译码性能。辅助比特由信道选择辅助窗口内的信息位决定。接收端如译码失败,将进行二次译码尝试。译码方案分两阶段进行：基于相同结构的扩展生成矩阵,将辅助译码比特译出;结合译出的辅助比特,对原码字进行译码,提高译码成功率。仿真结果显示,使用所提方法进行译码,其译码性能明显优于普通串行抵消译码方法;与两种传统的自动重传请求方案相比,能分别获得1 dB和1.9 dB的性能增益。     

一种简单分组码编、译码器的单片机实现方案

本论文给出了一种简单分组码-(7,4)汉明码编、译码器的单片机实现方案.在硬件实现上验证了(7,4)汉明码的纠一位随机错误能力和交织度为2时的纠两位突发错误的能力.     

Theoretical analysis of the error correction performance ofmajority-logic-like vector symbol codes

The average codeword success probability of the majority-logic-like vector symbol (MLLVS) code is derived for the following two cases: (1) single-pass decoding and (2) upper bound of multipass decoding, when the received word has more than (J-1) symbol errors, where J is the number of check sum equations. The MLLVS code has been simulated by Metzner (1996), and it was concluded that the average error correcting capability of MLLVS codes exceed the decoding capability of Reed-Solomon codes, but is achieved with less complexity. Additionally, for codes that have larger structures, the error correcting capability is sustained even further with a high probability of decoding success through multipass decoding procedures. The mathematical derivations of the error correction performance beyond (J-1) symbol errors serve as theoretical proof of the MLLVS code error correcting capability that was shown only through simulation results until now by Metzner. One characteristic feature of this derivation is that it does not assume any specific inner code usage, enabling the derived decoding probability equations to be easily applied to any inner code selected, of a concatenated coding structure     

一种差分高阶调制联合LDPC编码方案及其FPGA实现

针对复杂环境中通信系统误码率高和硬件实现复杂度高的问题,提出基于正交频分复用( Orthogonal Frequency Division Multiplexing, OFDM)时域差分和 16 进制幅度差分相移键控( 16 Multilevel Differential Amplitude and Phase Shi...     

DTMB中NR码软解码的实现

提出了一种有效的软输入软输出NR解码方法,可应用于地面数字电视广播传输标准(DTMB)中.其算法基于软输入的最大似然概率译码,使用最大相关码字和次最大相关码字产生输出软信息.经仿真验证,引入此方案的NR解码后,P8码率LDPC解码性能提高了约3.6 dB.     

一种新的IP网络视频通信丢包错误纠正方案

分组丢失是IP交换网络常见的现象。该文针对下一代网络多媒体通信,提出了一套IP网络抗分组丢失的方案。包括纠删编码、打包和发送以及接收端错误掩盖。与常见的纠删编码相比,该文提出的[9,5,3]码具有构造简单,编解码时间短,纠删能力高的优点。打包和发送方案根据[9,5,3]码的纠删性能对视频数据打包,并以一定顺序发送,提高了纠删码抗突发错误的能力。采用新的视频编码方案H.264所提供的抗误码工具灵活的宏块次序(FMO),对纠删失效的视频数据在解码端进行错误掩盖。     

A New Error Control Scheme for Hybrid ARQ Systems

This paper introduces the concept of a generalized hybrid ARQ (GH-ARQ) scheme for adaptive error control in digital communication systems. This technique utilizes the redundant information available upon successive retransmissions in an efficient manner so as to provide high throughput during poor channel conditions. A new class of linear codes is proposed for the GH-ARQ system application. The main feature of this class of codes is that the encoder/decoder configuration does not change as the length of the code is varied. As a result, the receiver uses the same decoder for decoding the received information after every retransmission while the error correcting capability of the code increases, thereby leading to an improved performance and minimum complexity for the overall system implementation.     

An Iteratively Decodable Tensor Product Code with Application to Data Storage

The error pattern correcting code (EPCC) can be constructed to provide a syndrome decoding table targeting the dominant error events of an inter-symbol interference channel at the output of the Viterbi detector. For the size of the syndrome table to be manageable and the list of possible error events to be reasonable in size, the codeword length of EPCC needs to be short enough. However, the rate of such a short length code will be too low for hard drive applications. To accommodate the required large redundancy, it is possible to record only a highly compressed function of the parity bits of EPCC?s tensor product with a symbol correcting code. In this paper, we show that the proposed tensor error-pattern correcting code (T-EPCC) is linear time encodable and also devise a low-complexity soft iterative decoding algorithm for EPCC?s tensor product with q-ary LDPC (T-EPCC-qLDPC). Simulation results show that T-EPCC-qLDPC achieves almost similar performance to single-level qLDPC with a 1/2 KB sector at 50% reduction in decoding complexity. Moreover, 1 KB T-EPCC-qLDPC surpasses the performance of 1/2 KB single-level qLDPC at the same decoder complexity.     

基于Logistic混沌序列的错误图样对纠错码的影响

为了在“比特级”层面对纠错码进行更深入的研究,提出了一种服从Logistic混沌序列的错误图样分布模型。通过将混沌序列映射成二进制序列,并采用一定的方法使序列中“1”的数目可控,以此来生成错误图样。将卷积码、RS码以及RS+卷积级联码作为研究对象,以随机错误为参照,分别研究了该错误图样下三者的译码性能。仿真结果表明,基于Logistic混沌序列的错误图样对卷积码和级联码的影响要大于随机错误图样,而随机错误图样对RS码的影响更大。     

Correction de deux paquets d’erreurs par un code de Reed-Solomon

Algebraic decoding procedures can be greatly simplified in case the number of errors being corrected is small. The authors present here a decoder which is capable of correcting errors occuring on four bits packets. The considered code is a (15, 11) Reed-Solomon code over GF (16). A Meggitttype decoder has been selected. The hardware implementation consists of 49 ttl (ls) packages and operates for the present at a rate of 5 Mbit/s. The utilisation of this decoding scheme is considered for other Reed-Solomon codes.     

Moment Balancing Templates: Constructions to Add Insertion/Deletion Correction Capability to Error Correcting or Constrained Codes

Templates are constructed to extend arbitrary additive error correcting or constrained codes, i.e., additional redundant bits are added in selected positions to balance the moment of the codeword. The original codes may have error correcting capabilities or constrained output symbols as predetermined by the usual communication system considerations, which are retained after extending the code. Using some number theoretic constructions in the literature, insertion/deletion correction can then be achieved. If the template is carefully designed, the number of additional redundant bits for the insertion/deletion correction can be kept small-in some cases of the same order as the number of parity bits in a Hamming code of comparable length.