Multi‐granular,multi‐purpose and multi‐Gb/s monitoring on off‐the‐shelf systems

As an attempt to make network managers’ life easier, we present M³Omon , a system architecture that helps to develop monitoring applications and perform network diagnosis. M³Omon behaves as an intermediate layer between the traffic and monitoring applications that provides advanced features, high performance and low cost. Such advanced features leverage a multi‐granular and multi‐purpose approach to the monitoring problem. Multi‐granular monitoring provides answers to tasks that use traffic aggregates to identify an event, and requires either flow records or packet data or even both to understand it and, eventually, take convenient countermeasures. M³Omon provides a simple API to access traffic simultaneously at several different granularities, i.e. packet‐level, flow‐level and aggregate statistics. The multi‐purposed design of M³Omon allows not only performing tasks in parallel that are specifically targeted to different traffic‐related purposes (e.g. traffic classification and intrusion detection) but also sharing granularities between applications, e.g. several concurrent applications fed from flow records that are provided by M³Omon . Finally, the low‐cost characteristic is brought by off‐the‐shelf systems (the combination of open‐source software and commodity hardware) and the high performance is achieved thanks to modifications in the standard NIC driver, low‐level hardware interaction, efficient memory management and programming optimization. Copyright © 2014 John Wiley & Sons, Ltd.     

Traffic pattern–based load‐balancing algorithm in software‐defined network using distributed controllers

Programmability and decoupling of the data plane and control plane in software‐defined networking (SDN) make the enterprise's network to focus on this new paradigm and to deploy their applications on it. Furthermore, supporting of distributed controllers in SDN opens the opportunities to address the limitations of centralized controller's architecture, which in turn improves the overall performance of the network. This study proposes a new load‐balancing algorithm to handle the load based on the traffic pattern specifically transmission control protocol (TCP) and user datagram protocol (UDP) traffic. Additionally, this study uses a distributed SDN controller's architecture to host the load balancer application. This study also employs a failover mechanism on the distributed architecture to achieve high‐availability environment and to ensure the redundancy and reliability of the network. The obtained results prove the effectiveness of the proposed algorithm in terms of availability, which is increased by 11%, response time is reduced by 98%, transaction rate is also increased by 258%, throughput is increased by 206%, concurrency is reduced by 63%, and packet loss is reduced by 86% while comparing with random, round‐robin, and weighted round‐robin algorithms in addition to ease the integration and deployment in distributed controllers.     

一种面向100Gbps网络的L7-filter硬件加速方法

L7-filter是当前广泛应用的流量分类系统,其采用基于正则表达式匹配的深包检测方法,通过检测数据包有效载荷中存在的字符串特征对流量进行分类.然而,由于计算复杂度高、存储消耗大等原因,现有L7-filter软硬件方法的处理性能严重不足,不能适应当前40Gbps以及更高性能骨干网络.在对L7-filter的应用层协议规则集进行分析,总结其中广泛存在的特征的基础上,本文提出了一个硬件加速方法,其通过有针对性的数据模型、算法优化、匹配架构设计以提高流量分类系统的处理能力.为了验证方法的可行性,采用了基于Virtex6的FPGA板卡实现原型系统并对其进行评估.实验结果表明,原型系统的数据吞吐率可以达到约115Gbps.     

Quality‐of‐Service Mechanisms for Flow‐Based Routers

In this paper, we propose quality of service mechanisms for flow‐based routers which have to handle several million flows at wire speed in high‐speed networks. Traffic management mechanisms are proposed for guaranteed traffic and non‐guaranteed traffic separately, and then the effective harmonization of the two mechanisms is introduced for real networks in which both traffic types are mixed together. A simple non‐work‐conserving fair queuing algorithm is proposed for guaranteed traffic, and an adaptive flow‐based random early drop algorithm is proposed for non‐guaranteed traffic. Based on that basic architecture, we propose a dynamic traffic identification method to dynamically prioritize traffic according to the traffic characteristics of applications. In a high‐speed router system, the dynamic traffic identification method could be a good alternative to deep packet inspection, which requires handling of the IP packet header and payload. Through numerical analysis, simulation, and a real system experiment, we demonstrate the performance of the proposed mechanisms.     

Low‐cost and high‐performance: VoIP monitoring and full‐data retention at multi‐Gb/s rates using commodity hardware

Voice over IP (VoIP) is increasingly replacing the old public switched telephone network (PSTN) technology. In this new scenario, there are several challenges for VoIP providers. First, VoIP requires a detailed monitoring of both users' quality of service (QoS) and experience (QoE) to a greater extent than in traditional PSTNs. Second, such a monitoring process must be able to track VoIP traffic in high‐speed networks, nowadays typically of multi‐Gb/s rates. Third, recent government directives require that providers retain information from their users' calls. Similarly, the convergence of data and voice services allows operators to provide new services such as full‐data retention, in which users' calls can be recorded for either quality assessment (call centers, QoE) or security purposes (lawful interception). This implies a significant investment in infrastructure, especially in large‐scale networks which require multiple points of measurement and redundancy. This paper proposes a novel methodology, architecture and system to fulfill such challenges, called VoIPCallMon, as well as the data structures and necessary hardware‐tuning knowledge for its development. As distinguishing features, VoIPCallMon provides very high performance, being able to process VoIP traffic on‐the‐fly at high bitrates, novel services and significant cost reduction by using commodity hardware with minimal interference with operational VoIP networks. The performance evaluation shows that the system copes with the VoIP load of real‐world operators. We further evaluated the system performance at a fully saturated 10 Gb/s link and no packet loss was reported, therefore demonstrating the potential of commodity hardware solutions. Copyright © 2014 John Wiley & Sons, Ltd.     

Separating VNF and Network Control for Hardware‐Acceleration of SDN/NFV Architecture

A hardware‐acceleration architecture that separates virtual network functions (VNFs) and network control (called HSN) is proposed to solve the mismatch between the simple flow steering requirements and strong packet processing abilities of software‐defined networking (SDN) forwarding elements (FEs) in SDN/network function virtualization (NFV) architecture, while improving the efficiency of NFV infrastructure and the performance of network‐intensive functions. HSN makes full use of FEs and accelerates VNFs through two mechanisms: (1) separation of traffic steering and packet processing in the FEs; (2) separation of SDN and NFV control in the FEs. Our HSN prototype, built on NetFPGA‐10G, demonstrates that the processing performance can be greatly improved with only a small modification of the traditional SDN/NFV architecture.     

Analysis of Distributed DDQ for QoS Router

In a packet switching network, congestion is unavoidable and affects the quality of real‐time traffic with such problems as delay and packet loss. Packet fair queuing (PFQ) algorithms are well‐known solutions for quality‐of‐service (QoS) guarantee by packet scheduling. Our approach is different from previous algorithms in that it uses hardware time achieved by sampling a counter triggered by a periodic clock signal. This clock signal can be provided to all the modules of a routing system to get synchronization. In this architecture, a variant of the PFQ algorithm, called digitized delay queuing (DDQ), can be distributed on many line interface modules. We derive the delay bounds in a single processor system and in a distributed architecture. The definition of traffic contribution improves the simplicity of the mathematical models. The effect of different time between modules in a distributed architecture is the key idea for understanding the delay behavior of a routing system. The number of bins required for the DDQ algorithm is also derived to make the system configuration clear. The analytical models developed in this paper form the basis of improvement and application to a combined input and output queuing (CIOQ) router architecture for a higher speed QoS network.     

Packet‐level‐based traffic aggregation to optimize NDN content delivery

In recent years, named data networking (NDN) has been accepted as the most popular future paradigm and attracted much attention, of which the routing model contains interest forwarding and content delivery. However, interest forwarding is far from the bottleneck of routing optimization; instead, the study on content delivery can greatly promote routing performance. Although many proposals on content delivery have been investigated, they have not considered packet‐level caching and deep traffic aggregation, which goes against the performance optimization of content delivery. In this paper, we propose a packet‐level‐based traffic aggregation (PLTA) scheme to optimize NDN content delivery. At first, the packet format is devised, and data plane development kit (DPDK) is used to ensure same size for each packet. Then, the whole delivery scheme with traffic aggregation consideration is presented. The simulation is driven by the real YouTube dataset over Deltacom, NSFNET, and CERNET topologies, and the experimental results demonstrate that the proposed PLTA has better delivery performance than three baselines in terms of cache hit ratio, delivery delay, network load, and energy efficiency.     

A Novel Scalable and Storage‐Efficient Architecture for High Speed Exact String Matching

String matching is a fundamental element of an important category of modern packet processing applications which involve scanning the content flowing through a network for thousands of strings at the line rate. To keep pace with high network speeds, specialized hardware‐based solutions are needed which should be efficient enough to maintain scalability in terms of speed and the number of strings. In this paper, a novel architecture based upon a recently proposed data structure called the Bloomier filter is proposed which can successfully support scalability. The Bloomier filter is a compact data structure for encoding arbitrary functions, and it supports approximate evaluation queries. By eliminating the Bloomier filter's false positives in a space efficient way, a simple yet powerful exact string matching architecture is proposed that can handle several thousand strings at high rates and is amenable to on‐chip realization. The proposed scheme is implemented in reconfigurable hardware and we compare it with existing solutions. The results show that the proposed approach achieves better performance compared to other existing architectures measured in terms of throughput per logic cells per character as a metric.     

Architecture design,performance analysis and VLSI implementation of a reconfigurable shared buffer for high‐speed switch/router

Modern switches and routers require massive storage space to buffer packets. This becomes more significant as link speed increases and switch size grows. From the memory technology perspective, while DRAM is a good choice to meet capacity requirement, the access time causes problems for high‐speed applications. On the other hand, though SRAM is faster, it is more costly and does not have high storage density. The SRAM/DRAM hybrid architecture provides a good solution to meet both capacity and speed requirements. From the switch design and network traffic perspective, to minimize packet loss, the buffering space allocated for each switch port is normally based on the worst‐case scenario, which is usually huge. However, under normal traffic load conditions, the buffer utilization for such configuration is very low. Therefore, we propose a reconfigurable buffer‐sharing scheme that can dynamically adjust the buffering space for each port according to the traffic patterns and buffer saturation status. The target is to achieve high performance and improve buffer utilization, while not posing much constraint on the buffer speed. In this paper, we study the performance of the proposed buffer‐sharing scheme by both a numerical model and extensive simulations under uniform and non‐uniform traffic conditions. We also present the architecture design and VLSI implementation of the proposed reconfigurable shared buffer using the 0.18 µm CMOS technology. Our results manifest that the proposed architecture can always achieve high performance and provide much flexibility for the high‐speed packet switches to adapt to various traffic patterns. Furthermore, it can be easily integrated into the functionality of port controllers of modern switches and routers. Copyright © 2008 John Wiley & Sons, Ltd.     

Scalable Network Architecture for Flow‐Based Traffic Control

Many control schemes have been proposed for flow‐level traffic control. However, flow‐level traffic control is implemented only in limited areas such as traffic monitoring and traffic control at edge nodes. No clear solution for end‐to‐end architecture has been proposed. Scalability and the lack of a business model are major problems for deploying end‐to‐end flow‐level control architecture. This paper introduces an end‐to‐end transport architecture and a scalable control mechanism to support the various flow‐level QoS requests from applications.     

Performance analysis and hardware implementation of a nearly optimal buffer management scheme for high‐performance shared‐memory switches

Burst traffic is a common traffic pattern in modern IP networks, and it may lead to the unfairness problem and seriously degrade the performance of switches and routers. From the perspective of switching mechanism, the majority of commercial switches adopt the on‐chip shared‐memory switching architecture, and high‐speed packet buffer with efficient queue management is required to deal with the unfairness and congestion problem. In this paper, the performance of a shared‐private buffer management scheme is analyzed in detail. In the proposed scheme, the total memory space is split into shared area and private area. Each output port has a private memory area that cannot be used by other ports. The shared area is completely shared among all output ports. A theoretical queuing model of the proposed scheme is formulated, and closed‐form formulas for multiple performance parameters are derived. Through the numerical studies, we demonstrate that a nearly optimal buffer partition policy can be obtained by setting an equally small amount of private area for each queue. This work is validated by simulations as well as hardware experiments. Software simulations show that the proposed scheme performs better than existing methods, and packet dropping caused by burst traffic can be significantly reduced. Besides, a prototype of the buffer management module is implemented and evaluated in field programmable gate array platform. The evaluation shows that the proposed scheme can ensure the efficiency and fairness while keeping a high throughput in real workload.     

Real‐time and fine‐grained network monitoring using in‐band network telemetry

In the modern era of software‐defined networking (SDN), network monitoring is becoming more important for providing information about a network and helping SDN controllers to make decisions about the network. In‐band Network Telemetry (INT) is a new network monitoring framework that collects packet‐level network information to provide real‐time and fine‐grained network monitoring. In this paper, we present the design of the overall INT management architecture and its two main components: the INT management system and INTCollector. The INT management system controls heterogeneous INT‐capable devices through a common interface. INTCollector is a high‐performance collector for INT data, which uses eXpress Data Path and an event detection mechanism. The evaluation result shows that INTCollector processes telemetry reports 27 times faster than other packet‐level telemetry collectors. We made the implementation as open source, to make researchers who are interested in INT implement their own ideas on top of our work.     

Reconfigurable Architecture for Network Flow Analysis

This paper describes a reconfigurable architecture based on field-programmable gate-array (FPGA) technology for monitoring and analyzing network traffic at increasingly high network data rates. Our approach maps the performance-critical tasks of packet classification and flow monitoring into reconfigurable hardware, such that multiple flows can be processed in parallel. We explore the scalability of our system, showing that it can support flows at multi-gigabit rate; this is faster than most software-based solutions where acceptable data rates are typically no more than 100 million bits per second.     

Performance of delay‐sensitive traffic in multi‐layered satellite IP networks with on‐board processing capability

In this article, performance of delay‐sensitive traffic in multi‐layered satellite Internet Protocol (IP) networks with on‐board processing (OBP) capability is investigated. With OBP, a satellite can process the received data, and according to the nature of application, it can decide on the transmission properties. First, we present a concise overview of relevant aspects of satellite networks to delay‐sensitive traffic and routing. Then, in order to improve the system performance for delay‐sensitive traffic, specifically Voice over Internet Protocol (VoIP), a novel adaptive routing mechanism in two‐layered satellite network considering the network's real‐time information is introduced and evaluated. Adaptive Routing Protocol for Quality of Service (ARPQ) utilizes OBP and avoids congestion by distributing traffic load between medium‐Earth orbit and low‐Earth orbit layers. We utilize a prioritized queueing policy to satisfy quality‐of‐service (QoS) requirements of delay‐sensitive applications while evading non‐real‐time traffic suffer low performance level. The simulation results verify that multi‐layered satellite networks with OBP capabilities and QoS mechanisms are essential for feasibility of packet‐based high‐quality delay‐sensitive services which are expected to be the vital components of next‐generation communications networks. Copyright © 2007 John Wiley & Sons, Ltd.     

A topology and application‐aware relay path allocation scheme in multipath transport system based on application‐level relay

The ever‐increasing transmission requirements of quality of service (QoS)‐sensitive applications, especially real‐time multimedia applications, can hardly be met by the single path routing protocols. Multipath transmission mechanism is a feasible approach to provide QoS for various applications. On the basis of the general framework of multipath transport system based on application‐level relay, we present a relay path allocation scheme, whose goal is to select suitable relay paths, while balancing the overlay traffic among the different domains and relayers. With the application‐layer traffic optimization service under the standardization within the Internet Engineering Task Force (IETF), the controller has the topology‐aware ability to allocate relay paths with excellent routing performance. To further develop the universality of our method, the controller perceives transmission performance of relay overlay network through relayers' performance detection processes and, thus, has the application‐aware ability to allocate relay paths with excellent transmission performance for different applications by consulting application‐specific transmission metrics. Simulation results demonstrate that the proposed relay path allocation algorithm performs well in allocating superior relay paths and can balance the distribution of overlay traffic across domains in different network situations.     

QoS‐based radio network dimensioning for LTE networks with heavy real‐time traffic

Applications of video streaming and real‐time gaming, which generate large amounts of real‐time traffic in the network, are expected to gain considerable popularity in Long Term Evolution networks. Maintaining the QoS such as packet delay, packet loss ratio, median, and cell border throughput requirements in networks dominated by real time traffic, is critical. The existing dimensioning methodology does not consider QoS parameters of real‐time traffic in network dimensioning. Moreover, exhaustive and time‐consuming simulations are normally required to evaluate the performance and QoS of real‐time services. To overcome this problem, we propose an improved radio network dimensioning framework that considers the QoS of real‐time traffic in network dimensioning. In this framework, an analytical model is proposed to evaluate the capacity and performance of real‐time traffic dominant Long Term Evolution networks. The proposed framework provides a fast and accurate means of finding the trade‐off between system load, packet delay, packet loss ratio, required median, and cell border throughput. It also provides network operators with an analytical means for obtaining the minimum number of sites required by jointly considering coverage, capacity and QoS requirements. The accuracy of the proposed model is validated through simulations. Copyright © 2012 John Wiley & Sons, Ltd.     

Pipelined Scheduling of Functional HW/SW Modules for Platform‐Based SoC Design

We developed a pipelined scheduling technique of functional hardware and software modules for platform‐based system‐on‐a‐chip (SoC) designs. It is based on a modified list scheduling algorithm. We used the pipelined scheduling technique for a performance analysis of an MPEG4 video encoder application. Then, we applied it for architecture exploration to achieve a better performance. In our experiments, the modified SoC platform with 6 pipelines for the 32‐bit dual layer architecture shows a 118% improvement in performance compared to the given basic SoC platform with 4 pipelines for the 16‐bit single‐layer architecture.     

LRP: Link quality‐aware queue‐based spectral clustering routing protocol for underwater acoustic sensor networks

Recently, underwater acoustic sensor networks (UASNs) have been considered as a promising approach for monitoring and exploring the oceans in lieu of traditional underwater wireline instruments. As a result, a broad range of applications exists ranging from oil industry to aquaculture and includes oceanographic data collection, disaster prevention, offshore exploration, assisted navigation, tactical surveillance, and pollution monitoring. However, the unique characteristics of underwater acoustic communication channels, such as high bit error rate, limited bandwidth, and variable delay, lead to a large number of packet drops, low throughput, and significant waste of energy because of packets retransmission in these applications. Hence, designing an efficient and reliable data communication protocol between sensor nodes and the sink is crucial for successful data transmission in underwater applications. Accordingly, this paper is intended to introduce a novel nature‐inspired evolutionary link quality‐aware queue‐based spectral clustering routing protocol for UASN‐based underwater applications. Because of its distributed nature, link quality‐aware queue‐based spectral clustering routing protocol successfully distributes network data traffic load evenly in harsh underwater environments and avoids hotspot problems that occur near the sink. In addition, because of its double check mechanism for signal to noise ratio and Euclidean distance, it adopts opportunistically and provides reliable dynamic cluster‐based routing architecture in the entire network. To sum up, the proposed approach successfully finds the best forwarding relay node for data transmission and avoids path loops and packet losses in both sparse and densely deployed UASNs. Our experimental results obtained in a set of extensive simulation studies verify that the proposed protocol performs better than the existing routing protocols in terms of data delivery ratio, overall network throughput, end‐to‐end delay, and energy efficiency.     

Rate Proportional SCFQ Algorithm for High‐Speed Packet‐Switched Networks

Self‐Clocked Fair Queueing (SCFQ) algorithm has been considered as an attractive packet scheduling algorithm because of its implementation simplicity, but it has unbounded delay property in some input traffic conditions. In this paper, we propose a Rate Proportional SCFQ (RP‐SCFQ) algorithm which is a rate proportional version of SCFQ. If any fair queueing algorithm can be categorized into the rate proportional class and input is constrained by a leaky bucket, its delay is bounded and the same as that of Weighted Fair Queueing (WFQ) which is known as an optimal fair queueing algorithm. RP‐SCFQ calculates the timestamps of packets arriving during the transmission of a packet using the current value of system potential updated at every packet departing instant and uses a starting potential when it updates the system potential. By doing so, RP‐SCFQ can have the rate proportional property. RP‐SCFQ is appropriate for high‐speed packet‐switched networks since its implementation complexity is low while it guarantees the bounded delay even in the worst‐case input traffic conditions.