低压功率VDMOS的结构设计研究

对功率集成电路中耐压为60V,电流容量为2．5A的VDMOS进行了设计和仿真。在理论计算的基础上,分析了外延参数和单胞尺寸结构的设计优化方法。通过ISETCAD器件仿真软件,得出相关数据和终端结构,进而借助L-edit完成最终版图结构。     

半导体放电管多元胞结构模型

在半导体放电管的版面设计上提出了多元胞结构版图 .对多元胞结构“短路模型”进行了理论分析和实验验证 ,结果表明合理设计多元胞版图尺寸和 P基区薄层电阻可以改善器件的转折导通特性和提高器件的抗雷电浪涌能力 ,从而为简化半导体放电管生产工艺提供了依据     

S波段大功率、高效率GaN HEMT器件研究

基于国产的SiC衬底GaN外延材料,研制出大栅宽GaN HEMT单胞管芯。通过使用源牵引和负载牵引技术仿真出所设计模型器件的输入输出阻抗,推导出本器件所用管芯的输入输出阻抗。使用多节λ/4阻抗变换线设计了宽带Wilkinson功率分配/合成器,对原理图进行仿真,优化匹配网络的S参数,对生成版图进行电磁场仿真,通过LC T型网络提升管芯输入输出阻抗。采用内匹配技术,成功研制出铜-钼-铜结构热沉封装的四胞内匹配GaN HEMT。在频率为2.7～3.5 GHz、脉宽为3 ms、占空比为50%、栅源电压Vgs为-3 V和漏源电压Vds为28 V下测试器件,得到最大输出功率Pout大于100 W(50 dBm),PAE大于47%,功率增益大于13 dB。     

半导体放电管多元胞结构模型

在半导体放电管的版面设计上提出了多元胞结构版图.对多元胞结构“短路模型”进行了理论分析和实验验证,结果表明合理设计多元胞版图尺寸和P基区薄层电阻可以改善器件的转折导通特性和提高器件的抗雷电浪涌能力,从而为简化半导体放电管生产工艺提供了依据.     

X波段高输出功率凹栅AlGaN/GaN HEMT

使用自主研制的SiC衬底GaN HEMT外延材料,研制出高输出功率AlGaN/GaN HEMT,优化了器件研制工艺,比接触电阻率小于1.0×10-6Ω·cm2,电流崩塌参量小于10%,击穿电压大于80V.小栅宽器件工作电压达到40V,频率为8GHz时输出功率密度大于10W/mm.栅宽为2mm单胞器件,工作电压为28V,频率为8GHz时,输出功率为12.3W,功率增益为4.9dB,功率附加效率为35%.四胞内匹配总栅宽为8mm器件,工作电压为27V时,频率为8GHz时,输出功率为33.8W,功率增益为6.3dB,功率附加效率为41.77%,单胞器件和内匹配器件输出功率为目前国内该器件输出功率的最高结果.     

X波段高输出功率凹栅AlGaN/GaN HEMT

使用自主研制的SiC衬底GaN HEMT外延材料,研制出高输出功率AlGaN/GaN HEMT,优化了器件研制工艺,比接触电阻率小于1.0×10-6Ω·cm2,电流崩塌参量小于10%,击穿电压大于80V.小栅宽器件工作电压达到40V,频率为8GHz时输出功率密度大于10W/mm.栅宽为2mm单胞器件,工作电压为28V,频率为8GHz时,输出功率为12.3W,功率增益为4.9dB,功率附加效率为35%.四胞内匹配总栅宽为8mm器件,工作电压为27V时,频率为8GHz时,输出功率为33.8W,功率增益为6.3dB,功率附加效率为41.77%,单胞器件和内匹配器件输出功率为目前国内该器件输出功率的最高结果.     

基于SKILL语言的参数化抗辐射器件版图设计

SKILL语言是IC设计业界采用的主要软件Cadence EDA提供的编程开发语言,用户可以基于SKILL语言对EDA设计环境进行定制设计或拓展。参数化单元(Parameter Cell,PCELL)可以根据设计规则(Design Rule)通过器件的W、L等参数实现对器件版图层次(Layer)的控制。另一方面抗辐射器件版图的特殊设计形式对版图设计工作提出了新的要求。阐述了通过SKILL语言实现的一款参数化抗辐射器件版图的设计理念和方法,并且在Cadence Design Framework(DFII)中编译调试和优化,实现了该版图的结构,较大幅度地提高了版图设计工作的效率。     

毫米波AlGaN / GaN HEMT 交流特性研究

毫米波频段已经成为AlGaN/GaN HEMT研究的一个发展趋势。利用器件仿真软件TCAD,对AlGaN/GaN HEMT交流特性进行了研究。从势垒层的Al组分和厚度两个参数分析了器件特征频率变化趋势。用TCAD仿真得到的AlGaN/GaN HEMT器件本征S参数,在ADS中添加器件的非本征参数,得到器件仿真的频率特性。在器件设计的基础上,进行了器件版图设计和流片,并测量了器件频率特性。测试和仿真结果的对比表明两者较为一致,表明器件仿真的有效性和指导意义。     

CMOS/SOS器件长期可靠性试验

用本所研制的CMOS/SOS器件作了两项试验,即CMOS/SOS4012长期可靠性试验和不同版图设计、不同器件工艺研制的CMOS/SOS长期可靠性对比试验。试验结果表明:不同版图设计和器件工艺对CMOS/SOS器件可靠性有较大的影响;改进了版图和器件工艺研制的CMOS/SOS器件达到了较高的可靠性;不同栅介质结构的CMOS/SOS器件在高温加电运行中,阈值电压的变化是不同的。     

版图结构对MOS器件总剂量辐照特性的影响

在商用标准0.6μm体硅CMOS工艺下,设计了采用普通单栅及多栅版图结构的nMOS和pMOS晶体管作为测试样品,讨论其经过γ射线照射后的总剂量辐照特性.辐照中器件采用不同电压偏置,并在辐照前后对器件的源漏极间泄漏电流、阈值电压漂移及跨导特性进行测量.研究表明nMOS总剂量效应对器件的版图结构非常敏感,而pMOS的总剂量效应几乎不受版图结构的影响.     

Comparisons of Design and Yield for Large-Area 10-kV 4H-SiC DMOSFETs

Three large-area 10-kV 4H-SiC DMOSFET designs are compared with respect to their design, die area, breakdown yield, and ON-state yield. The largest of these DMOSFETs had 0.62 $hbox{cm}^{2}$ of active area on a 1- $hbox{cm}^{2}$ die, with a 10-kV device producing 40 A at a gate field of 3 MV/cm. Two designs used linear interdigitated fingers, whereas the third design used a square cell layout. The linear interdigitated finger design proved to be more robust, with higher yields than the square cell geometry. It was determined that the square cell design was yield limited due to the impact of wafer bow and total thickness variations on photolithographic accuracy, making the square cell geometry less attractive for large-area 4H-SiC DMOSFETs.      

Performance of n+-p silicon solar cells in concentrated sunlight

Performance data for n⁺-p silicon solar cells operating at illuminations up to 90 suns (9 W/cm²) and temperatures up to 100°C are presented. Experimental results for 2-cm²cells with different base resistivities are compared to performances predicted by a numerical device analysis computer code. Excellent agreement between numerical simulation and experiment is observed. For the illumination levels considered, an optimum base resistivity of approximately 0.3 Ω. cm is predicted by the numerical analyses and verified experimentally. The 0.3-Ω. cm cells exhibit conversion efficiencies above 11.8 percent up to 90 suns with a peak efficiency of 14 percent at approximately 30 suns. Preliminary results for a large-area (15.2 cm²) circular cell design are also presented for illuminations up to 60 suns. A peak conversion efficiency of 13.5 percent is measured for this cell at ∼25 suns.     

Characteristics and Optimum Operating Parameters of a Gyrotron Traveling Wave Amplifier

Characteristics and optimum operating parameters are determined for a new type of high-power high-efficiency generator of millimeter waves known as a gyrotron traveling wave amplifier. In the example consided, wave amplification results from the interaction of a TE/sub 01/ waveguide mode with the fundamental cyclotron harmonic of an electron beam. The parameter optimization involves the determination of the point of maximum device efficiency as a function of beam density, beam energy, beam positioning, and external magnetic field for the output power required. An analytical linear theory and a numerical simulation code form the basis of theoretical calculations. As a result of the extensive survey in parameter space, the peak efficiency in the beam frame has been found to exceed 70 percent. This result has been applied to the specific design of a 35-GHz amplifier with output power ~340 kW, a power gain of 2 dB/cm, and a laboratory frame efficiency of 51 percent.     

Area efficient layout design of CMOS circuit for high-density ICs

Efficient layouts have been an active area of research to accommodate the greater number of devices fabricated on a given chip area. In this work a new layout of CMOS circuit is proposed, with an aim to improve its electrical performance and reduce the chip area consumed. The study shows that the design of CMOS circuit and SRAM cells comprising tapered body reduced source fully depleted silicon on insulator (TBRS FD-SOI)-based n- and p-type MOS devices. The proposed TBRS FD-SOI n- and p-MOSFET exhibits lower sub-threshold slope and higher I_on to I_off ratio when compared with FD-SOI MOSFET and FinFET technology. Other parameters like power dissipation, delay time and signal-to-noise margin of CMOS inverter circuits show improvement when compared with available inverter designs. The above device design is used in 6-T SRAM cell so as to see the effect of proposed layout on high density integrated circuits (ICs). The SNM obtained from the proposed SRAM cell is 565 mV which is much better than any other SRAM cell designed at 50 nm gate length MOS device. The Sentaurus TCAD device simulator is used to design the proposed MOS structure.     

Operational-amplifier compilation with performance optimization

A method for designing analog circuits in which topological design is followed by simultaneous device sizing and layout design is described. By merging circuit and layout design into a single design process, analog circuits can be optimally designed taking layout parasitics fully into account. Using the method, a CMOS operational-amplifier compiler (OAC) has been developed. Given a set of performance specifications and process parameters, OAC generates a layout with circuit performance optimized to meet specified performance constraints. A procedural layout technique is employed to generate a compact and practical layout. A nonlinear optimization method for device sizing which relies on the results of simulations based on the circuit extracted from the layout is applied. Design experiments have shown that OAC can produce satisfactory results with respect to both circuit performance and layout density     

9μm截止波长128×128 AlGaAs/GaAs量子阱红外焦平面探测器阵列

报道了128×128 AlGaAs/GaAs量子阱红外焦平面探测器阵列的设计和制作.采用金属有机化学气相淀积外延技术生长外延材料,并在GaAs集成电路工艺线上完成工艺制作.为得到器件参数,设计制作了台面尺寸为300μm×300μm的大面积测试器件;77K下2V偏压时暗电流密度为1.5×10-3A/cm2;80K工作温度下,器件峰值响应波长为8.4μm,截止波长为9μm,黑体探测率DB 为3.95×108(cm·Hz1/2)/W.将128×128元 AlGaAs/GaAs量子阱红外焦平面探测器阵列芯片与相关CMOS读出电路芯片倒装焊互连,在80K工作温度下实现了室温环境目标的红外热成像,盲元率小于1%.     

Selectively silicided vertical power DMOSFETs for high-frequency power conversion

A 50 V, 0.56 m Omega cm/sup 2/ vertical power DMOSFET fabricated using selectively silicided gate and source contact regions is reported. The gate-source isolation was provided by anisotropically etched oxide sidewall spacers. This new device structure lowers the source contact resistance considerably by providing a larger contact area and improves the distributed gate RC propagation delay by lowering the gate sheet resistance compared with the conventional heavily doped n/sup +/-polysilicon gates. Devices with cell density as high as 8 million cells/inch/sup 2/ and die size as large as 200 mil*220 mil and capable of conducting more than 160 A of current have been successfully fabricated with excellent gate yield. These results represent the highest reported forward conductivities for any type of power FET in the 50 V reverse blocking range.<>     

Design of 100‐V Super‐Junction Trench Power MOSFET with Low On‐Resistance

Power metal‐oxide semiconductor field‐effect transistor (MOSFET) devices are widely used in power electronics applications, such as brushless direct current motors and power modules. For a conventional power MOSFET device such as trench double‐diffused MOSFET (TDMOS), there is a tradeoff relationship between specific on‐state resistance and breakdown voltage. To overcome the tradeoff relationship, a super‐junction (SJ) trench MOSFET (TMOSFET) structure is studied and designed in this letter. The processing conditions are proposed, and studies on the unit cell are performed for optimal design. The structure modeling and the characteristic analyses for doping density, potential distribution, electric field, width, and depth of trench in an SJ TMOSFET are performed and simulated by using of the SILVACO TCAD 2D device simulator, Atlas. As a result, the specific on‐state resistance of 1.2 mΩ‐cm² at the class of 100 V and 100 A is successfully optimized in the SJ TMOSFET, which has the better performance than TDMOS in design parameters.     

An Efficient Thermal Design Method Based on Boundary Condition Modeling

Until recently, layout design methods for electronic devices such as large scale integration circuits (LSIs) have been considered strictly from the viewpoint of electrical circuit design. In the near future, however, electronic system design will also require thermal design as well. Current thermal layout design is treated as power distribution in electrical layout design. But, evaluation of thermal design is not power density. That is a temperature of the chip. In the process, the designer faces problems. Evaluation of temperature needs the thermal analysis. And, the thermal analysis is slower than electrical evaluation. This, in turn, accentuates the need to accelerate thermal analysis and design methods. We have been investigating a novel high-speed thermal management method for the upper-stream of electronic device layout design on modules when the designer is interested in narrowing down possible design solutions. This method has four features, i.e., 1) division of elements on modules by the boundary conditions, 2)high-speed thermal analysis (10-$mu$s order), 3) division of design by inter-module boundary conditions to three design layers, and 4)automatic identification of regions in design space that satisfy the design constraints. As an illustration, we performed a layout design of a board with four device modules mounted on top with 16 design parameters. Our method achieves the very fast design time (150 s) with 4$ast hbox10^5$analysis.