A Low-Cost Serial Decoder Architecture for Low-Density Parity-Check Convolutional Codes

We propose a low-cost serial decoder architecture for low-density parity-check convolutional codes (LDPC-CCs). It has been shown that LDPC-CCs can achieve comparable performance to LDPC block codes with constraint length much less than the block length. The proposed serial decoder architecture for LDPC-CCs uses a single decoding processor. Terminated data frames are sent through the processor iteratively until correctly decoded or a maximum number of iterations is reached. This architecture saves memory consumption and uses a very small number of logic elements, making it especially suitable for strong LDPC-CCs with large code memory. The proposed architecture is realized for a (2048,3,6) regular LDPC-CC on an Altera Stratix FPGA. With a maximum of 100 iterations, the design achieves up to 9-Mb/s throughput using only a very small portion of the field-programmable gate array resources.      

截断式原模图低密度奇偶校验卷积码边扩展优化

截断式原模图低密度奇偶校验(LDPC)卷积码(P-LDPC-CCs)结合了原模图LDPC(P-LDPC)码和卷积码的特点,具有多变的编码构造方式和优异的纠错性能,实现了编译码低时延特性.边扩展作为构造截断式原模图LDPC卷积码基础矩阵关键步骤,是影响其性能的重要因素.该文提出了一种边扩展优化方法.该方法利用原模图外信息转移(P-EXIT)算法理论分析基础矩阵的译码门限,引入差分进化思想搜索一定条件下最优的边扩展方式.理论分析与系统仿真结果均表明所提边扩展优化方法比现有的方法具有更好的性能.     

截断式原模图低密度奇偶校验卷积码边扩展优化

截断式原模图低密度奇偶校验(LDPC)卷积码(P-LDPC-CCs)结合了原模图LDPC (P-LDPC)码和卷积码的特点,具有多变的编码构造方式和优异的纠错性能,实现了编译码低时延特性。边扩展作为构造截断式原模图LDPC卷积码基础矩阵关键步骤,是影响其性能的重要因素。该文提出了一种边扩展优化方法。该方法利用原模图外信息转移(P-EXIT)算法理论分析基础矩阵的译码门限,引入差分进化思想搜索一定条件下最优的边扩展方式。理论分析与系统仿真结果均表明所提边扩展优化方法比现有的方法具有更好的性能。     

Reversible Low-Density Parity-Check Codes

Low-density parity-check (LDPC) codes may be decoded using a circuit implementation of the sum-product algorithm which maps the factor graph of the code. By reusing the decoder for encoding, both tasks can be performed using the same circuit, thus reducing area and verification requirements. Motivated by this, iterative encoding techniques based upon the graphical representation of the code are proposed. Code design constraints which ensure encoder convergence are presented, and then used to design iteratively encodable codes, while also preventing 4-cycle creation. We show how the Jacobi method for iterative matrix inversion can be applied to finite field matrices, viewed as message passing, and employed as the core of an iterative encoder. We present an algebraic construction of 4-cycle free iteratively encodable codes using circulant matrices. Analysis of these codes identifies a weakness in their structure, due to a repetitive pattern in the factor graph. The graph supports pseudo-codewords of low pseudo-weight. In order to remove the repetitive pattern in the graph, we propose a recursive technique for generating iteratively encodable codes. The new codes offer flexibility in the choice of code length and rate, and performance that compares well to randomly generated, quasi-cyclic and extended Euclidean-geometry codes.     

Belief-Propagation-Approximated Decoding of Low-Density Parity-Check Codes

In this paper, we propose a new reduced-complexity decoding algorithm of Low-Density Parity-Check (LDPC) codes, called Belief-Propagation-Approximated (BPA) algorithm, which utilizes the idea of normalization and translates approximately the intricate nonlinear operation in the check nodes of the original BP algorithm to only one operation of looking up the table. The normalization factors can be obtained by simulation, or theoretically. Simulation results demonstrate that BPA algorithm exhibits fairly satisfactory bit error performance on the Additive White Gaussian Noise (AWGN) channel.     

Two Bit-Flipping Decoding Algorithms for Low-Density Parity-Check Codes

In this letter, a low complexity decoding algorithm for binary linear block codes is applied to low-density paritycheck (LDPC) codes and improvements are described, namely an extension to soft-decision decoding and a loop detection mechanism. For soft decoding, only one real-valued addition per code symbol is needed, while the remaining operations are only binary as in the hard decision case. The decoding performance is considerably increased by the loop detection. Simulation results are used to compare the performance with other known decoding strategies for LDPC codes, with the result that the presented algorithms offer excellent performances at smaller complexity.     

Low Complexity Decoder Architecture for Low-Density Parity-Check Codes

In this paper, we propose a low complexity decoder architecture for low-density parity-check (LDPC) codes using a variable quantization scheme as well as an efficient highly-parallel decoding scheme. In the sum-product algorithm for decoding LDPC codes, the finite precision implementations have an important tradeoff between decoding performance and hardware complexity caused by two dominant area-consuming factors: one is the memory for updated messages storage and the other is the look-up table (LUT) for implementation of the nonlinear function Ψ(x). The proposed variable quantization schemes offer a large reduction in the hardware complexities for LUT and memory. Also, an efficient highly-parallel decoder architecture for quasi-cyclic (QC) LDPC codes can be implemented with the reduced hardware complexity by using the partially block overlapped decoding scheme and the minimized power consumption by reducing the total number of memory accesses for updated messages. For (3, 6) QC LDPC codes, our proposed schemes in implementing the highly-parallel decoder architecture offer a great reduction of implementation area by 33% for memory area and approximately by 28% for the check node unit and variable node unit computation units without significant performance degradation. Also, the memory accesses are reduced by 20%.     

Weight Distribution of Low-Density Parity-Check Codes

We derive the average weight distribution function and its asymptotic growth rate for low-density parity-check (LDPC) code ensembles. We show that the growth rate of the minimum distance of LDPC codes depends only on the degree distribution pair. It turns out that capacity-achieving sequences of standard (unstructured) LDPC codes under iterative decoding over the binary erasure channel (BEC) known to date have sublinearly growing minimum distance in the block length     

Efficient Puncturing Method for Rate-Compatible Low-Density Parity-Check Codes

In this paper, we propose an efficient puncturing method for LDPC codes. The proposed algorithm provides the order of variable nodes for puncturing based on the proposed cost function. The proposed cost function tries to maximize the minimum reliability among those provided from all check nodes. Also, it tries to allocate survived check nodes evenly to all punctured variable nodes. Furthermore, the proposed algorithm prevents the formation of a stopping set from the punctured variable nodes even when the amount of puncturing is quite large. Simulation results show that the proposed punctured LDPC codes perform better than existing punctured LDPC codes.     

Multiple-Rate Low-Density Parity-Check Codes with Constant Blocklength

This paper describes and analyzes low-density parity-check code families that support variety of different rates while maintaining the same fundamental decoder architecture. Such families facilitate the decoding hardware design and implementation for applications that require communication at different rates, for example to adapt to changing channel conditions. Combining rows of the lowest-rate parity-check matrix produces the parity-check matrices for higher rates. An important advantage of this approach is that all effective code rates have the same blocklength. This approach is compatible with well known techniques that allow low-complexity encoding and parallel decoding of these LDPC codes. This technique also allows the design of programmable analog LDPC decoders. The proposed design method maintains good graphical properties and hence low error floors for all rates.     

Quasi-Cyclic Low-Density Parity-Check Codes for Space-Time Bit-Interleaved Coded Modulation

In this letter, it is shown that the diversity order of space-time bit-interleaved coded modulation (ST-BICM) system is determined by the number of submatrices having linearly independent column vectors in a parity-check matrix of quasicyclic low-density parity-check (QC-LDPC) code. It is also proved that this diversity order can be derived from the base matrix of QC-LDPC code, which can make it easy to design QC-LDPC codes suitable for ST-BICM systems. Finally, the simulation results are provided to confirm the analytical results.     

Universal Context Based Decoding with Low-Density Parity-Check Codes

Universal estimation strategies are proposed to improve channel decoding of sequences that contain context based redundancy. The new methods combine techniques from universal compression, such as the Burrows-Wheeler Transform (BWT) and segmentation of piecewise stationary memoryless sources (PSMS's) with recently proposed methods of discrete denoising. Simulation results with systematic low density parity check (LDPC) codes show significant improvements of the proposed methods on standard decoding, even when the actual sequence context model is unknown in advance. The combined methods inherit advantages of each of the separate methods.     

Nonlinear Programming Approaches to Decoding Low-Density Parity-Check Codes

We consider the decoding problem for low-density parity-check codes, and apply nonlinear programming methods. This extends previous work using linear programming (LP) to decode linear block codes. First, a multistage LP decoder based on the branch-and-bound method is proposed. This decoder makes use of the maximum-likelihood-certificate property of the LP decoder to refine the results when an error is reported. Second, we transform the original LP decoding formulation into a box-constrained quadratic programming form. Efficient linear-time parallel and serial decoding algorithms are proposed and their convergence properties are investigated. Extensive simulation studies are performed to assess the performance of the proposed decoders. It is seen that the proposed multistage LP decoder outperforms the conventional sum-product (SP) decoder considerably for low-density parity-check (LDPC) codes with short to medium block length. The proposed box-constrained quadratic programming decoder has less complexity than the SP decoder and yields much better performance for LDPC codes with regular structure.     

Low-Density Parity-Check Codes with 2-State Trellis Decoding

A class of low-density parity-check (LDPC) codes with a simple 2-state trellis structure is presented. For LDPC decoding, the conventional belief propagation (BP) algorithm consists of numerous sub-decoders of single-parity check codes and exchanges information between sub-decoders in an iterative manner. If the single-parity check codes can be constructed and grouped in a proper way, the decoder can be decomposed into few identical 2-state trellis decoders. Therefore, instead of numerous sub-decoders of single-parity check codes, an iterative decoding algorithm based on few sub-decoders over 2-state trellis is proposed. The proposed decoding algorithm improves the efficiency of message passing between sub-decoders and hence provides a fast convergent rate as compared to the standard BP algorithm. Simulation results show that the proposed scheme provides a better performance and a fast convergent rate as compared to those of standard BP algorithm. The result also shows that the proposed algorithm has a similar performance as that of asynchronous replica shuffled BP algorithm and has a slightly inferior performance than that of synchronous replica shuffled BP algorithm. However, complexity analysis shows that our proposed algorithm has complexity that is lower than that of the replica shuffled BP algorithm.     

LDPC码在QPSK调制下的应用分析

对低密度奇偶校验码(LDPC)在QPSK调制下的对数似然比(LLR)算法进行了深入研究,分析了LDPC码在QPSK调制下初始消息的计算方法,推导了初始消息的计算公式。同时对该算法进行了程序仿真,仿真结果表明LDPC码在QPSK调制中具有良好的性能。当信噪比为3.5 dB时,误码率可达到10-6数量级。     

Generalized Low-Density Parity-Check Codes Based on Hadamard Constraints

In this paper, we consider the design and analysis of generalized low-density parity-check (GLDPC) codes in AWGN channels. The GLDPC codes are specified by a bipartite Tanner graph, as with standard LDPC codes, but with the single parity-check constraints replaced by general coding constraints. In particular, we consider imposing Hadamard code constraints at the check nodes for a low-rate approach, termed LDPC-Hadamard codes. We introduce a low-complexity message-passing based iterative soft-input soft-output (SISO) decoding algorithm, which employs the a posteriori probability (APP) fast Hadamard transform (FHT) for decoding the Hadamard check codes at each decoding iteration. The achievable capacity with the GLDPC codes is then discussed. A modified LDPC-Hadamard code graph is also proposed. We then optimize the LDPC-Hadamard code ensemble using a low-complexity optimization method based on approximating the density evolution by a one-dimensional dynamic system represented by an extrinsic mutual information transfer (EXIT) chart. Simulation results show that the optimized LDPC-Hadamard codes offer better performance in the low-rate region than low-rate turbo-Hadamard codes, but also enjoy a fast convergence rate. A rate-0.003 LDPC-Hadamard code with large block length can achieve a bit-error-rate (BER) performance of 10^-5 at -1.44 dB, which is only 0.15 dB away from the ultimate Shannon limit (-1.592 dB) and 0.24 dB better than the best performing low-rate turbo-Hadamard codes     

外部信息转移图设计LDPC码

本文利用外部信息转移图技巧设计LDPC编码的数字调幅广播系统,取得令人满意的结果.例如在典型长波信道中所设计的具有线性编码复杂度的非正则LDPC码收敛门限距信道容量不超过0.54dB,码长为104时仿真结果距离信道容量不超过1dB.实验还表明在各种广播信道中优化的LDPC码皆优于本文中的Turbo码方案.     

构造短码长不规则LDPC码

在给定长度和度数分布对情况下,不规则短码长LDPC码的性能差别很大。本文给出了一种低复杂度的基于树的贪婪搜索算法(GTS),此算法通过调整校验矩阵中环的分布情况,尽量减少短长度环,获得最大的平均最小环,从而构造性能很好的短码长不规则LDPC码。     

LDPC码在16PSK调制下的应用分析

研究十六相移相键控(16PSK)对低密度奇偶校验码(LDPC)调制下的对数似然比(LLR)算法,分析在16PSK调制下LDPC码的初始信息的计算方法,并推导出初始信息公式.仿真表明:LDPC码在16PSK调制下展现出优良的译码性能.当信噪比为3.8 dB时,误码率可达到10-6数量级.