超高频双差分对管DQ401

1.DQ401主要参数指标I_(CEO)≤0.1μA(V_(CE)=10V);BV_(CEO)≥20V(I_(CE)=1mA);BV_(CBO)≥25V(I_(CB)=10μA);BV_(EBO)≥5V(I_(EB)=10μA);β≥40(V_(CE)=6V,I_C=10mA,f_O=200MHz);(β_1-β_2)/β_2≤5%,V_(BE1)-V_(BE2)≤2mV(V_(CE)=6V,I_C=10mA);f_T≥1000MHz(V_(CE)=6V,I_C=10mA、f_O=200MHz);I_(CM)≥20mA(单管最大工作电流);P_(CM)≥100mW(单管功耗).     

硅平面大功率晶体管D402、D10管芯失效机理分析

一、概述我们采用电分析和显微分析相结合的方法,在大量解剖分析失效的硅平面大功率晶体管D402、D10管芯的基础上,对表面引起失效及体内引起失效的机理进行了较为详细的分析和讨论.D402和D10晶体管是npn型硅平面低频大功率管,其主要技术性能:P_(CM)为2～5W;I_(CM)为1A;BV_(ceo)≥100V(I_C=0.5mA):I_(ceo)≤0.1mA(V_(ce)=20V);V_(ces)≤0.6V(I_c=0.5mA,I_b=0.05mA).其主要用途是作十二英寸、十四英寸黑白电视机伴音功放,以及部分电源推动和激励,其外壳采用D-1C管座封装,     

SEBISIT——一种新型高压抗辐射功率晶体管

SEBISIT器件充分利用了SIT器件的栅的电场屏蔽作用,一方面有效地抑制了高反压下耗尽层向基区内的扩展,实现了高压薄基区;另一方面保证了器件有接近于BV_(cbo)的BV_(ceo),实现了较薄外延层下有较高的BV_(ceo),本文对此器件作了较全面的分析。实验验证了SIT屏蔽效应的存在,并试制出BV_(ceo)为225V,f_T大于400MHz的功率加固器件,其φ0.5为常规高压器件的60多倍,有效地改善了高压晶体管的抗辐射加固性能。     

高性能高压自对准双扩散横向pnp晶体管

适用于高压线集成电路的一种新的横向晶体管——自对准双扩散横向(SADDL)晶体管已经开发出来。这种管子具有一个自对准形成的窄的n型基区,以提供高的h_(FE)和高的f_T;还有一个可减小电场、提供高的击穿电压BV_(ceo)的P~-型集电极。业已证明,SADDL晶体管的f_T在不降低BV_(ceo)的情况下可以得到改进,f_T值比已经报道过的其它横向晶体管的高十倍以上。制造出的350V档SADDL晶体管,具有高的h_(FE)(约100)、高的f_T(约15MHz)和高的阿莱电压(>1000V)。     

集电极扩散隔离工艺

本文介绍集电极扩散隔离工艺的特点,叙述该工艺的实验,并给出用此工艺技术制作的晶体管(β≥100,f_T>1000MHz,BV_(ceo)≥6V)和E/T转换器的结果。     

基于SiC的NPN双极型晶体管设计

利用高禁带宽度的SiC材料,设计了一种基于SiC的NPN双极型晶体管,该晶体管采用多层缓变掺杂基区结构实现。在完成晶体管结构设计基础上,仿真分析了晶体管的直流电流增益、击穿特性以及频率特性。在工艺方面,设计完成了晶体管制备工艺流程与版图。仿真结果表明,SiC双极型晶体管具有击穿电压高(BV_(CEO)=900 V)、特征频率高(f_T=5 GHz),晶体管增益适中(β=33)等特点。     

一种与双极型模拟电路兼容的低/高压MOS器件

本文介绍一种与双极IC电路技术完全兼容的低压(CMOS)/高压(VDMOS)器件设计与制备工艺。VDMOS器件阈电压:1～2伏(根据注入剂量调节),漏击穿电压大于150伏。V_(GS)=5V时其跨导大于10m(?),导通电阻小于200Ω,最大输出电流约800mA。同时得到的NPN器件其β≥250,BV_(ceo)≥65V,BV_(CBO)≥90V。CMOS器件性能也合乎要求。利用这种工艺可制作任何低压和高压双极/MOS器件,这对于功率集成、高低压转换与驱动、等离子体显示等方面应用会有很多实用价值。     

GaAlAs/GaAs宽禁带发射极异质结微波双极型晶体管的设计制造和性能

本文比较详细地叙述了GaAlAs/GaAs宽禁带发射极异质结微波双极型晶体管的设计原理、制作工艺和实验结果。在叙述原理时着重于与Si微波功率管的对比,并将实验结果和理论值进行了对比和分析,指出了进一步改进高频性能的途径。已经得到的初步实验结果为:击穿电压BV_(ceo)=80V,l_(cmax)=200mA(发射结面积为A_B=2×10~(-4)cm~2),电流增益h(fe)=20～300,最大振荡频率f_(max)=1.2GHz,特征频率f_T=2.0GHz(V_(ce)=20V,I_c=20mA),实测到的温度-电流增益h_(fe)曲线说明晶体管的工作温度可高达350℃。     

晶体管特性图示仪数字显示装置

本文就晶体管的β、I_(ceo)、BV_(ceo)三个参数的数字显示的实施进行简要的介绍.一、综合方框图图1示出了β、I_(ceo)、BV_(ceo)三个参数数字显示的综合方框图.由图可见,β、I_(ceo)的取样信号是通过各自的键控,     

电子辐照消除CMOS电路自锁效应的探讨

<正> CMOS电路中存在着pnpn寄生可控硅结构,见图1(a),它比实际可控硅的结构多两个分流电阻Rn和R_p,见图1(b)、(c).若寄生npn和pnp晶体管的电流增益分别为β_(npn)和β_(pnp),这时导通条件便由理想可控硅的β_(npn)·β_(pnp)=1变为β_(npn)·β_(pnp)=     

A high-voltage IC for a transformerless trunk and subscriber line interface

A new high-voltage, junction-isolated, complementary bipolar technology has been used to fabricate an IC for a transformerless trunk and subscriber line interface. The new technology provides both vertical p-n-p and n-p-n transistors with BV/SUB CE0/ greater than 60 V, betas of 100, and f/SUB T/'s of 200 MHz. It permits the straightforward op amp realization of a new op amp circuit configuration in transformerless line circuits. The new configuration uses the high-voltage IC plus some low voltage control circuitry to provide limited current battery-feed, loop-closure detection, reverse-battery signaling, two-wire to four-wire conversion, lightning protection, power-down capability, and longitudinal performance which is independent of the battery-feed current magnitude.     

A BiCMOS technology with 660-MHz vertical p-n-p transistor foranalog/digital ASICs

A fully complementary BiCMOS technology based on a 2-μm process designed for 12-V analog/digital applications is described. In this technology, a triple diffused vertical p-n-p transistor and n-p-n bipolar and CMOS devices are integrated in a single chip. A transition frequency of 660 MHz and a collector-to-emitter breakdown voltage of over 15 V have been obtained for the collector-isolated p-n-p transistor by adding only one extra mask to a conventional 2-μm BiCMOS process. The total number of masks is 20 with double-layer metallization. A unity gain frequency of 52 MHz and a DC gain of 85 dB have been obtained for a single-supply operational amplifier with a vertical p-n-p first stage. The propagation delay time for a CMOS two-NAND gate was 1.27 ns driving three loads and 3 mm of metal     

A 150-V multiple up-drain VDMOS, CMOS, and bipolar process in`direct-bonded' silicon on insulator on silicon

Silicon on insulator on silicon (SOIS) has been produced with silicon direct bonding (SDB). Within a silicon film of 15-μm thickness, islands with ubiquitous oxide isolation have been formed for the simultaneous integration of 150-V power VDMOS transistors, CMOS circuits in a channelless sea-of-gates array with 2-μm gates, and bipolar transistors. The up-drain VDMOS transistors with 2-Ω-mm ² specific on-resistance allow multiple isolated outputs, so high-voltage push-pull drivers can be fabricated in a single chip. The bipolar transistors are comparable to those of a 60-V standard process with vertical n-p-n and lateral p-n-p current gains of 80     

High-speed organic transistors with three-dimensional organic channels and organic rectifiers based on them operating above 20 MHz

Three-dimensional organic transistors (3D-OFETs) comprising vertical short channels are developed to raise the operational speed of organic transistors. The devices with a short-channel length of 0.8 μm and reduced parasitic capacitance operate at up to 20 MHz with an applied drain voltage of −15 V. Organic rectifiers based on the diode-connected 3D-OFETs are also demonstrated to operate at above 20 MHz, even with an applied effective voltage of about 4 V, which is higher than the speed of radio frequency identification tags of 13.56 MHz required in near field communication. These techniques boost the performance of organic transistors and can help to realize the breakthrough for practical applications of organic logic circuits used as key components in various flexible or plastic devices.     

A compact low noise operational amplifier for a 1.2 μm digitalCMOS technology

A compact low noise operational amplifier using lateral p-n-p bipolar transistors in the input stage has been fabricated in a standard 1.2 μm digital n-well CMOS process. Like their n-p-n counterparts in p-well processes, these lateral p-n-p transistors exhibit low 1/f noise and good lateral β. The fabricated op amp has an area of only 0.211 mm² with E_n=3.2 nV/√(Hz), I_n=0.73 pA/√(Hz), E_n and I_n 1/f noise corner frequencies less than 100 Hz, a -3 dB bandwidth greater than 10 MHz with a closed loop gain of 20.8 dB, a minimum PSRR (DC) of 68 dB, a CMRR (DC) of 100 dB, a minimum output slew rate of 39 V/μs, and a quiescent current of 2.1 mA at supply voltages of ±2.5 V. The operational amplifier drives a 1 kΩ resistive load to 1 V peak-to-peak at 10 MHz and has been used as a versatile building block for mixed-signal IC designs     

A dielectrically isolated complementary bipolar technique for analog/Digital compatible LSI's

A dielectrically isolated complementary bipolar technique has been developed for use in analog LSI's or analog/digital compatible LSI's. This process makes it possible to form vertical double-diffused transistors in complementary islands and to obtain a high breakdown voltage of more than 350 V in spite of using shallow junctions with a depth of less than 2 µm. The gain bandwidth product fTis 450 and 200 MHz for n-p-n and p-n-p transitors, respectively. With this process, a subscriber line interface LSI that includes three functions (battery feed, supervision, and hybrid) has been successfully achieved within a 12.6 mm²die area.     

10K Gate I/sup 2/L and 1K Component Analog Compatible Bipolar VLSI Technology -- HIT-2

An advanced analog/digital bipolar VLSI technology that combines on the same chip 2-ns 10K I/sup 2/L gates with 1K analog devices is proposed. The new technology, called high-density integration technology-2 (HIT-2), is based on a new structure concept that consists of three major techniques shallow grooved-isolation, I/sup 2/L active layer etching, and I/sup 2/L current gain increase. I/sup 2/L circuits with 80-MHz maximum toggle frequency have developed compatibly with n-p-n transistors having a BV/sub CEO/of more than 10 V and an f/sub T/ of 5 GHz, and lateral p-n-p transistors having an f/sub T/ of 150 MHz.     

Performance, temperature behavior, and first-order modeling of ISL

The minimum propagation delay time of integrated Schottky logic (ISL) made in a standard LS process is determined by saturation of the vertical p-n-p clamp transistor. A performance improvement is obtained by increasing the dope of the substrate to prevent this saturation effect. When using 5 /spl mu/m minimum dimensions the minimum propagation delay is then well below 3 ns over the full temperature range from -55 up to 150/spl deg/C chip temperature. It is shown that a vertical p-n-p clamp transistor is essential to obtain a high speed when relaxed design rules are used. Furthermore, it is shown that ISL can be modeled in a relatively simple manner with one n-p-n transistor and one or two p-n-p transistors, depending on the resistivity of the substrate.     

An Advanced Bipolar-MOS-I/sub 2/L Technology with a Thin Epitaxial Layer for Analog-Digital VLSI

A novel Bi-MOS technology, Advanced Bipolar CMOS (ABC), is proposed. Bipolar transistors (n-p-n, p-n-p, I/sup 2/L)and MOS transistors (both n- and p-channel) have been successfully fabricated on the same chip with no decrease in performance by using a 3-/spl mu/m design rule. Thin epitaxial layer (<= 2 /spl mu/m) is used in order to obtain small-size high-performance (3-GHz) bipolar devices. Device size is reduced by using a shallow junction and self-aligning technique. n-channel MOS transistors are formed in p-well regions designed to reach p-type substrate, and p-channel MOS transistors are formed in epitaxial layer with an n/sup +/ buried layer. This technology has the potential for monolithic multifunctional analog-digital VLSI.     

A BiCMOS process utilizing selective epitaxy for analog/digitalapplications

A 2-μm BiCMOS process that has been designed for 10-V analog/digital applications is described. This process utilizes selective epitaxial growth to integrate a vertical n-p-n bipolar with an f_T of 3.0 GHz, and a nonoptimized vertical p-n-p structure into a 2-μm CMOS process with poly-to-n⁺ capacitors. The insertion of the bipolar structures is accomplished with only two added masking steps, and with no changes to the critical process parameters that determine the performance of the MOS transistors. The circuit worthiness of the process is demonstrated by fabricating CMOS, vertical n-p-n RTL, and vertical p-n-p RTL ring oscillators, and demonstrating high yields for these circuits