A simple analytical threshold voltage model of nanoscale single-layer fully depleted strained-silicon-on-insulator MOSFETs

For the first time, a simple and accurate analytical model for the threshold voltage of nanoscale single-layer fully depleted strained-silicon-on-insulator MOSFETs is developed by solving the two-dimensional (2-D) Poisson equation. In the proposed model, the authors have considered several important parameters: 1) the effect of strain (in terms of equivalent Ge mole fraction); 2) short-channel effects; 3) strained-silicon thin-film doping; 4) strained-silicon thin-film thickness; and 5) gate work function and other device parameters. The accuracy of the proposed analytical model is verified by comparing the model results with the 2-D device simulations. It has been demonstrated that the proposed model correctly predicts a decrease in threshold voltage with increasing strain in the silicon thin film, i.e., with increasing equivalent Ge concentration. The proposed compact model can be easily implemented in a circuit simulator.     

隐埋层中二维效应对全耗尽SOI非对称HALO结构阈值电压的影响

在非对称HALO结构的全耗尽SOI二维阈值电压解析模型的基础上,对阈值电压受隐埋层中二维效应的影响进行了讨论.通过与一维模型的比较,说明在深亚微米SOI MOSFET器件中隐埋层的二维效应会导致器件提前出现短沟道效应.新模型结果与二维数值模拟软件MEDICI吻合较好.     

隐埋层中二维效应对全耗尽SOI非对称HALO结构阈值电压的影响

在非对称HALO结构的全耗尽SOI二维阈值电压解析模型的基础上,对阈值电压受隐埋层中二维效应的影响进行了讨论.通过与一维模型的比较,说明在深亚微米SOI MOSFET器件中隐埋层的二维效应会导致器件提前出现短沟道效应.新模型结果与二维数值模拟软件MEDICI吻合较好.     

Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs

A two-dimensional (2-D) analytical model for the surface potential variation along the channel in fully depleted dual-material gate silicon-on-insulator MOSFETs is developed to investigate the short-channel effects (SCEs). Our model includes the effects of the source/drain and body doping concentrations, the lengths of the gate metals and their work functions, applied drain and substrate biases, the thickness of the gate and buried oxide and also the silicon thin film. We demonstrate that the surface potential in the channel region exhibits a step function that ensures the screening of the drain potential variation by the gate near the drain resulting in suppressed SCEs like the hot-carrier effect and drain-induced barrier-lowering (DIBL). The model is extended to find an expression for the threshold voltage in the submicrometer regime, which predicts a desirable "rollup" in the threshold voltage with decreasing channel lengths. The accuracy of the results obtained using our analytical model is verified using 2-D numerical simulations.     

A new method for extracting the counter-implanted channel profileof enhancement-mode p-MOSFETs

A new methodology is proposed to extract the nonuniform channel doping profile of enhancement mode p-MOSFETs with counter implantation, based on the relationship between device threshold voltage and substrate bias. A selfconsistent mathematical analysis is developed to calculate the threshold voltage and the surface potential of counter-implanted long-channel p-MOSFET at the onset of heavy inversion. Comparisons between analytic calculation and two-dimensional (2-D) numerical analysis have been made and the accuracy of the developed analytic model has been verified. Based on the developed analytic model, an automated extraction technique has been successfully implemented to extract the channel doping profile. With the aid of a 2-D numerical simulator, the subthreshold current can be obtained by the extracted channel doping profile. Good agreements have been found with measured subthreshold characteristics for both long- and short-channel devices. This new extraction methodology can be used for precise process monitoring and device optimization purposes     

Subthreshold current model of FinFETs based on analytical solution of 3-D Poisson's equation

The potential variation in the channel obtained from analytical solution of three-dimensional (3-D) Poisson's equation is used to calculate the subthreshold current and threshold voltage of fin field-effect transistors with doped and undoped channels. The accuracy of the model has been verified by the data from 3-D numerical device simulator. The variation of subthreshold slope and threshold voltage with device geometry and doping concentration in the channel has been studied.     

A threshold voltage model for short-channel MOSFETs taking into account the varying depth of channel depletion layers around the source and drain

In this paper, an analytical model for threshold voltage of short-channel MOSFETs is presented. For such devices, the depletion regions due to source/drain junctions occupy a large portion of the channel, and hence are very important for accurate modeling. The proposed threshold voltage model is based on a realistic physically-based model for the depletion layer depth along the channel that takes into account its variation due to the source and drain junctions. With this, the unrealistic assumption of a constant depletion layer depth has been removed, resulting in an accurate prediction of the threshold voltage. The proposed model can predict the drain induced barrier lowering (DIBL) effect and hence, the threshold voltage roll-off characteristics quite accurately. The model predictions are verified against the 2-D numerical device simulator, DESSIS of ISE TCAD.     

Analytical modeling of the two-dimensional potential distribution and threshold voltage of the SOI four-gate transistor

The two-dimensional (2-D) channel potential and threshold voltage of the silicon-on-insulator (SOI) four-gate transistor (G/sup 4/-FET) are modeled. The 2-D analytical body potential is derived by assuming a parabolic potential variation between the lateral junction-gates and by solving Poisson's equation. The model is used to obtain the surface threshold voltage of the G/sup 4/-FET as a function of the lateral gate bias and for all possible charge conditions at the back interface. The body-potential model is extendable to fully depleted SOI MOSFETs and can serve to depict the charge-sharing and drain-induced barrier-lowering effects in short-channel devices.     

非对称HALO结构的全耗尽SOI二维阈值电压解析模型

在考虑了隐埋层与硅层的二维效应的基础上提出非对称HALO结构的全耗尽SOI二维阈值电压解析模型,该模型计算了在不同硅膜厚度,掺杂浓度,HALO区占沟道比例的条件下的阈值电压.模型结果与二维数值模拟软件MEDICI的模拟结果较好的吻合,该模型对HALO结构的物理特性和工艺设计有很好的指导意义.     

Short-channel single-gate SOI MOSFET model

The authors derive an analytical model for threshold voltage for fully depleted single-gate silicon-on-insulator (SOI) MOSFETs taking into consideration the two-dimensional effects in both SOI and buried-oxide layers. Their model is valid for both long- and short-channel SOI MOSFETs and demonstrates the dependence of short-channel effects on the device parameters of channel-doping concentration, gate oxide, SOI, and buried-oxide thickness. It reproduces the numerical data for sub-0.1-/spl mu/m gate-length devices better than previous models.     

Three-dimensional analytic modelling of front and back gate threshold voltages for small geometry fully depleted SOI MOSFET’s

New 3-D analytical models of front and back gate threshold voltages for fully depleted SOI MOSFET’s have been described here. The present models take into account the contributions of all the three paths of conduction such as front gate oxide-silicon, back gate oxide-silicon and side wall oxide-silicon interfaces in mesa isolated structure of such MOSFET’s. In order to do this, 3-D Poisson’s equation has been solved analytically with suitable boundary conditions to obtain an explicit expression of electrostatic potential within fully depleted SOI film with uniform doping concentration. With the help of this expression, the compact and closed form formulae of front and back gate threshold voltages under various conditions have been established. In addition to this, the closed form expressions of biasing counterparts of front and back threshold voltages i.e. respective back and front gate biases have also been reported in order to decide required operational modes of both interfaces of the device. The calculated results of the threshold voltages have been validated with available numerical data.     

Threshold voltage model for small geometry AlGaN/GaN HEMTs based on analytical solution of 3-D Poisson's equation

A simple and accurate analytical model for the threshold voltage of AlGaN/GaN high electron mobility transistor (HEMT) is developed by solving three-dimensional (3-D) Poisson equation to investigate the short channel effects (SCEs) and the narrow width effects present simultaneously in a small geometry device. It has been demonstrated that the proposed model correctly predicts the potential and electric field distribution along the channel. In the proposed model, the effect of important parameters such as the thickness of the barrier layer and its doping on the threshold voltage has also been included. The model is, further, extended to find an expression for the threshold voltage in the sub-micrometer regime. The accuracy of the proposed analytical model is verified by comparing the model results with 3-D device simulations for different gate lengths and widths.     

A new simplified threshold-voltage model for n-MOSFETs with nonuniformly doped substrate and its application to MOSFET's miniaturization

The formulation, verification, and application of a new simplified 2-D threshold voltage model for n-MOSFETs with nonuniformly doped substrate profile are provided, in which the averaged normal field at the Si/SiO/sub 2/ interface in the active channel is quoted from a simplified solution of two-dimensional Poisson equation using the Green function technique. Starting with the expression of this average normal field, a simple threshold-voltage model for short-channel n-MOSFETs with nonuniformly doped substrate profile is explicitly expressed in terms of device structures and terminal voltages by considering parabolic source-drain boundary potentials. Moreover, the effects of the junction depth on the threshold voltage are examined in detail. It is shown that the DIBL effect cannot be completely eliminated by simply increasing the substrate doping concentration. Comparisons among developed model, 2-D numerical analysis, and experimental data have been made and the accuracy of the developed analytical model has been verified. In addition, a direct extension of our model to the case of uniformly doped substrates leads to a new constraint equation for device miniaturization.<>     

Multiple Sb ion implantation for deep-submicron pMOS channel doping

We propose a channel doping technology for pMOSFET's in which Sb is multiply ion implanted to produce a uniform doping profile in the region deeper than the minimum projected range of the multiple ion implantation. We derive a threshold voltage model and show how to realize this uniform doping profile, which is verified with experimental data. We study the short-channel effect of this device using a two-dimensional (2-D) device simulator, and show that this transistor can readily operate with a gate length of down to 0.1 μm     

A new approach to threshold voltage modelling of short-channel MOSFETS

A simple analytical model has been developed to predict the threshold voltage on drain bias dependence of an arbitrarily doped short-channel MOSFET. Based on an analytical solution of the two-dimensional Poisson equation, the potential distribution in the channel depletion region has been derived. The maximum surface field and the minimum surface potential are used to determine the threshold voltage. The influence of drain voltage on threshold voltage has been included by an equivalent shrinkage of the virtual channel length hereafter called “voltage-length transformation”. This simple but general procedure enables us to account for the drain effect and to extend other threshold voltage models derived under assumption of low drain-source voltage. Predictions for threshold voltage have been compared with results of two-dimensional numerical analysis and experimental data. The comparison has been made for a wide variety of doping profiles, channel length, substrate and drain bias, gate oxide thickness and junction depth. Excellent agreement has been obtained down to submicron channel length.     

Threshold voltage model for deep-submicron fully depleted SOI MOSFETs with back gate substrate induced surface potential effects

A simple analytical threshold voltage model for short-channel fully depleted SOI MOSFETs has been derived. The model is based on the analytical solution of the two-dimensional potential distribution in the silicon film (front silicon), which is taken as the sum of the long-channel solution to the Poisson's equation and the short-channel solution to the Laplace equation, and the solution of the Poisson's equation in the silicon substrate (back silicon). The proposed model accounts for the effects of the back gate substrate induced surface potential at the buried oxide-substrate interface which contributed an additional 15–30% reduction in the threshold voltage for the devices used in this work. Conditions on the back gate supply voltage range are determined upon which the surface potential at the buried oxide-substrate interface is accumulated, depleted, or inverted. The short-channel associated drain induced barrier lowering effects are also included in the model. The model predications are in close agreement with PISCES simulation results. The equivalence between the present model and previously reported models is proven. The proposed model is suitable for use in circuit simulation tools such as Spice.     

一种非均匀掺杂的全耗尽SOI-MOSFET阈值电压模型

对垂直于沟道的二维电势分布函数提出了一种新的近似,给出了基于这种近似的杂质浓度呈高斯分布的非均匀掺杂全耗尽SOI-MOSFET的阈值电压解析模型.模型结果与MEDICI数值模拟结果符合得很好,表明了模型的准确性,这为实践中分析与控制非均匀掺杂的全耗尽SOI-MOSFET的阈值电压提供了一种新的途径.     

一种非均匀掺杂的全耗尽SOI-MOSFET阈值电压模型(英文)

对垂直于沟道的二维电势分布函数提出了一种新的近似,给出了基于这种近似的杂质浓度呈高斯分布的非均匀掺杂全耗尽SOI-MOSFET的阈值电压解析模型.模型结果与MEDICI数值模拟结果符合得很好,表明了模型的准确性,这为实践中分析与控制非均匀掺杂的全耗尽SOI-MOSFET的阈值电压提供了一种新的途径.     

一种非均匀掺杂的全耗尽SOI-MOSFET阈值电压模型

对垂直于沟道的二维电势分布函数提出了一种新的近似,给出了基于这种近似的杂质浓度呈高斯分布的非均匀掺杂全耗尽SOI-MOSFET的阈值电压解析模型.模型结果与MEDICI数值模拟结果符合得很好,表明了模型的准确性,这为实践中分析与控制非均匀掺杂的全耗尽SOI-MOSFET的阈值电压提供了一种新的途径.