双层复合有机栅绝缘膜漏电机理的研究

本文研究了利用旋涂法在硅衬底上制备的聚甲基丙烯酸甲酯(PMMA)和三氟乙烯-偏氟乙烯的共聚物(P(VDFTrFE))双层复合绝缘膜的漏电机理,采用这种膜的MIS器件的单位面积电容为32nF/cm2。电流-电压测试结果显示在不同的电压范围内其漏电曲线出现转折点,反映了这种膜在不同的电场下有不同的漏电机制。对实验结果拟合分析表明,在0~1V电压范围内,其漏电主要是Poole-Frenkel机制控制;在1~25V电压范围内,主要是以肖特基发射电流为主;而在35~40V的电压范围内,绝缘膜漏电流是空间电荷限制电流。     

Temperature effect on gate leakage currents in gate dielectric films of GaAs MOSFET

The gate dielectrics of Ga₂O₃(As₂O₃) of the GaAs MOSFET were prepared by a low-cost and low-temperature liquid-phase chemically enhanced oxidation method. The temperature and oxide thickness dependence of gate dielectric films on GaAs MOSFET have been investigated. The leakage current and dielectric breakdown field were both studied. Both gate leakage current density and breakdown electrical field were found to depend on the oxide thickness and operating temperature. The increasing trend in gate leakage current and the decreasing trend in breakdown electrical field were observed upon reducing oxide thickness from 30 to 12 nm and increasing operating temperature from −50°C to 200°C.     

A novel double gate MOSFET by symmetrical insulator packets with improved short channel effects

In this article, we study a novel double-gate SOI MOSFET structure incorporating insulator packets (IPs) at the junction between channel and source/drain (S/D) ends. The proposed MOSFET has great strength in inhibiting short channel effects and OFF-state current that are the main problems compared with conventional one due to the significant suppressed penetrations of both the lateral electric field and the carrier diffusion from the S/D into the channel. Improvement of the hot electron reliability, the ON to OFF drain current ratio, drain-induced barrier lowering, gate-induced drain leakage and threshold voltage over conventional double-gate SOI MOSFETs, i.e. without IPs, is displayed with the simulation results. This study is believed to improve the CMOS device reliability and is suitable for the low-power very-large-scale integration circuits.     

Gate Current Modeling and Optimal Design of Nanoscale Non-Overlapped Gate to Source/Drain MOSFET

In this paper, novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time. The gate leakage behaviour of novel MOSFET structure has been investigated with help of compact analytical model and Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region. It is found that optimal Source/Drain-to-Gate Non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and DIBL characteristic. It is concluded that this structure solves the problem of high leakage current without introducing the extra series resistance.     

Investigation of the novel attributes of a single-halo double gate SOI MOSFET: 2D simulation study

The novel features of an asymmetric double gate single halo (DG-SH) doped SOI MOSFET are explored theoretically and compared with a conventional asymmetric DG SOI MOSFET. The two-dimensional numerical simulation studies demonstrate that the application of single halo to the double gate structure results in threshold voltage roll-up, reduced DIBL, high drain output resistance, kink free output characteristics and increase in the breakdown voltage when compared with a conventional DG structure. For the first time, we show that the presence of single halo on the source side results in a step function in the surface potential, which screens the source side of the structure from the drain voltage variations. This work illustrates the benefits of high performance DG-SH SOI MOS devices over conventional DG MOSFET and provides an incentive for further experimental exploration.     

Gate current modeling and optimal design of nanoscale non-overlapped gate to source/drain MOSFET

A novel nanoscale MOSFET with a source/drain-to-gate non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time.The gate leakage behaviour of the novel MOSFET structure has been investigated with the help of a compact analytical model and Sentaurus simulation. A fringing gate electric field through the dielectric spacer induces an inversion layer in the non-overlap region to act as an extended S/D(source/drain) region.It is found that an optimal source/drain-to-gate non-overlapped and high-A:spacer structure has reduced the gate leakage current to a great extent as compared to those of an overlapped structure.Further,the proposed structure had improved off current,subthreshold slope and drain induced barrier lowering(DIBL) characteristics.It is concluded that this structure solves the problem of high leakage current without introducing extra series resistance.     

具有补偿埋层的槽型埋氧层SOI高压器件新结构

A new silicon-on-insulator(SOI) high-voltage MOSFET structure with a compensation layer on the trenched buried oxide layer(CL T-LDMOS) is proposed.The high density inverse interface charges at the top surface of the buried oxide layer(BOX) enhance the electric field in the BOX and a uniform surface electric field profile is obtained,which results in the enhancement of the breakdown voltage(BV).The compensation layer can provide additional P-type charges,and the optimal drift region concentration is increased in order to satisfy the reduced surface electric field(RESURF) condition.The numerical simulation results indicate that the vertical electric field in the BOX increases to 6 MV/cm and the B V of the proposed device increases by 300%in comparison to a conventional SOI LDMOS,while maintaining low on-resistance.     

Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. PMOS-only sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by 88 to 97% as compared to the standard dual threshold voltage domino logic circuits. Similarly, a 22 to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45 nm CMOS technology.     

Impact of SOI thickness on device performance and gate oxide reliability of Ni fully silicide metal-gate strained SOI MOSFET

This study investigates the effects of oxide traps induced by SOI of various thicknesses (T_SOI = 50, 70 and 90 nm) on the device performance and gate oxide TDDB reliability of Ni fully silicide metal-gate strained SOI MOSFETs capped with different stressed SiN contact-etch-stop-layer (CESL). The effects of different stress CESLs on the gate leakage currents of the SOI MOSFET devices are also investigated. For devices with high stress (either tensile or compressive) CESL, thinner T_SOI devices have a smaller net remaining stress in gate oxide film than thicker T_SOI devices, and thus possess a smaller bulk oxide trap (N_BOT) and reveal a superior gate oxide reliability. On the other hand, the thicker T_SOI devices show a superior driving capability, but it reveals an inferior gate oxide reliability as well as a larger gate leakage current. From low frequency noise (LFN) analysis, we found that thicker T_SOI device has a higher bulk oxide trap (N_BOT) density, which is induced by larger strain in the gate oxide film and is mainly responsible for the inferior gate oxide reliability. Presumably, the gate oxide film is bended up and down for the p- and nMOSFETs, respectively, by the net stress in thicker T_SOI devices in this CESL strain technology. In addition, the bending extent of gate oxide film of nMOSFETs is larger than that of pMOSFETs due to the larger net stress in gate oxide film resulting from additional compressive stress of shallow trench isolation (STI) pressed on SOI. Therefore, an appropriate SOI thickness design is the key factor to achieve superior device performance and reliability.     

Quantum-mechanical effects and gate leakage current of nanoscale n-type FinFETs: A 2d simulation study

This paper simulates a kind of new sub-50 nm n-type double gate MOS nanotransistors by solving coupled Poisson-Schrödinger equations in a self-consistent manner with a finite element method, and presents a systematic simulation-based study on quantum-mechanical effects, gate leakage current of FinFETs. The simulation results indicate that the deviation from the classical model becomes more important as the gate oxide, gate length and Fin channel width becomes thinner and the Fin channel doping increases. Gate tunneling current density reduces with the body thickness decreasing. Excessive scaling increases the gate current below Fin thickness of 5 nm. The gate current can be dramatically reduced beyond 10¹⁷ cm⁻³ with the Fin body doping increasing. In order to understand the influence of electron confinement, quantum mechanical simulation results are also compared with the results from the classical approach. Our simulation results indicate that quantum mechanical simulation is essential for the realistic optimization of the FinFET structure.     

Analytical surface potential modeling and simulation of junction-less double gate (JLDG) MOSFET for ultra low-power analog/RF circuits

In this paper, a simple structure for short channel junction-less double gate (JLDG) MOSFET is proposed. Further expression for surface potential of JLDG has been derived using 2D Poisson׳s equation. Based on the proposed analytical model for surface potential distribution along channel thickness and channel length is derived. The proposed junction-less MOSFET has no p-n junction as the doping of channel is same to that of Source/Drain region. The analytical model is compared with numerical solution using ATLAS device simulator. The result shows the variation of channel potential with channel length, channel thickness, doping concentration and applied gate bias. Further, in this paper the analog performance and RF figure of merits (FOMs) have been investigated. The purpose of this research is to provide a physical explanation for improved analog and RF performance exhibited by the device. In this paper major FOMs such as trans-conductance (g_m), output conductance (g_d), early voltage (V_EA), intrinsic gain (A_V), trans-conductance generation factor (TGF), cut-off frequency (f_T), trans-conductance frequency product (TFP), gain frequency product (GFP), gain trans-conductance frequency product (GTFP) are analyzed. The simulation result shows that the JLDG exhibit a higher trans-conductance, higher cut-off frequency and lower drain conductance.     

Modeling and estimation of edge direct tunneling current for nanoscale metal gate (Hf/AlNx) symmetric double gate MOSFET

This paper present, the modeling and estimation of edge direct tunneling current of metal gate (Hf/AlN_x) symmetric double gate MOSFET with an intrinsic silicon channel. To model this leakage current, we use the surface potential model obtained from 2D analytical potential model for double gate MOSFET. The surface potential model is used to evaluate the electric field across the insulator layer hence edge direct tunneling current. Further, we have modeled and estimated the edge direct tunneling leakage current for high-k dielectric. In this paper, from our analysis, it is found that dual metal gate (Hf/AlN_x) material offer the optimum leakage currents and improve the performance of the device. This feature of the device can be utilized in low power and high performance circuits and systems.     

Low leakage and high performance of nMOSFET using SiGe layer as a diffusion barrier

As a boron diffusion barrier, a 20 nm-thick Si_0.8Ge_0.2 layer was successfully utilized in n-channel MOSFETs for implementing a retrograded well structure. Compared with the conventional Si CMOS process, the developed n-channel MOSFET process provides an enhanced transconductance (7%) and lower sub-threshold swing which is nearly unchanged even at an increased drain-source voltage. Especially, because sub-threshold leakage current is one of the key issues in the MOS device scaling due to reduced threshold voltage, the usage of a Si_0.8Ge_0.2 layer in n-channel MOSFET was verified to be useful for low power and high performance even under aggressive scaling constraints.     

具有非平面埋氧层的新型SOI材料的制备

提出一种基于SDB技术的非平面埋氧层SOI材料制备方法.其关键技术包括:通过干法刻蚀、高压氧化和淀积二氧化硅获得高质量非平面埋氧层;通过化学气相淀积多晶硅来形成键合缓冲层,并运用回刻光刻胶和化学机械抛光来实现键合面的局部和全局平坦化;通过室温真空贴合、中温预键合和高温加固键合来进行有源片和衬底片的牢固键合.基于该技术研制了有源层厚度为21μm、埋氧层厚度为0.943μm、顶面槽和底面槽槽高均为0.9μm的具有双面绝缘槽结构的非平面埋氧层新型SOI材料.测试结果表明该材料具有结合强度高、界面质量好、电学性能优良等优点.     

A fuzzy-logic-based approach to accurate modeling of a double gate MOSFET for nanoelectronic circuit design

正The double gate(DG) silicon MOSFET with an extremely short-channel length has the appropriate features to constitute the devices for nanoscale circuit design.To develop a physical model for extremely scaled DG MOSFETs,the drain current in the channel must be accurately determined under the application of drain and gate voltages.However,modeling the transport mechanism forthe nanoscale structures requires the use of overkill methods and models in terms of their complexity and computation time(self-consistent,quantum computations,...). Therefore,new methods and techniques are required to overcome these constraints.In this paper,a new approach based on the fuzzy logic computation is proposed to investigate nanoscale DG MOSFETs.The proposed approach has been implemented in a device simulator to show the impact of the proposed approach on the nanoelectronic circuit design.The approach is general and thus is suitable for any type of nanoscale structure investigation problems in the nanotechnology industry.     

Subtle gate oxide defect elimination to improve the reliability of a 32M-bit SRAM product

Tiny defects may escape from in-line defect scan and pass WAT (Wafer Acceptance Test), CP (Chip Probing), FT (Final Test) and SLT (System Level Test). Chips with such kind of defects will cause reliability problem and impact revenue significantly. It is important to catch the defects and derive the prevention strategy earlier in the technology development stage. In this paper, we investigate an SRAM with tiny defects which passed in-line defect scan, WAT, CP and FT but failed in HTOL (High Temperature Operation Life) test, one of the product reliability qualification items. FA (Failure Analysis) reveals gate oxide missing defect is the root cause. The goal is to pass reliability qualification and release product into production on schedule. The failure mechanism, optimization of gate oxide process, enhancement of defect scan and testing methodology will be introduced. Experiment results show very good HTOL performance by the combination of process and testing optimization.     

具有非平面埋氧层的新型SOI材料的制备

提出一种基于SDB技术的非平面埋氧层SOI材料制备方法.其关键技术包括:通过干法刻蚀、高压氧化和淀积二氧化硅获得高质量非平面埋氧层;通过化学气相淀积多晶硅来形成键合缓冲层,并运用回刻光刻胶和化学机械抛光来实现键合面的局部和全局平坦化;通过室温真空贴合、中温预键合和高温加固键合来进行有源片和衬底片的牢固键合.基于该技术研制了有源层厚度为21μm、埋氧层厚度为0.943μm、顶面槽和底面槽槽高均为0.9μm的具有双面绝缘槽结构的非平面埋氧层新型SOI材料.测试结果表明该材料具有结合强度高、界面质量好、电学性能优良等优点.     

SOI／SDB超薄膜全耗尽隐埋n沟MOSFET的解析模型

本文给出了基于SDB材料的无PN结超薄膜全耗尽隐埋n沟型MOSFET的较明确的物理模型,详细分析了它的导电机理,给出了解析表达式.并将本模型的计算结果与实验结果进行了比较,同时进行了一些讨论.