Frequency and voltage dependence of negative capacitance in Au/SiO2/n-GaAs structures

The frequency (f) and bias voltage (V) dependence of electrical and dielectric properties of Au/SiO₂/n-GaAs structures have been investigated in the frequency range of 10 kHz–3 MHz at room temperature by considering the presence of series resistance (R_s). The values of R_s, dielectric constant (ε′), dielectric loss (ε″) and dielectric loss tangent (tan δ) of these structures were obtained from capacitance–voltage (C–V) and conductance–voltage (G/ω–V) measurements and these parameters were found to be strong functions of frequency and bias voltage. In the forward bias region, C–V plots show a negative capacitance (NC) behavior, hence ε′–V plots for each frequency value take negative values as well. Such negative values of C correspond to the maximum of the conductance (G/ω). The crosssection of the C–V plots appears as an abnormality when compared to the conventional behavior of ideal Schottky barrier diode (SBD), metal–insulator–semiconductor (MIS) and metal–oxide–semiconductor (MOS) structures. Such behavior of C and ε′ has been explained with the minority-carrier injection and relaxation theory. Experimental results show that the dielectric properties of these structures are quite sensitive to frequency and applied bias voltage especially at low frequencies because of continuous density distribution of interface states and their relaxation time.     

Dielectric characteristics of gamma irradiated Au/SnO2/n-Si/Au (MOS) capacitor

The dielectric characteristics of gamma irradiated Au/SnO₂/n-Si/Au (MOS) capacitor were studied. The MOS capacitor was irradiated by a ⁶⁰Co gamma radiation source with a dose rate of 0.69 kGy/h. The dielectric parameters such as dielectric constant (ε′), dielectric loss (ε″), loss factor (tan δ) and ac electrical conductivity (σ_ac) were calculated from the capacitance–voltage (C–V) and conductance–voltage (G/ω–V) measurements. It is found that the C and G/ω values decrease with the increasing total dose due to the irradiation-induced defects at the interface. Also, the calculated values of ε′, ε″ and σ_ac are found to decrease with an increased radiation dose. This result indicates that the dielectric characteristics of the MOS capacitor are sensitive to gamma-ray dose.     

Temperature dependent dielectric studies of Ni/n-GaP Schottky diodes by capacitance and conductance measurements

The dielectric properties of Ni/n-GaP Schottky diode were investigated in the temperature range 140–300 K by capacitance–voltage (C–V) and conductance–voltage (G/ω–V) measurements. The effect of temperature on series resistance (R_s) and interface state density (N_ss) were investigated. The dependency of dielectric constant (ε′), dielectric loss (ε′′), loss tangent (tan δ), ac conductivity (σ_ac), real (M′) and imaginary (M′′) parts of the electric modulus over temperature were evaluated and analyzed at 1 MHz frequency. The temperature dependent characteristics of ε′ and ε′′ reveal the contribution of various polarization effects, which increases with temperature. The Arrhenius plot of σ_ac shows two activation energies revealing the presence of two distinct trap states in the chosen temperature range. Moreover, the capacitance–frequency (C–f) measurement over 1 kHz to 1 MHz was carried out to study the effect of localized interface states.     

The effects of thermal annealing on the electrical characteristics of Au/n–InP/In diode

An Au/n–InP/In diode has been fabricated in the laboratory conditions and the current–voltage (I–V) and capacitance–voltage (C–V) characteristics of the diode have been measured in room temperature. In order to observe the effect of the thermal annealing, this diode has been annealed at temperatures 100 and 200 °C for 3 min in N₂ atmosphere. The characteristic parameters such as leakage current, barrier height and ideality factor of this diode have been calculated from the forward bias I–V and reverse bias C–V characteristics as a function of annealing temperature. Also the rectifying ratio of the diode is evaluated for as-deposited and annealed diode.     

The source of negative capacitance and anomalous peak in the forward bias capacitance-voltage in Cr/p-si Schottky barrier diodes (SBDs)

The frequency and voltage dependence of capacitance–voltage (C–V) and conductance-voltage (G/ω−V) characteristics of the Cr/p-Si metal semiconductor (MS) Schottky barrier diodes (SBDs) were investigated in the frequency and applied bias voltage ranges of 10 kHz to 5 MHz and (−4 V)−(+4 V), respectively, at room temperature. The effects of series resistance (R_s) and density distribution of interface states (N_ss), both on C–V and G/ω−V characteristics were examined in detail. It was found that capacitance and conductance, both, are strong functions of frequency and applied bias voltage. In addition, both a strong negative capacitance (NC) and an anomalous peak behavior were observed in the forward bias C–V plots for each frequency. Contrary to the behavior of capacitance, conductance increased with the increasing applied bias voltage and there happened a rapid increase in conductance in the accumulation region for each frequency. The extra-large NC in SBD is a result of the existence of R_s, N_ss and interfacial layer (native or deposited). In addition, to explain the NC behavior in the forward bias region, we drew the C–I and G/ω−I plots for various frequencies at the same bias voltage. The values of C decrease with increasing frequency at forward bias voltages and this decrease in the NC corresponds to an increase in conductance. The values of N_ss were obtained using a Hill–Coleman method for each frequency and it exhibited a peak behavior at about 30 kHz. The voltage dependent profile of R_s was also obtained using a Nicollian and Brews methods.     

The effect of frequency and temperature on capacitance/conductance–voltage (C/G–V) characteristics of Au/n-GaAs Schottky barrier diodes (SBDs)

The capacitance–voltage (C–V) and conductance–voltage (G/ω–V) characteristics of the Au/n-GaAs Schottky barrier diodes (SBDs) have been investigated for 10, 100 and 500 kHz at 80 and 280 K. To evaluate the reason of non-ideal behavior in C–V and G/ω–V plots, the measured C and G/ω values were corrected by taking into accounts series resistance effect. Experimental results show that the values of C and G/ω were found to be a strong function of interface states (N_ss) at inverse and depletion regions especially at low frequencies, but R_s is effective only at the accumulation region especially at high frequencies. Such behavior of the C and G/ω values may be attributed to an increase in polarization especially at low frequencies and the existence of N_ss or dislocations between metal and semiconductor. It can be concluded that the increase in C and G/ω at low frequencies especially at weak and depletion regions results from the existence of N_ss. The values of doping concentration (N_d) and barrier height (BH) between metal and semiconductor were also obtained from the linear part of high frequency (500 kHz) C⁻² vs. V plots at 80 and 280 K, respectively.     

Frequency and voltage dependency of interface states and series resistance in Al/SiO2/p-Si MOS structure

The capacitance–voltage (C–V) and conductance–voltage (G/ω–V) characteristics of Al/SiO₂/p-Si metal-oxide-semiconductor (MOS) Schottky diodes have been measured in the voltage range from ?3 to +3 V and frequency range from 5 KHz to 1 MHz at room temperature. It is found that both C and G/ω of the MOS capacitor are very sensitive to frequency. The fairly large frequency dispersion of C–V and G/ω–V characteristics can be interpreted in terms of the particular distribution of interface states at SiO₂/Si interface and the effect of series resistance. At relatively low frequencies, the interface states can follow an alternating current (AC) signal that contributes to excess capacitance and conductance. This leads to an anomalous peak of C–V curve in the depletion and accumulation regions. In addition, a peak at approximately ?0.2 V appears in the R_s–V profiles at low frequency. The peak values of the capacitance and conductance decrease with increasing frequency. The density distribution profile of interface state density (N_ss) obtained from C_HF–C_LF capacitance measurement also shows a peak in the depletion region.     

Determination of the laterally homogeneous barrier height of palladium Schottky barrier diodes on n-Ge (1 1 1)

We have studied the experimental linear relationship between barrier heights and ideality factors for palladium (Pd) on bulk-grown (1 1 1) Sb-doped n-type germanium (Ge) metal-semiconductor structures with a doping density of about 2.5×10¹⁵ cm^?3. The Pd Schottky contacts were fabricated by vacuum resistive evaporation. The electrical analysis of the contacts was investigated by means of current–voltage (I–V) and capacitance–voltage (C–V) measurements at a temperature of 296 K. The effective barrier heights from I–V characteristics varied from 0.492 to 0.550 eV, the ideality factor n varied from 1.140 to 1.950, and from reverse bias capacitance–voltage (C^?2–V) characteristics the barrier height varied from 0.427 to 0.509 eV. The lateral homogenous barrier height value of 0.558 eV for the contacts was obtained from the linear relationship between experimental barrier heights and ideality factors. Furthermore the experimental barrier height distribution obtained from I–V and (C^?2?V) characteristics were fitted by Gaussian distribution function, and their mean values were found to be 0.529 and 0.463 eV, respectively.     

Determination of contact parameters of Ni/n-GaP Schottky contacts

The electrical analysis of Ni/n-GaP structure has been investigated by means of current–voltage (I–V), capacitance–voltage (C–V) and capacitance–frequency (C–f) measurements in the temperature range of 120–320 K in dark conditions. The forward bias I–V characteristics have been analyzed on the basis of standard thermionic emission (TE) theory and the characteristic parameters of the Schottky contacts (SCs) such as Schottky barrier height (SBH), ideality factor (n) and series resistance (R_s) have been determined from the I–V measurements. The experimental values of SBH and n for the device ranged from 1.01 eV and 1.27 (at 320 K) to 0.38 eV and 5.93 (at 120 K) for Ni/n-GaP diode, respectively. The interface states in the semiconductor bandgap and their relaxation time have been determined from the C–f characteristics. The interface state density N_ss has ranged from 2.08 × 10¹⁵ (eV^?1 m^?2) at 120 K to 2.7 × 10¹⁵ (eV^?1 m^?2) at 320 K. C_ss has increased with increasing temperature. The relaxation time has ranged from 4.7 × 10^?7 s at 120 K to 5.15 × 10^?7 s at 320 K.     

Evaluation of lateral barrier height of inhomogeneous photolithography-fabricated Au/n-GaAs Schottky barrier diodes from 80 K to 320 K

In order to evaluate current conduction mechanism in the Au/n-GaAs Schottky barrier diode (SBD) some electrical parameters such as the zero-bias barrier height (BH) Φ_bo(I–V) and ideality factor (n) were obtained from the forward bias current–voltage (I–V) characteristics in wide temperature range of 80–320 K by steps of 10 K. By using the thermionic emission (TE) theory, the Φ_bo(I–V) and n were found to depend strongly on temperature, and the n decreases with increasing temperature while the Φ_bo(I–V) increases. The values of Φ_bo and n ranged from 0.600 eV and 1.51(80 K) to 0.816 eV and 1.087 (320 K), respectively. Such behavior of Φ_bo and n is attributed to Schottky barrier inhomogeneities by assuming a Gaussian distribution (GD) of BHs at Au/n-GaAs interface. In the calculations, the electrical parameters of the experimental forward bias I–V characteristics of the Au/n-GaAs SBD with the homogeneity in the 80–320 K range have been explained by means of the TE, considering GD of BH with linear bias dependence.     

Origin of forward bias capacitance peak and intersection behavior of C and G/w of Ag/p-InP Schottky barrier diodes

Frequency-dependent electrical characteristics of Ag/p-InP diodes have been determined using impedance spectroscopy at room temperature. Series resistance (R_s) and interface state(s) (N_ss) values were extracted from capacitance (C) and conductance (G/w) data using the Nicollian and Goetzberger and Hill–Coleman methods, respectively. C and G/w data were also corrected in the whole measured bias voltage range to obtain real diode capacitance C_c and conductance G_c values in order to see the effects of R_s. Both the C–V and R_s–V plots showed anomalous peak in depletion region especially at low frequencies due to the existence of N_ss. C–V and G/w–V plots crossed at a certain bias voltage and this point shifted toward negative bias voltages with increasing frequency and then disappeared at 3 MHz. Also, decrease in C values corresponds to an increase in G/w values in the same bias voltages.     

Characteristics of RF reactive sputter-deposited Pt/SiO2/n-InGaN MOS Schottky diodes

All RF sputtering-deposited Pt/SiO₂/n-type indium gallium nitride (n-InGaN) metal–oxide–semiconductor (MOS) diodes were investigated before and after annealing at 400 °C. By scanning electron microscopy (SEM), the thickness of Pt, SiO_2, n-InGaN layer was measured to be ~250, 70, and 800 nm, respectively. AFM results also show that the grains become a little bigger after annealing, the surface topography of the as-deposited film was smoother with the rms roughness of 1.67 nm and had the slight increase of 1.92 nm for annealed sample. Electrical properties of MOS diodes have been determined by using the current–voltage (I–V) and capacitance–voltage (C–V) measurements. The results showed that Schottky barrier height (SBH) increased slightly to 0.69 eV (I–V) and 0.82 eV (C–V) after annealing at 400 °C for 15 min in N₂ ambient, compared to that of 0.67 eV (I–V) and 0.79 eV (C–V) for the as-deposited sample. There was the considerable improvement in the leakage current, dropped from 6.5×10⁻⁷ A for the as-deposited to 1.4×10⁻⁷ A for the 400 °C-annealed one. The annealed MOS Schottky diode had shown the higher SBH, lower leakage current, smaller ideality factor (n), and denser microstructure. In addition to the SBH, n, and series resistance (R_s) determined by Cheungs׳ and Norde methods, other parameters for MOS diodes tested at room temperature were also calculated by C–V measurement.     

Investigations on electrical characteristics and reliability properties of MOS capacitors using HfAlOx on n-GaAs substrates

Radio frequency sputtering system is employed to fabricate metal oxide semiconductor (MOS) capacitors using an ultra-thin layer of HfAlO_x dielectric deposited on n-GaAs substrates with and without a Si interface control layer incorporated in between the dielectric and the semiconductor. Measurements are performed to obtain capacitance voltage (C–V) and current voltage (I–V) characteristics for GaAs/Si/HfAlO_x and GaAs/HfAlO_x capacitors under different constant voltage and constant current stress conditions. The variation of different electrical parameters such as change in interface trap density, hysteresis voltage with various values of constant voltage stress and the dependence of flat band voltage, fractional change in gate leakage current density, etc. with stress time are extracted from the C–V and I–V data for capacitors with and without a Si interlayer. Further the trap charge density and the movement of trap centroid are investigated for various injected influences. The dielectric breakdown and reliability properties of the dielectric films are studied using constant voltage stressing. A high time-dependent dielectric breakdown (TDDB, t_bd ? 1350 s) is observed for HfAlO_x gate dielectric with a silicon inter-layer under the high constant voltage stress at 8 V. Compared to capacitors without a Si interlayer, MOS capacitors with a Si interlayer exhibit improved electrical and breakdown characteristics, and excellent interface and reliability properties.     

Electrical and photovoltaic properties of SnSe/Si heterojunction

Thin film of SnSe is deposited on n-Si single crystal to fabricate a p-SnSe/n-Si heterojunction photovoltaic cell. Electrical and photoelectrical properties have been studied by the current density–voltage (J–V) and capacitance–voltage (C–V) measurements at different temperatures. The fabricated cell exhibited rectifying characteristics with a rectification ratio of 131 at ±1 V. At low voltages (V<0.55 V), the dark forward current density is controlled by the multi-step tunneling mechanism. While at a relatively high voltage (V>0.55 V), a space charge-limited-conduction mechanism is observed with trap concentration of 2.3×10²¹ cm⁻³. The C–V measurements showed that the junction is of abrupt nature with built-in voltage of 0.62 V which decreases with temperature by a gradient of 2.83×10⁻³ V/K. The cell also exhibited strong photovoltaic characteristics with an open-circuit voltage of 425 mV, a short-circuit current density of 17.23 mA cm⁻² and a power conversion efficiency of 6.44%. These parameters have been estimated at room temperature and under light illumination provided by a halogen lamp with an input power density of 50 mW cm⁻².     

Transport and storage properties of CrSi2/Si junctions made using the CAPVD technique

p-CrSi₂/n-crystSi and p-CrSi₂/p-crystSi hetero junctions produced by cathodic arc physical vapor deposition were worked out by means of capacitance–voltage–temperature (C–V–T) and current–voltage–temperature (I–V–T) measurements to investigate storage and transport properties. Former measurement on p-CrSi₂/n-crystSi structure confirmed an abrupt type junction together with a building voltage at the proximity of 0.7 V. Though a fairly well rectification ratio (10³ at ±2 V) was realized by I–V measurement, it became deteriorated with the increase in ambient temperature. From temperature dependence of I–V variations, distinct conduction mechanisms were identified. In forward (reverse) direction trap assisted single-multistep tunneling recombination (generation) and space-charge limited current flow that corresponded to low and high bias voltage regions, respectively, were identified. Moreover, an activation energy (E_A) determined from the slopes of I–V–T curves as 0.22 and 0.26 eV was interpreted as the energy position of a chromium–boron (Cr–B) complex-type point defect residing in n/p doped c-Si semiconductor in CrSi₂/n–c-Si and CrSi₂/p–c-Si junctions. The retrieved E_A was in agreement with the recent DLTS measurement. Based on the experimental observations, schematic current path was built to interpret I–V/C–V behaviors. The model was successful in explaining the decrease in measured capacitance under large forward bias voltage reported for the first time by us for the present CrSi₂/Si junctions.     

Adaptation of admittance analysis to extract interface traps of a-Si:H/c-Si heterojunctions

Complete admittance expressions, adapted from the equations previously presented for Metal/Oxide/Semiconductor (MOS) structure, were derived and modified admittance approach was successfully applied on a-Si:H/c-Si heterojunction to deduce surface state density (N_ss) by employing capacitance–voltage (C–V) and conductance–voltage (G/ω–V) measurements. Through the approach, N_ss was determined as 6×10¹² cm⁻² eV⁻¹ that was mutually checked by continuum model, used previously for evaluating N_ss in MOS structure. Furthermore, locating such an amount at the interface of a-Si:H and c-Si, experimentally measured C–V curve was reproduced through AFORS-HET simulation program. Presence of such a large amount of N_ss was originated due to native oxide layer, confirmed through spectroscopic elipsometry measurement.     

High performance sol–gel spin-coated titanium dioxide dielectric based MOS structures

High-κ TiO₂ thin films have been fabricated using cost effective sol–gel and spin-coating technique on p-Si (100) wafer. Plasma activation process was used for better adhesion between TiO₂ films and Si. The influence of annealing temperature on the structure-electrical properties of titania films were investigated in detail. Both XRD and Raman studies indicate that the anatase phase crystallizes at 400 °C, retaining its structural integrity up to 1000 °C. The thickness of the deposited films did not vary significantly with the annealing temperature, although the refractive index and the RMS roughness enhanced considerably, accompanied by a decrease in porosity. For electrical measurements, the films were integrated in metal-oxide-semiconductor (MOS) structure. The electrical measurements evoke a temperature dependent dielectric constant with low leakage current density. The Capacitance–voltage (C–V) characteristics of the films annealed at 400 °C exhibited a high value of dielectric constant (~34). Further, frequency dependent C–V measurements showed a huge dispersion in accumulation capacitance due to the presence of TiO₂/Si interface states and dielectric polarization, was found to follow power law dependence on frequency (with exponent ‘s’=0.85). A low leakage current density of 3.6×10⁻⁷ A/cm² at 1 V was observed for the films annealed at 600 °C. The results of structure-electrical properties suggest that the deposition of titania by wet chemical method is more attractive and cost-effective for production of high-κ materials compared to other advanced deposition techniques such as sputtering, MBE, MOCVD and ALD. The results also suggest that the high value of dielectric constant ‘κ‘ obtained at low processing temperature expands its scope as a potential dielectric layer in MOS device technology.     

Dielectric properties in Au/SnO2/n-Si (MOS) structures irradiated under Co-γ rays

The metal-oxide-semiconductor (MOS) structures with insulator layer thickness range of 55-430 Å were stressed with a bias of 0 V during ⁶⁰Co-γ ray source irradiation with the dose rate of 2.12 kGy/h and the total dose range was 0-5×10⁵ Gy. The real part of dielectric constant ε′, dielectric loss ε″, dielectric loss tangent tanδ and the dc conductivity σ_dc were determined from against frequency, applied voltage, dose rate and thickness of insulator layer at room temperature for Au/SnO₂/n-Si (MOS) structures from C-V capacitance and G-V conductance measurements in depletion and weak inversion before and after irradiation. The dielectric properties of MOS structures have been found to be strongly influenced by the presence of dominant radiation-induced defects. The frequency, applied voltage, dose rate and thickness dependence of ε′, ε″, tanδ and σ_dc are studied in the frequency (500 Hz-10 MHz), applied voltage (−10 to 10 V), dose rate (0-500 kGy) and thickness of insulator layer (55-430 Å) range, respectively. In general, dielectric constant ε′, dielectric loss ε″ and dielectric loss tangent are found to decrease with increasing the frequency while σ_dc is increased. Experimental results shows that the interfacial polarization can be more easily occurred at the lower frequency and/or with the number of density of interface states between Si/SnO₂ interfaces, consequently, contribute to the improvement of dielectric properties of Au/SnO₂/n-Si (MOS) structures.     

Study on the basic capacitance–voltage characteristics of organic molecular semiconductors

Capacitance–voltage (C–V) characteristics of organic molecular semiconductors attracted much research interest recently, but no convincing physical mechanism has been established so far. In this work, the C–V characteristics of pentacene-based devices have been systematically investigated at various frequencies. Only one peak occurs when the measuring frequency is less than 3 kHz or greater than 8 kHz. While within the frequency range between the two, two C–V peaks are observed with quite different dependence on temperature, which suggests that the origins of these two C–V peaks are respectively mobile holes and trapped carriers. This conclusion is also experimentally validated with the C–V characteristics of intentionally doped devices.     

Electrical parameters of a DC sputtered Mo/n-type 6H-SiC Schottky barrier diode

A Mo/n-type 6H-SiC/Ni Schottky barrier diode (SBD) was fabricated by sputtering Mo metal on n-type 6H-SiC semiconductor. Before the formation of Mo/n-type 6H-SiC SBD, an ohmic contact was formed by thermal evaporation of Ni on n-type 6H-SiC and annealing at 950 °C for 10 min. It was seen that the structure had excellent rectification. The electrical parameters were extracted using its current–voltage (I–V) and capacitance–voltage (C–V) measurements carried out at room temperature. Very high (1.10 eV) barrier height and 1.635 ideality factor values were reported for Mo/n-type 6H-SiC using ln I–V plot. The barrier height and series resistance values of the diode were also calculated as 1.413 eV and 69 Ω from Norde׳s functions, respectively. Furthermore, 1.938 eV barrier height value of Mo/n-type 6H-SiC SBD calculated from C–V measurements was larger than the one obtained from I–V data.