Low-power performance of 0.5-μm JFET for low-cost MMIC's inpersonal communications

The low-power microwave performance of an enhancement-mode ion-implanted GaAs JFET is reported. A 0.5-μm×100-μm E-JFET with a threshold voltage of V_th=0.3 V achieved a maximum DC transconductance of g_m=489 mS/mm at V _ds=1.5 V and I_ds=18 mA. Operating at 0.5 mW of power with V_ds=0.5 V and I_ds =1 mA, the best device on a 3-in wafer achieved a noise figure of 0.8 dB with an associated gain of 9.6 dB measured at 4 GHz. Across a 3-in wafer the average noise figure was F_min=1.2 dB and the average associated gain was G_a=9.8 dB for 15 devices measured. These results demonstrate that the E-JFET is an excellent choice for low-power personal communication applications     

Super low noise InGaP gated PHEMT

Very high performance InGaP/InGaAs/GaAs PHEMTs will be demonstrated. The fabricated InGaP gated PHEMTs devices with 0.25 × 160/cm² and 0.25 × 300 μm² of gate dimensions show 304 mA/mm and 330 mA/mm of saturation drain current at V_GS = 0 V, V_DS = 2 V, and 320 mS/mm and 302 mS/mm of extrinsic transconductances, respectively. Noise figures for 160 μm and 300 μm gate-width devices at 12 GHz are measured to be 0.46 dB with a 13 dB associated gain and 0.49 dB with a 12.85 dB associated gain, respectively. With such a high gain and low noise, the drain-to-gate breakdown voltage can be larger than 11 V. Standard deviation in the threshold voltage of 22 mV for 160 μm gate-width devices across a 4-in wafer can be achieved using a highly selective wet recess etching process. Good thermal stability of these InGaP gated PHEMTs is also presented     

80-GHz Tuned Amplifier in Bulk CMOS

An 80-GHz six-stage common source tuned amplifier has been demonstrated using low leakage (higher V_T) NMOS transistors of a 65-nm digital CMOS process with six metal levels. It achieves power gain of 12 dB at 80 GHz with a 3-dB bandwidth of 6 GHz, noise figures (NF's) lower than 10.5 dB at frequencies between 75 and 81 GHz with the lowest NF of 9 dB. IP_{1 dB} is -21 dBm and IIP3 is -11.5 dBm. The amplifier consumes 27 mA from a 1.2 V supply. At V_DD = 1.5 V and 33 mA bias current, NF is less than 9.5 dB within the 3-dB bandwidth and reaches a minimum of 8 dB at 80 GHz.     

DC, RF, and microwave noise performances of AlGaN/GaN HEMTs on sapphire substrates

High-performance AlGaN/GaN high electron-mobility transistors with 0.18-/spl mu/m gate length have been fabricated on a sapphire substrate. The devices exhibited an extrinsic transconductance of 212 mS/mm, a unity current gain cutoff frequency (f/sub T/) of 101 GHz, and a maximum oscillation frequency (f/sub MAX/) of 140 GHz. At V/sub ds/=4 V and I/sub ds/=39.4 mA/mm, the devices exhibited a minimum noise figure (NF/sub min/) of 0.48 dB and an associated gain (Ga) of 11.16 dB at 12 GHz. Also, at a fixed drain bias of 4 V with the drain current swept, the lowest NFmin of 0.48 dB at 12 GHz was obtained at I/sub ds/=40 mA/mm, and a peak G/sub a/ of 11.71 dB at 12 GHz was obtained at I/sub ds/=60 mA/mm. With the drain current held at 40 mA/mm and drain bias swept, the NF/sub min/,, increased almost linearly with the increase of drain bias. Meanwhile, the Ga values decreased linearly with the increase of drain bias. At a fixed bias condition (V/sub ds/=4 V and I/sub ds/=40 mA/mm), the NF/sub min/ values at 12 GHz increased from 0.32 dB at -55/spl deg/C to 2.78 dB at 200/spl deg/C. To our knowledge, these data represent the highest f/sub T/ and f/sub MAX/, and the best microwave noise performance of any GaN-based FETs on sapphire substrates ever reported.     

基于无线功率放大器应用的多指结构SiGe HBT

采用简单的双台面工艺制作了完全平面结构的5个单元、10个发射极指大面积的SiGe HBT.器件表现出了良好的直流和高频特性,最大电流增益β为214.BVCEO为9V,集电极掺杂浓度为1×1017 cm-3,厚度为400nm时,BVCBO为16V.在直流偏置下IC=30mA,VCE=3.0V得到fT和fmax分别为18.0GHz和19.3GHz,1GHz下最大稳定增益为24.5dB,单端功率增益为26.6dB.器件采用了新颖的分单元结构,在大电流下没有明显的增益塌陷现象和热效应出现.     

应用于IEEE 802.11b无线局域网系统的2.4GHzCMOS单片收发机射频前端

实现了一个应用于IEEE 802.11b无线局域网系统的2.4GHz CMOS单片收发机射频前端,它的接收机和发射机都采用了性能优良的超外差结构.该射频前端由五个模块组成:低噪声放大器、下变频器、上变频器、末前级和LO缓冲器.除了下变频器的输出采用了开漏级输出外,各模块的输入、输出端都在片匹配到50Ω.该射频前端已经采用0.18μm CMOS工艺实现.当低噪声放大器和下变频器直接级联时,测量到的噪声系数约为5.2dB,功率增益为12.5dB,输入1dB压缩点约为-18dBm,输入三阶交调点约为-7dBm.当上变频器和末前级直接级联时,测量到的噪声系数约为12.4dB,功率增益约为23.8dB,输出1dB压缩点约为1.5dBm,输出三阶交调点约为16dBm.接收机射频前端和发射机射频前端都采用1.8V电源,消耗的电流分别为13.6和27.6mA.     

A low power high gain UWB LNA in 0.18-μm CMOS

A low power high gain differential UWB low noise amplifier (LNA) operating at 3-5 GHz is presented.A common gate input stage is used for wideband input matching; capacitor cross coupling (CCC) and current reuse techniques are combined to achieve high gain under low power consumption. The prototypes fabricated in 0.18-μm CMOS achieve a peak power gain of 17.5 dB with a -3 dB bandwidth of 2.8-5 GHz, a measured minimum noise figure (NF) of 3.35 dB and -12.6 dBm input-referred compression point at 5 GHz, while drawing 4.4 mA from a 1.8 V supply. The peak power gain is 14 dB under a 4.5 mW power consumption (3 mA from a 1.5 V supply). The proposed differential LNA occupies an area of 1.01 mm~2 including test pads.     

Design of 20-44 GHz broadband doubler MMIC

This paper presents the design and performance of a broadband millimeter-wave frequency doubler MMIC using active 0.15 μm GaAs PHEMT and operating at output frequencies from 20 to 44 GHz. This chip is composed of a single ended-into differential-out active Balun, balanced FETs in push-push configuration, and a distributed amplifier. The MMIC doubler exhibits more than 4 dB conversion gain with 12 dBm of output power, and the fundamental frequency suppression is typically -20 dBc up to 44 GHz. The MMIC works at VDD = 3.5 V, VSS = -3.5 V, Id = 200 mA and the chip size is 1.5 ×1.8 mm2.     

Monolithic SiGe HBT Feedforward Variable Gain Amplifiers for 5 GHz Applications

Monolithic SiGe heterojunction bipolar transistor (HBT) variable gain amplifiers (VGAs) with a feedforward configuration have been newly developed for 5 GHz applications. Two types of the feedforward VGAs have been made: one using a coupled‐emitter resistor and the other using an HBT‐based current source. At 5.2 GHz, both of the VGAs achieve a dynamic gain‐control range of 23 dB with a control‐voltage range from 0.4 to 2.6 V. The gain‐tuning sensitivity is 90 mV/dB. At V_CTRL= 2.4 V, the 1 dB compression output power, P_1‐dB, and dc bias current are 0 dBm and 59 mA in a VGA with an emitter resistor and ‐1.8 dBm and 71mA in a VGA with a constant current source, respectively.     

Small-signal gain performance of the permeable base transistor at EHF

The small-signal amplifier performance at 40.5 GHz is reported for a GaAs permeable base transistor (PBT) having a base grating of 3200-Å periodicity and 1-mm periphery. The device was embedded in a microstrip circuit with appropriate matching networks and biased for optimal small-signal gain with Vbe= 0.2 V, Vce= 2.0 V, and Ice= 59 mA. The prototype amplifier achieved 11 dB of stable gain at 40.5 GHz. The circuit design was facilitated by the moderate impedance levels and highly unilateral nature of the PBT.     

K波段反馈式MMIC中功率放大器

给出了一种基于功率PHEMT工艺技术设计加工的K波段反馈式MMIC宽带功率放大器。在21～29GHz的工作频段内,当漏极电压为6V、栅电压为-0.25V、电流为111mA时,1dB压缩点输出功率大于21dBm,小信号增益在13±1.5dB,输入驻波比小于3,输出驻波比均小于1.7。芯片尺寸:1mm×2.5mm×0.1mm。同时给出了一种芯片级电磁场仿真验证方法,用该方法仿真的结果和测试结果非常一致,保证了电路设计的准确性。     

A 60-dB 246-MHz CMOS variable gain amplifier for subsampling GSM receivers

A variable gain amplifier (VGA) is designed for a GSM subsampling receiver. The VGA is implemented in a 0.35-/spl mu/m CMOS process and approximately occupies 0.64 mm/sup 2/. It operates at an IF frequency of 246 MHz. The VGA provides a 60-dB digitally controlled gain range in 2-dB steps. The overall gain accuracy is less than 0.3 dB. The current is 9 mA at 3 V supply. The noise figure at maximum gain is 8.7 dB. The IIP3 is -4 dBm at minimum gain, while the OIP3 is -1 dBm at maximum gain. The group delay is 1.5 ns across 5-MHz bandwidth.     

Adaptive antenna receiver module for WLAN at C-band with low-power consumption

A low-power consuming adaptive antenna receiver module at C-band for 802.11a and HIPERLAN is presented. The highly integrated GaAs microwave monolithic integrated circuit consists of low noise amplifiers, calibration switches and a vector modulator with 360/spl deg/ phase control and over 15 dB gain control. At 5.2 GHz, the module has a maximum gain of 12.5 dB, a noise figure of 2.7 dB, and a 1 dB output compression point of -7 dBm. The module draws only 2.3 mA up to 3.5 mA from a 2.7 V supply. Chip size is 1.9 mm /spl times/ 1.6 mm.     

4H-SiC MESFET with 2.8 W/mm power density at 1.8 GHz

MESFET's were fabricated using 4H-SiC substrates and epitaxy. The D.C., S-parameter, and output power characteristics of the 0.7 μm gate length, 332 μm gate width MESFET's were measured. At ν_ds =25 V the current density was about 300 mA/mm and the maximum transconductance was in the range of 38-42 mS/mm. The device had 9.3 dB gain at 5 GHz and f_max=12.9 GHz. At V_ds=54 V the power density was 2.8 W/mm with a power added efficiency=12.7%     

多晶发射极双台面微波功率SiGe HBT

研制成功了可商业化的75mm单片超高真空化学气相淀积锗硅外延设备SGE500,并生长了器件级SiGe HBT材料.研制了具有优良小电流特性的多晶发射极双台面微波功率SiGe HBT器件,其性能为:β=60@VCE/IC=9V/300μA,β=100@5V/50mA,BVCBO=22V,ft/fmax=5.4GHz/7.7GHz@10指,3V/10mA.多晶发射极可进一步提供直流和射频性能的折衷,该工艺总共只有6步光刻,与CMOS工艺兼容且(因多晶发射极)无需发射极外延层的生长,这些优点使其适合于商业化生产.利用60指和120指的SiGe HBT制作了微波锗硅功率放大器.60指功放在900MHz和3.5V/0.2A偏置时在1dB压缩点给出P1dB/Gp/PAE＝22dBm/11dB/26.1%.120指功放900MHz工作时给出了Pout/Gp/PAE＝33.3dBm (2.1W)/10.3dB/33.9%@11V/0.52A.     

A dual-band reconfigurable direct-conversion receiver RF front-end

6 dBm at 2.2 GHz, and a gain of 18.8 dB and IIP3 of 7.3 dBm at 4.5 GHz. The whole front-end consumes 12 mA current at 1.2 V voltage supply for the LNA and 2.1 mA current at 1.8 V for the mixer, with a die area of 1.2 × 1 mm2.     

60-GHz high power performance In/sub 0.35/Al/sub 0.65/As-In/sub 0-35/Ga/sub 0.65/As metamorphic HEMTs on GaAs

We report on a double-pulse doped, double recess In/sub 0.35/Al/sub 0.65/As-In/sub 0.35/Ga/sub 0.65/As metamorphic high electron mobility transistor (MHEMT) on GaAs substrate. This 0.15-/spl mu/m gate MHEMT exhibits excellent de characteristics, high current density of 750 mA/mm, extrinsic transconductance of 700 mS/mm. The on and off state breakdown are respectively of 5 and 13 V and defined It gate current density of 1 mA/mm. Power measurements at 60 GHz were performed on these devices. Biased between 2 and 5 V, they demonstrated a maximum output power of 390 mW/mm at 3.1 V of drain voltage with 2.8 dB power gain and a power added efficiency (PAE) of 18%. The output power at 1 dB gain compression is still of 300 mW/mm. Moreover, the linear power gain is of 5.2 dB. This is to our knowledge the best output power density of any MHEMT reported at this frequency.     

A Four‐Channel Laser Array with Four 10 Gbps Monolithic EAMs Each Integrated with a DBR Laser

A distributed Bragg reflector (DBR) laser and a high speed electroabsorption modulator (EAM) are integrated on the basis of the selective area growth technique. The typical threshold current is 4 to 6 mA, and the side mode suppression ratio is over 40 dB with single mode operation at 1550 nm. The DBR laser exhibits 2.5 to 3.3 mW fiber output power at a laser gain current of 100 mA, and a modulator bias voltage of 0 V. The 3 dB bandwidth is 13 GHz. A 10 Gbps non‐return to zero operation with 12 dB extinction ratio is obtained. A four‐channel laser array with 100 GHz wavelength spacing was fabricated and its operation at the designed wavelength was confirmed.     

A Ku-Band Interference-Rejection CMOS Low-Noise Amplifier Using Current-Reused Stacked Common-Gate Topology

A Ku-band CMOS low-noise amplifier (LNA) with high interference-rejection (IR), wide gain control range, and low dc power consumption is presented. The LNA consists of two common-gate metal-oxide-semiconductor field-effect transistors interconnected with an interstage parallel tank for the IR. The stacked common-gate stages share the same dc bias current to reduce power consumption and have controllable gain by changing this dc current. The implemented 0.13 mum CMOS LNA achieves measured power gain of 10.8 dB, noise figure of 4.2 dB, output P₁ dB of -4.3 dBm at 15 GHz, while rejecting interference down to a 38.5 dB level. The gain control range is 23.3 dB by varying the gate voltage from 0.2 to 1.2 V. The LNA consumes only 4 mA from a 1.3-V supply.     

A dual mode 2.4-GHz CMOS low noise amplifier employing body biasing

This paper presents a dual mode CMOS low noise amplifier (LNA) suitable for Worldwide Interoperability for Microwave Access applications, at 2.4?GHz. The design concept is based on body biasing. An off chip Digital to Analog Converter is used to generate the proper body bias voltage to control the LNA gain and linearity. Measurement results show that in the high gain mode, for V _BS?=?0.3?V, the cascode LNA, implemented in a 0.13???m CMOS standard process, exhibits a 14?dB power gain, a 3.6?dB noise figure (NF) and ?4.6?dBm of third order intercept point (IIP3) for a 4?mA current consumption under 1?V supply. Tuning V _BS to ?0.55?V, switches the LNA into the low gain mode. It achieves 8.6?dB power gain, 6.2?dB NF and 6?dBm IIP3 under a constrained power consumption of 1.7?mW.