A clock distribution network for microprocessors

A global clock distribution strategy used on several microprocessor chips is described. The clock network consists of buffered tunable trees or treelike networks, with the final level of trees all driving a single common grid covering most of the chip. This topology combines advantages of both trees and grids. A new tuning method was required to efficiently tune such a large strongly connected interconnect network consisting of up to 6 m of wire and modeled with 50000 resistors, capacitors, and inductors. Variations are described to handle different floor-planning styles. Global clock skew as low as 22 ps on large microprocessor chips has been measured     

一种高精度时钟同步电路

本文提出了一种基于交错延迟单元和动态补偿电路的高精度时钟同步电路结构,HPSC,并 可用在对时钟要求较高的大规模分布网络中。此电路采用了基于SMD的粗调结构和动态补偿 电路的细调结构,可在两个时钟周期内完成粗调并在接下来三个时钟周期内完成细调,其误 差小于3.8 ps。本电路使用SMIC 0.13 μm 1P6M 工艺设计并实现,供电电压1.2 V。其输入 频率为200MHz-800MHz,占空比为20%-80%,有效面积 245μm×134μm,功耗为1.64 mW@500MHz     

A 4-GHz clock system for a high-performance system-on-a-chip design

A digital system's clocks must have not only low jitter, but also well-controlled duty cycles in order to facilitate versatile clocking techniques. Power-supply noise is often the most common and dominant source of jitter on a phase-locked loop's (PLL) output clock. Jitter can be minimized by regulating the supply to the PLL's noise-sensitive analog circuit blocks in order to filter out supply noise. This paper introduces a PLL-based clock generator intended for use in a high-speed highly integrated system-on-a-chip design. The generator produces clocks with accurate duty cycles and phase relationships by means of a high-speed divider design. The PLL also achieves a power-supply rejection ratio (PSRR) greater than 40 dB while operating at frequencies exceeding 4 GHz. The high level of noise rejection exceeds that of earlier designs by using a combination of both passive and active filtering of the PLL's analog supply voltage. The PLL system has been integrated in a 0.15-μm single-poly 5-metal digital CMOS technology. The measured performance indicates that at a 4-GHz output frequency the circuit achieves a PSRR greater than 40 dB. The peak cycle-to-cycle jitter is 25 ps at 700 MHz and a 2.8-GHz VCO frequency with a 500-mV step on the regulator's 3.3-V supply. The total power dissipated by the prototype is 130 mW and its active area is 1.48×1.00 mm²     

快速buffer添加算法

在深亚微米设计中,连线延迟时间已经超过器件延迟时间,成为影响性能的瓶颈之一。在线网中插入缓冲器（buffer）是改善线延迟的一种有效方法,但是目前基于缓冲器块（bufferblock）的方法一般因其计算量比较大,算法比较慢,并且也增加布局（floorplan）的复杂性。为此本文提出并实现了一种新的快速算法来解决芯片顶层互连中缓冲器添加问题。     

Improved clock buffer with high PSRR for SC circuit applications

Clock feedthrough in SC circuits results in low PSRR figures, incompatible with high-performance signal processing. A high-PSRR CMOS clock buffer is presented here, which blocks this power supply (PS) noise coupling path. The presented circuit is a significant improvement over an earlier circuit proposed by the same author, but having a PSRR of over 40 dB now.<>     

A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation

This paper describes a fully integrated low-jitter CMOS phase-locked loop and clock buffer for low-power digital systems with a wide range of operating frequencies. The design uses static CMOS inverters as a building block of the voltage-controlled oscillator and clock buffering. To reduce supply-induced jitter, programmable circuits with opposite sensitivity compensate for the delay variations. Both elements have supply-induced delay sensitivity of /spl les/0.1%-delay/1%-V/sub DD/. The design is fabricated in 0.25-/spl mu/m CMOS technology and consumes 10mW from a 2.5-V supply. The experimental results verify that the proposed methods significantly improve the jitter.     

CMOS optoelectronic components for clock distribution

Optoelectronic components for clock distribution that are fully compatible with all standard CMOS processes are described. Waveguide cores are silicon nitride, while the waveguide cladding is silicon dioxide. Polysilicon photodetectors offer responsivities up to 1.3 A/W, 10-90% rise time of 0.58 ns, and full-width half-max duration of 0.85 ns. Power budget calculations indicate that 1 μA of photocurrent from the end node detectors can be achieved with only 48 μW of optical power input into a 16-node H-tree.     

A one-wire approach for skew-compensating clock distribution basedon bidirectional techniques

A clock-deskew buffer using the delay-locked loop and the bidirectional technique has been developed. It needs only one wire to synchronize the clocks for a chip-to-chip system. It has been fabricated by a 0.35-μm n-well CMOS process. Experimental results demonstrate that it can achieve the peak-to-peak jitter smaller than 100 ps through a two-meter coaxial cable while operating at the frequency of 120 MHz. The total power dissipation of the skew buffer is 218 mW for a 3 V supply. The core chip area is 980×1700 μm²     

A 250-622 MHz deskew and jitter-suppressed clock buffer usingtwo-loop architecture

A 250-622 MHz clock buffer has been developed, using a two-loop architecture: a delay-locked loop (DLL) for deskew, and a frequency-locked loop (FLL) for reference frequency supply to the DLL. The DLL incorporates a current-mode phase detector which utilizes a flip-flop metastability to detect a phase difference in the order of 20 ps. A measured jitter is suppressed to less than 40 ps RMS over the operating frequency range. A DLL acquisition time of 150 ns typical is simulated at 400 MHz. A 0.4-μm CMOS technology is used to fabricate the chip     

Design methodology for synthesizing clock distribution networksexploiting nonzero localized clock skew

An integrated top-down design methodology is presented in this brief for synthesizing high performance clock distribution networks based on application dependent localized clock skew. The methodology is divided into four phases: (1) determining an optimal clock skew schedule composed of a set of nonzero clock skew values and the related minimum clock path delays; (2) designing the topology of the clock distribution network with delays assigned to each branch based on the circuit hierarchy, the aforementioned clock skew schedule, and minimizing process and environmental delay variations; (3) designing circuit structures to emulate the delay values assigned to the individual branches of the clock tree; and (4) designing the physical layout of the clock distribution network. The clock distribution network synthesis methodology is based on CMOS technology. The clock lines are transformed from distributed resistive capacitive interconnect lines into purely capacitive interconnect lines by partitioning the RC interconnect lines with inverting repeaters. Variations in process parameters are considered during the circuit design of the clock distribution network to guarantee a race-free circuit. Nominal errors of less than 2.5% for the delay of the clock paths and 7% for the clock skew between any two registers belonging to the same global data path as compared with SPICE Level-3 are demonstrated     

一种基于分频链的时钟校准方法

针对晶体振荡器的温漂特性,设计了一种基于分频链的时钟校准算法。在不改变晶体振荡器的情况下可调节时钟频率,校准精度达±0.25ppm,校准范围±32ppm,通过多次实验分析,用Verilog-HDL语言编写全部模块,在modelsim6.2b软件中实现模块仿真。全部功能正常实现,符合设计要求。     

Optical broadcast and clock distribution for multi-chip-modules

In this letter, we report a new architecture for clock and broadcast distribution using optical interconnect components, such as vertical cavity surface emitting lasers (VCSEL) and pin photodiodes with benefits of diffractive optical elements (DOE) fan-out. A two-bit-large bus for broadcast or clock distribution demonstration is presented using collective wiring technologies and MCM hybridization process in a standard BGA package. Diffractive optical elements allow one to four distribution scene through an optical plate. Specific laser drivers for VCSELs and photodiode receiver are realized in complete CMOS 0.6 μm transmitter and receiver chips.     

A design methodology for low-leakage and high-performance buffer based on deviant behavior of gate leakage

Based on the observation that both subthreshold and gate leakage depend on transistors width, this paper introduces a feasible method to fast estimate leakage current in buffers. In simulating of leakage current with swept transistor width, we found that gate leakage is not always a linear function of the device geometry. Subsequently, this paper presented the theoretical analysis and ex- perimental evidence of this exceptional gate leakage behavior and developed a design methodology to devise a low-leakage and high-performance buffer with no penalty in area using this deviation.     

一种缓存控制的自适应时钟恢复的改进算法

文章介绍了TDMoIP(TDM over IP)技术中的一种基于去抖动缓存区自适应时钟恢复的改进算法,该算法将原算法的按固定周期长度调整接收端时钟频率改进为变长调整周期,通过改进算法和原算法的仿真对比,可以看出改进后的算法克服了原算法中的矛盾现象.最后对改进算法的性能进行分析,从理论上进一步验证了改进算法的优越性.     

A high-performance VLSI architecture for the histogram peak-climbing data clustering algorithm

Image feature separation is a crucial step for image segmentation in computer vision systems. One efficient and powerful approach is the unsupervised clustering of the resulting data set; however, it is a very computationally intensive task. This paper presents a high-performance architecture for unsupervised data clustering. This architecture is suitable for VLSI implementations. It exploits paradigms of massive connectivity like those inspired by neural networks, and parallelism and functionality integration that can be afforded by emerging nanometer semiconductor technologies. By utilizing a "global-quasi-systolic, local-hyper-connected" architectural approach, the hardware can process real-time DVD-quality video at the highest rate allowed by the MPEG-2 standard. The architecture is a realization of the histogram peak-climbing clustering algorithm, and it is the first special-purpose architecture that has been proposed for this important problem. The architecture has also been prototyped using a Xilinx field programmable gate array (FPGA) development environment. Although this paper discusses a computer vision application, the architecture presented can be utilized in the acceleration of the clustering process of any type of high-dimensionality data.     

Novel PLL-based clock distribution scheme

A technique for minimising clock skew in VLSI chips and multichip modules is proposed. A phase-locked loop is used to tune the delay of the clock interconnects. Negative, zero and positive delays can be achieved. This allows for clock synchronisation between individual modules with locally optimised clock distribution to minimise global clock-skew.<>     

自相似业务流下的星上交换全局优化缓冲分配算法

针对空间信息网络星上交换节点缓冲资源有限,提出一种适用于星上交换的缓冲优化分配算法。采用了Crossbar交换模型,在此基础上建立了虚通道自相似排队模型,通过计算每个虚通道缓冲溢出概率并采用遗传算法来实现缓冲资源全局优化分配。仿真结果表明,与均匀分配算法和贪婪分配算法相比,新算法具有更好的延时性能,在同等分组平均时延、业务流自相似程度为0.6和0.8的情况下,新算法比均匀分配算法可分别节省24.5%和26.4%的缓冲资源,并且分配效率比贪婪分配算法提高约21.9%。     

Adaptive hybrid clock discipline algorithm for the network timeprotocol

This paper describes the analysis, implementation, and performance of a new algorithm engineered to discipline a computer clock to a source of standard time, such as a GPS receiver or another computer synchronized to such a source. The algorithm is intended for the network time protocol (NTP), which is in widespread use to synchronize computer clocks in the global Internet, or with another functionally equivalent protocol such as DTSS or PCS. It controls the computer clock time and frequency using an adaptive-parameter hybrid phase/frequency lock feedback loop. Compared with the current NTP Version 3 algorithm, the new algorithm developed for NTP Version 4 provides improved accuracy and reduced network overhead, especially when per-packet or per-call charges are involved. The algorithm has been implemented in a special-purpose NTP simulator, which also includes the entire suite of NTP algorithms. The performance has been verified using this simulator and both synthetic data and real data from Internet time servers in Europe, Asia, and the Americas     

一种适用于地空通信的负载分布算法

针对地空通信系统传输时延较高、吞吐量较低的问题,提出了一种拥塞感知负载分布（Congestion-aware Load Distribution,CALD）算法。算法通过通信路径质量的变化,估计对应路径的拥塞窗口变化情况,自适应地调整每次子流分配大小,降低端到端的延迟,以应对地空通信的低带宽和高时延特性。同时基于搭建的多路径端到端服务器进行了实验,结果表明,所提算法在吞吐量性能和端到端延迟等方面都优于现有的子流分配算法。     

Performance aspects of reference clock distribution for evolvingdigital networks

Recent reference clock distribution technologies are reviewed. Performance concepts and specification methodologies for synchronization system designs are then summarized. The focus is on the common master-slave synchronization designs, generally consisting of three subsystems: the primary clock supply, the slave clock supply, and the clock distribution system overlaid on the digital network. Network synchronization performance is specified with relative clock frequency stability and accuracy of the corresponding reference clock. An overview is also given of clock and jitter and wander specification methodologies discussed in CCITT