DSP实时操作系统及其应用

由DSP处理器单独承担原来需要微控器和DSP处理器共同完成的任务的新一代DSP处理系统，已经开始成为嵌入式DSP系统开发领域主流。而且为了有效的发挥DSP处理器不断增加的性能，一个DSP已经开始用于同时并发的多个任务处理。在多任务或多个DSP处理器的系统中采用实时操作系统可以有效的降低开发难度，提高系统的可靠性和可升级性。本文对基于VDK的DSP实时操作系统内核进行了研究，详细描述了内核采用的多线程调度机制，并以一个多任务应用系统为例，实现了新线程的创建和取消，多线程之间的优先级排列和调度策略，给出了其API函数使用方法。     

实时操作系统DSP／BIOS的应用

介绍实时操作系统(RTOS)DSP／BIOS在DSP开发中的应用。首先简述DSP及其应用的一般模型，然后分别论述实时操作系统在DSP的外设管理、实时性能分析以及程序流程控制中的应用。同时总结了学习步骤。     

DSP应用正在吸引实时操作系统制造商

数字信号处理(DSP)技术的应用领域日益增多,正在为支持商用实时操作系统(RTOS)创造一个引人入胜的环境。DSP专用RTOS领域的先驱 Spectron Microsystems公司的SPOX操作系统不久将开始遇到竞争对手。两家竞争对手是 Eonic Systems 和Wind River Systems公司,它们提供的实时操作系统可在传统微控制器和DSP芯片这两个领域之间架起一座桥梁。但是,Spectron并不是无动于衷,最近宣布为Texas Instruments公司的DSP/BIOS提供开发者工具箱。     

实时操作系统DSP/BIOS在DSP开发中的应用

本文介绍了实时操作系统DSP/BIOS在DSP开发中的应用。首先简述了DSP应用的一般模型,并说明了实时操作系统在DSP外设管理,实时性能分析,程序总体流程控制中的应用。     

实时操作系统DSP/BIOS在DSP开发中的应用

本文介绍了RTOS(实时操作系统)DSP／BIOS在DSP的开发设计中的应用。在简述了DSP的一般模型后，论述了RTOS在DSP／BIOS外设管理，实时性能分析以及程序流程控制中的应用。     

实时操作系统可简化DSP应用程序的开发调试

数字信号处理(DSP)不断改进,结构往往越趋复杂,除了继续在传统的通信领域推广应用之外,在消费类电子产品和汽车电子产品领域的应用也日益广泛。不过,DSP的设计开发工具却未能跟上其应用普及的步伐。一些厂家开发的实时操作系统(RTOS)有助于解决这一问题。     

新一代物联网应用实时操作系统

正风河推出新一代VxWorks 7实时操作系统平台。VxWorks采用高度模块化的方式,实现了内核与文件系统和网络栈等组件的分离,因此可以随时对单个应用进行更新,无须对整个系统进行改造或者重新测试,从而提高了可伸缩性以及迅速适应市场变化的能力。RTOS由此进入真正的模块化、可升级平台时代,可广泛支     

DSP市场增长强劲 ZSP Foundry项目倍受青睐

L S I逻辑于近期宣布,中芯国际已加入Z S PFoundry项目,取得ZSP400和ZSP500的生产许可授权。中芯国际的加盟,对于广受欢迎的ZSP数字信号处理器技术在中国的生产支持,以及向fabless半导体公司和设计公司以高成本效益的、灵活的方式提供使用定制的ZSP硬核,有着重要意义。中芯国际市场及销售部门副总裁PaulOuyang表示:“通过加入ZSPFoundry项目,中芯国际将能够满足那些在无线、语音和多媒体产品的设计和生产中寻求更短的上市时间和更大灵活性的客户的需求。”目前可以提供给fabless公司的ZSP核包括:布局视图和完全描述特性的时序视…     

德州仪器的DSP在互联网音频市场倍受青睐

到2000年11月下旬,德州仪器公司(TI)共销售200万只互联美国网音频DSP,是成绩最好的一年。在拉斯维加斯举办的消费电器展览会上,TI     

DSP市场增长强劲ZSP Foundry项目倍受青睐

LSI逻辑于近期宣布，中芯国际已加入ZSP Foundry项目，取得ZSP400和ZSP500的生产许可授权。中芯国际的加盟，对于广受欢迎的ZSP数字信号处理器技术在中国的生产支持，以及向fabless半导体公司和设计公司以高成本效益的、灵活的方式提供使用定制的ZSP硬核，有着重要意义。     

采用Linux与DSP/BIOS RTOS实施双OS信号处理技术

在系统性能与编程简易性之间的权衡折中是通用操作系统与实时操作系统之间的主要区分点之一.     

VLIW DSP for mobile applications

We have developed a new digital signal processor (DSP) core for handheld terminals, the SPXK5 performance and flexibility, is compatible with high-level languages, and its architecture features low-power consumption. We describe the SPXK5 architecture and its performance in DSP applications. We also consider the question of application-specific enhancements. Such architecture enhancements as add-compare-select instructions or coprocessors for the Viterbi (1995) decoding algorithm are employed in some programmable DSPs, and for video codecs, other architectures include either single-instruction multiple-data (SIMD) instructions or media coprocessors. While such application-specific enhancements are valuable when their applications are actually in use, they do nothing to enhance the performance of other applications, and the more they are added, the greater the increase in chip size and energy requirements. In other words, for handheld terminals, such enhancements need to be chosen in a careful and balanced way. We have done this in developing the SPXK5, in which a wide range of signal processing algorithms are efficiently implemented     

Energy-efficient approximate adders for DSP applications

In this paper, approximate adders were proposed for DSP processors. DSP processors are mainly composed of adders and multipliers at bottom level. The power is minimized in transistor level design. Proposed adders have less power dissipation when compared to existing approximate adders. Results have shown that the proposed adders have less PDP with more accuracy. The circuits were simulated in Cadence virtuoso tool under 45 nm CMOS technology. Supply voltage is?+?0.5 V.

     

Efficient unfolding procedure for DSP applications

An FSFG can be used to obtain a rate-optimal schedule. There are some criteria to measure the optimality. Normally, an iteration period bound (IPB) is used for the optimal implementation. If an iteration period (IP) is the same as the IPB, the schedule is called rate-optimal. Unfolding can reduce the IP and guarantee rate-optimal schedules with an optimum unfolding factor. A new unfolding procedure, called JK's unfolding, is introduced which has low complexity and can be described using graphical methods     

Wave digital filters boost DSP applications

Wave digital filters (WDFs), digital filters that are derived by mathematical transformations from passive analog circuits, are discussed. Design and implementation techniques of WDFs are described, and it is shown that the most flexible WDF structure is that derived from the analog lattice network. The use of WDFs in traditional frequency-selective applications, transmultiplexing, interpolators and decimators (i.e. circuits that increase or decrease, respectively), the sampling rate, and image processing applications are also discussed     

Communication-sensitive loop scheduling for DSP applications

The performance of computation-intensive digital signal processing applications running on parallel systems is highly dependent on communication delays imposed by the parallel architecture. In order to obtain a more compact task/processor assignment, a scheduling algorithm considering the communication time between processors needs to be investigated. Such applications usually contain iterative or recursive segments that are modeled as communication sensitive data flow graphs (CS-DFGs), where nodes represent computational tasks and edges represent dependencies between them. Based on the theorems derived, this paper presents a novel efficient technique called cyclo-compaction scheduling, which is applied to a CS-DFG to obtain a better schedule. This new method takes into account the data transmission time, loop carried dependencies, and the target architecture. It implicitly uses the retiming technique (loop pipelining) and a task remapping procedure to allocate processors and to iteratively improve the parallelism while handling the underlying communication and resource constraints. Experimental results on different architectures demonstrate that this algorithm yields significant improvement over existing methods. For some applications, the final schedule length is less than one half of its initial length     

InSyn: integrated scheduling for DSP applications

We present the InSyn algorithm for high-level synthesis of DSP applications. InSyn combines allocation and scheduling of functional, storage, and interconnect units into a single phase and uses the following unique optimizations. (i) The concept of register states (free, busy, and undecided) is used for optimizing registers in a partial schedule where lifetimes of data values are not yet available. (ii) Reusable data values and broadcast are used to alleviate bus contention. (iii) InSyn can alternate between performance-guided and resource-guided measures. For example, InSyn can forgo its priority in favor of completing partially evaluated paths when the availability of allocated registers becomes low. (iv) InSyn ran selectively increase execution time of noncritical operations to alleviate bus contention. (V) InSyn can optimize and trade off distinct (functional units, interconnect, and registers) resource sets concurrently leading to more area-delay efficient designs. (vi) InSyn utilizes estimation tools towards resource allocation, design space pruning, and evaluation of synthesized designs. The experiments show that the features incorporated in inSyn result in very good designs     

Coprocessor for accelerated bit-true simulation of DSP applications

Bit-true simulation in DSP applications is very time consuming in comparison to functional-true simulation. This is caused by discrepancies in the finite word length features between the application and the simulating processor. The authors present a method for accelerating bit-true simulation based on coprocessor with dedicated instructions