Evaluation of electrolessly deposited NiP integral resistors on flexible polyimide substrate

Integral nickel–phosphorus (NiP) resistors were fabricated on flexible polyimide (PI) substrates by electroless NiP deposition. The deposition process was first set up for standard rigid epoxy substrates and then modified for the flexible substrates. The effects of the PI surface modifications on the interfacial adhesion (NiP/PI) were measured experimentally by the pull-off method. The process parameters were optimised to give good adhesion. The mechanical durability of the electrolessly deposited thin film NiP resistors was tested by measuring the electrical resistance during cyclic loading. The results showed the resistors to be mechanically stable. The electrical resistance was also monitored continuously during exposure to corrosive gas environment. The corrosive environment had no significant effect on the resistance of either the electrolessly deposited resistors or the commercial integral resistors used as a reference. The results show that resistors can be fabricated on flexible PI substrate by the described method.     

High value implanted resistors for microcircuits

Boron ion implantation has been used to fabricate high sheet resistance p-type junction resistors in silicon substrates. Thermally grown SiO2and conventional photolithography were employed to define the resistor geometries. Ion doses in the range 0.5 × 10¹³to 10 × 10¹³ions/cm²with energies ranging from 30 to 55 keV followed by anneal at 950°C were used. The temperature coefficient of resistance (TCR), voltage coefficient of resistance (VCR), junction Characteristics, and noise level of these resistors have been studied for sheet resistances ρx, from 0.8 to 11 kΩ/square. Over this range of sheet resistances the TCR increases smoothly from approximately 800 to 4000 PPM/°C with the lower TCR corresponding to the lower sheet resistance. For 3 kΩ square implanted resistors, the variation of resistance with temperature closely matches that found for a standard boron base and resistor (B&R) diffusion having a sheet resistance of 140 Ω/square. The junction leakage and the noise level of the implanted resistors can be made comparable to that obtained for diffused resistors. The implanted resistor exhibits a positive VCR, which increases with increasing sheet resistance as a result of depletion-layer pinch-off action from the substrate. Details of the implant conditions and process control are discussed. Experimental results demonstrating the compatibility of the resistor implantation process with microcircuits using low current, high β diffused bipolar transistors are presented.     

Quantitative Analysis of Resistance Variations in Nickel-Phosphorus (NiP) Resistors

Embedded resistors can be fabricated by plating resistive Nickel-Phosphorus (NiP) alloy to form resistors on circuit boards. As-deposited NiP alloy resistors typically have poor resistance tolerances and require tuning by costly laser trimming to meet specifications. The cost of the resistors can be reduced if the tolerances can be reduced without laser trimming. In this study, a group of parameters affecting patterning accuracies, plating and sheet resistivities were varied to evaluate their effects on the resistance tolerances of electroless-plated NiP resistors. The effect of the substrate on sheet resistivity variations was also characterized. Design guidelines to obtain NiP resistors with low tolerance without laser trimming arc discussed.     

Comparative study of the dissolution kinetics of electrolytic Ni and electroless Ni–P by the molten Sn3.5Ag0.5Cu solder alloy

Lead-free solders have high Sn content and high melting temperature, which often cause excessive interfacial reactions at the interface. Sn3.5Ag0.5Cu lead-free solder alloy has been used to identify its interfacial reactions with two-metal layer flexible substrates. In this paper we investigate the dissolution kinetics of Sn3.5Ag0.5Cu solder on electrolytic Ni/electroless NiP layer. It is found that during 1 min of reflow electroless NiP layer dissolves slightly lower than the electrolytic Ni due to the barrier layer formation between the intermetallic compounds (IMCs) and electroless NiP layer. Faster nucleation of IMCs on the electrolytic Ni layer is proposed as the main reason for higher initial dissolution. The appearance of P-rich Ni layer acts as a diffusion barrier layer between the solder and electroless NiP layer, which decreases the dissolution rate and IMCs growth rate than that of the electrolytic Ni layer, but weaken the interface and reduces the ball shear strength and reliability. After acquiring certain thickness P-rich Ni layer breaks and increases the diffusion rate of Sn and as a consequence both the IMCs growth rate and dissolution rate also increases. It is found that 3 μm thick electroless NiP layer cannot protect the Cu layer for more than 120 min at 250 °C. In electrolytic Ni shear strength does not change significantly and lower dissolution rate and more protective for Cu layer during long time molten reaction.     

Stability of miniaturized non-trimmed thick- and thin-film resistors

This paper is focused on reliability tests of non-trimmed miniaturized thin-film and thick-film resistors. Thick-film resistors are screen printed by polymer paste on LTCC (Low Temperature Co-fired Ceramic) substrate by two different approaches. Nonstandard precise screen printing process provide tolerance of resistivity less than 5% and thus further trimming is not necessary. OhmegaPly material with Nickel Phosphorous (NiP) metal alloy is used for thin-film resistors fabricated by subtractive process. Miniaturized resistors have dimensions 0.5 × 0.5 mm, and thus 1 square, with thickness 1 μm for thin-film and 20 μm for thick-film resistors. Stability of miniaturized resistors were tested by humidity test, thermal shocks, long-term thermal ageing, direct current stress, current pulses and simulation of soldering process using VPS (Vapour Phase Soldering). Resistivity of resistors is measured by four wire method before and after each set of test and relative change of resistivity is plotted in graphs. Influence of every test on each type of resistor is analysed.     

An approach to ensure stability of precision laser trimmed thick film resistors

In view of its complete automation, very high throughput, least in process variation, etc., laser trimming has been an industry standard in thick film technology. Random variations in print thickness, uncertainty of sheet resistivity in a paste lot and other process variations in a production line make it difficult to ensure a reasonably good yield for high precision resistors, where the tolerances under consideration are of the order of ±0.30%. Special attention has to be given to the resistor configuration type of laser cut and post trim processing. The studies were performed on samples drawn from a regular production line which contained two resistor—one with AR (L/W) > 1 where an L cut/Vernier cut combination was used for trimming and the other with AR < 1 where a P cut/Vernier cut combination was used. The post trim resistors' performance was studied under two conditions—one at room temperature and the other after baking at 150°C for 100hr and then maintained at room temperature. These studies lead to the conclusion that for high precision resistors the resistors should be so designed that the L cut/Vernier cut combination can be adopted for trimming. Secondly the trimmed resistor should be stored at 150°C for a period of 100 hr to make the post trim behaviour more predictable and also to achieve better yield.     

Microwave Dielectric Properties of ZnO-2TiO<Subscript>2</Subscript>-Nb<Subscript>2</Subscript>O<Subscript>5</Subscript> Ceramics with BaCu (B<Subscript>2</Subscript>O<Subscript>5</Subscript>) Addition

The influence of BaCu(B₂O₅) (BCB) addition on the sintering temperature and microwave dielectric properties of ZnO-2TiO₂-Nb₂O₅ (ZTN) ceramic has been investigated using dilatometry, x-ray diffraction, scanning electron microscopy, and microwave dielectric measurements. A small amount of BCB addition to ZTN can lower the sintering temperature from 1100°C to 900°C. The reduced sintering temperature was attributed to the formation of the BCB liquid phase. The ZTN ceramics containing 3.0 wt.% BCB sintered at 900°C for 2 h have good microwave dielectric properties of Q × f = 19,002 GHz (at 6.48 GHz), ε _r = 45.8 and τ _f  = 23.2 ppm/°C, which suggests that the ceramics can be applied in multilayer microwave devices, provided that Ag compatibility exists.     

埋入电镀电阻在高速线路中的应用

埋入电阻是实现高频电路的重要方法之一。现已开发出在内层要求精确电镀上电阻元件的工艺,这意味着PCB制造厂可采用各种类型层压板材料,根据不同电镀时间得到从25 Ω到100 Ω范围内的方块电阻值(电阻率),而不是采用各种不同电阻值金属箔的基材来制备不同阻值的埋入电阻。采用常规PWB的活化和化学镀等制造步骤便可制作这种电阻,这种埋入电阻工艺是易于激光检修并层压到多层板内部是很稳定的。这种埋入电阻经过多层层压,温度变化或者显露于潮湿环境下表明电阻值是很小改变的,经过模拟电路运作具有好的稳定性。     

Thermomechanical Reliability Study of Benzocyclobutene Film in Wafer-Level Chip-Size Package

A new wafer-level chip-scale package process for high-performance, low-cost packaging has been developed based on passivation with low dielectric constant. This process is simpler and shorter when using permanent photosensitive benzocyclobutene (BCB) compared with the conventional process. However, cracks nucleating on the BCB cause serious reliability problems. The major reasons for cracking of the BCB layer seem to be both thermal stress and a shortage of BCB cross-linking agent (cyclobutene). The stress was reduced by optimizing the thickness of the BCB layer and the underlying stress buffer layer. The BCB cracking resistance was improved by creating more cross-linking agent at the final curing process through modification of the photolithography processes.     

Polycrystalline silicon resistors for integrated circuits

The suitability of thin films of doped polycrystalline silicon on SiO₂ substrates for the production of high value resistors for monolithic integrated circuits is considered. Resistors fabricated from this material posses the advantages of high sheet resistivity and dielectric isolation while still preserving an all silicon technology compatible with conventional production techniques.Relevant structural and electrical properties of doped polycrystalline films produced by both vacuum evaporation onto hot substrates with gas-doping and by diffusion-annealing of amorphous films have been investigated. Sheet resistivities and TCR values measured on 2500 Å polycrystalline films have proved superior to those encountered with conventional diffused resistors. Typically films with sheet resistivities of 1 kΩ/□ had TCR's of ?1000 ppm/°C while conventional diffused resistors are generally made from material of 200 Ω/□ and +2000 ppm/°C TCR. Etched resistor line widths of 0·25 mil. have been obtained in the polycrystalline material employing conventional photolithographic techniques. The temperature stability and linearity of doped polycrystalline resistors have been investigated.     

Boron-implanted silicon resistors

The sheet resistance of silicon resistors implanted with boron at room temperature has been experimentally determined for doses from 5 × 10¹² to 2 × 10¹⁶ cm^?2. The results have been compared with the V calculated values. Two methods for minimizing the temperature coefficient, TCR, are described, and their merits and disadvantages are discussed. For a 1-kΩ/□ resistor, TCR can be reduced to 1000 ppm/°C by implanting ¹¹B⁺ at low energy, 5–10 keV, and to less than 100 ppm/°C by implanting a suitable dose of Ar⁺ damage. In a two-terminal resistor, the end effect of the total sheet resistance on TCR and on voltage coefficient VCR was also investigated.     

A compatible technique for the formation of thin tantalum film resistors on silicon integrated circuits

A problem in the production of silicon integrated circuits has been yield limitation and applicability restriction due to the large variation and temperature sensitivity of diffused silicon resistors. Use of a thin-film resistive complement on silicon integrated circuits improves performance of many microcircuits heretofore made by the silicon planar process alone. The technique for thin-film on silicon integrated circuits is based on a two-metal resistor-conductor system: tantalum and aluminum. Tantalum was selected as the resistive material because it can be cathodically sputtered with ease, and a wide range of specific resistivity is available as a result of the controlled energy sputtering technique. The process involves production of the active element part of the circuit with standard silicon integrated circuit planar techniques, including contacting the cuts with deposited aluminum. The only deviation from the standard process lies in leaving some unetched SiO2surface area for resistor deposition. Tantalum is cathodically sputtered over the wafer, and delineated by standard photolithographic techniques to form resistor, conductor, and pad areas. A second layer of aluminum is then vacuum deposited over the wafer, and this is delineated to cover the pad and conductor areas of the tantalum with a high conductivity overlay. The exposed tantalum is then thermally stabilized and the final sheet resistivity adjusted by the resulting controlled sheet resistivity increase. The resulting circuits contain stable resistors with tolerance distributions of ±5 percent to ±10 percent, and TCR of -200 to -300 PPM/°C. The silicon active elements in the circuits do not degrade as a result of the thin-film resistor formation.     

Buried-guarded layer ion-implanted resistors

Megohm silicon monolithic resistors have been fabricated with sheet resistances up to 120 kΩ/□ using an implanted p-layer resistor which is buried under an implanted n-guard layer. The n-guard layer protects against slice-to-slice variations of the fixed surface charge, and was made using phosphorus doses and energy of 1.5-5 × 10¹²/cm²and 30 keV. Resistors have been fabricated up to 20 MΩ; sheet resistances were in the range of 7-120 kΩ/□ using boron doses and energies of 1-3 × 10^:12/cm²and 30-300 keV. The sheet resistance, voltage dependence of resistance, temperature coefficients, junction leakage, and parasitic capacitance have been measured for different implantation parameters. This process has been used to fabricate two matched 8-MΩ resistors for use in a high input impedance differential preamplifier integrated circuit. A match of 2 percent and a magnitude tolerance of ±10 percent has been achieved. The temperature coefficient of resistance (TCR) is about 4000 ppm/°C and tracks within 400 ppm/ °C. These resistors are linear up to ∼1 V, about 50 times higher bias voltage than required in the application. The structure and fabrication are compatible with present monolithic silicon integrated circuit processing.     

Band gap engineered resistor for mitigating linear energy transfer sensitivities in scaled submiron CMOS technology SRAM cells

Use of cross-coupling latch resistors is a prime method of mitigating single event upsets (SEU). Scaling has dramatically reduced ability of using this technique because of the large area needed as well as high temperature coefficient of resistance (TCR) of lightly doped polysilicon resistors. We present results of a study of the electrical properties of Al_1?xIn_xN films resistor which offers distinct advantage over polysilicon resistors. The films were grown on silicon nitride by magnetron sputter deposition at room temperature. Sheet resistance in the range of 8–10 kΩ/□ was reproducibly grown. The resistor film is thermally stable with TCR of less than minus 0.09%/°C for temperature range of minus 55 °C to +125 °C.     

Environmental Qualification Testing and Failure Analysis of Embedded Resistors

Embedding passive components (capacitors, resistors, and inductors) within printed wiring boards (PWBs) is one of a series of technology advances enabling performance increases, size and weight reductions, and potentially economic advantages in electronic systems. This paper explores the reliability testing and subsequent failure analysis for laser-trimmed Gould subtractive nickel chromium and MacDermid additive nickel phosphorous embedded resistor technologies within a PWB. Laser-trimmed resistors that have been “reworked” using an inkjet printing process to add material to their surface to reduce resistance have also been considered. Environmental qualification testing performed included: thermal characterization, stabilization bake, temperature cycling, thermal shock and temperature/humidity aging. In addition, a pre/post-lamination analysis was performed to determine the effects of the board manufacturing process on the embedded resistors. A failure analysis consisting of optical inspection, scanning acoustic microscope (SAM) and environmental scanning electron microscope (ESEM) imaging, and PWB cross-sectioning was employed to determine failure mechanisms. All the embedded resistors were trimmed and the test samples included resistors fabricated both parallel and perpendicular to the weave of the board dielectric material. Material stability assessment and a comparison with discrete resistor technologies was performed.     

Characterization of interface defects in oxygen-implanted silicon films

Defects in ungated n- or p-type and gated p-type resistors have been characterized by photoinduced transient spectroscopy (PITS). These resistors were fabricated with p-type separation by implanted oxygen (SIMOX) wafers with a single-energy 200-keV oxygen implant to a total fluence of 1.8 × 10¹⁸ cm⁻². One wafer, used for gated resistor fabrication was implanted at 595°C and sequentially annealed at 1325°C for 4 h in argon (plus 0.5% oxygen) followed by 4 h in nitrogen (plus 0.5% oxygen). Another wafer, used for ungated resistor fabrication, was implanted at 650°C and annealed at 1275°C for 2 h in nitrogen (plus 0.5% oxygen). The photoconductive response of these resistors to a 1-μs long visible light pulse, measured at temperatures in the 80-to 170-K range, shows different persistent photoconductive effects due to trapped minority carriers that are somewhat linked to the thermal anneal given to the SIMOX wafers. Our results indicate that more damage is present in the wafer annealed at 1275°C than in the one annealed at 1325°C. We model the photoconductive response in terms of a perpendicular built-in field created in the conductive film by trapped charge located at or near the interface with the buried oxide. Defects distributed throughout the conductive film body or located at the interface with the gate oxide are not expected to contribute significantly to the PITS signature, because of the fabrication of the gate oxide with standard metal-oxide semiconductor technology. We estimate the average trap density at the back interface to be in the 10¹¹ cm² range.     

Redistribution and bumping of a high I/O device for flip chipassembly

Redistribution and bumping of a high I/O device has been successfully achieved at Motorola's Interconnect Prototype Lab using a combination of photosensitive benzocyclobutene (BCB), electroless nickel underbump metallurgy, and photoresist defined solder printing technique. To take full advantage of flip chip packaging technology, redistribution is necessary to rewire bondpads to an area array. BCB was chosen as the interlayer dielectric between the redistributed metal traces and device circuitry. Advantages of BCB include high level of planarization, low moisture uptake, rapid thermal curing, high thermal stability, high solvent resistance, and a low dielectric constant. We successfully optimized many steps in the process flow to redistribute the bondpads. The BCB residue in vias was cleaned with a plasma descum comprised of an Ar/SF₆ mixture. BCB to BCB adhesion was improved by optimizing the curing time. The shear strength of the bumps was increased 80% by sputter-roughening of the BCB/Al interface. Sematech ATC04-2 functional wafers with 1004 bumps/die and a minimum pitch of 8 mils were successfully redistributed to a 10 mil and 16 mil mixed array pitch and solder bumped using a photodefined squeegee bump technology     

Quantitative Analysis of Resistance Tolerance of Polymer Thick Film Printed Resistors

Low cost methodologies of resistor fabrications are needed for cost effective embedding of resistors into polymeric substrates. Polymer thick film resistors (PTFRs) are low temperature processable, low cost resistors with a wide resistivity range. The electrical resistance variation of these resistors is in the range of around plusmn20% after deposition and trimming procedure is employed to tune the resistances to meet specifications. This adds to the cost and complicates the fabrication process when the resistors are embedded. In this study, the influences of PTFRs geometries on the resistance tolerances were investigated. Results indicated that the resistance accuracy of stencil printed resistors was markedly higher than that of the screen-printed resistors. The screen-printed resistor edge geometries were observed to be rough. Finite element method analyses revealed that the resistance tolerances were associated with edge roughness. Remedies to reduced variations were proposed and the relationship between resistance tolerances and aperture orientations was also outlined     

Environmentally sustainable composite resistors with low temperature coefficient of resistance

Temperature coefficient of resistance (TCR) of thick film resistors are based on fired conducting grains and glass composites. Many analog sensor and control circuits require low (<100 ppm/°C) TCR value. To prepare resistors with low TCR value, knowledge of processing conditions and conduction mechanism parameters are of particular importance because TCR is finalised during firing and cannot be trimmed in the latter stage to a target value as resistors can be. This paper reports the preparation and properties such as microstructural and electrical in particular to sheet resistance, TCR (hot and cold) of eco-friendly composite resistor paste compositions. Our resistor compositions showed the sheet resistance in the range of 1.18–1.38 KΩ/□ and the hot and cold TCR of the compositions reduced substantially from 360 to 100 ppm/°C and 175 to 60 ppm/°C with the addition of TCR modifier.     

Temperature sensitivity in silicon piezoresistive pressure transducers

The various mechanisms responsible for temperature sensitivity in silicon piezoresistive pressure sensors are described. As a representative transducer, a full-bridge device having a 1-mm-square 23-µm-thick diaphragm is used. The 200 Ω/square, 2K-Ω bridge resistors produce a pressure sensitivity of 13.3 µV/V.mmHg with a temperature coefficient of -1300 ppm/°C. Variability in this sensitivity is most strongly influenced by the diaphragm thickness and the absolute resistor tolerance. A new technique-the electrochemical EDP etch-stop-is found to offer significant advantages over alternative schemes for diaphragm formation. Temperature sensitivity in electrostatically-bonded, vacuum-sealed devices is dominated by resistor match, with oxide stress and junction leakage current playing relatively minor roles over the -40 to + 180°C temperature range. While individual pressure trims for offset and sensitivity will continue to be required, individual temperature trims may be eliminated in these devices for many applications as increasingly precise resistor processes are used.