A review of latchup and electrostatic discharge (ESD) in BiCMOS RF silicon germanium technologies: Part I—ESD

Electrostatic discharge (ESD) continues to be a semiconductor quality and reliability area of interest as semiconductor components are reduced to smaller dimensions. The combination of scaling, design integration, circuit performance objectives, new applications, and the evolving system environments, ESD robustness will continue to be a technology concern. With the transition from silicon bipolar junction transistor to modern BiCMOS silicon germanium (SiGe) semiconductor technologies, new semiconductor process and integration issues have evolved which influence both device performance and ESD protection. Additionally, the issues of low cost, low power and radio frequency (RF) GHz performance objectives has lead to both revolutionary as well as derivative technologies; these have opened new doors for discovery, development and research in the area of on-chip ESD protection and design. With the growth of interest of ESD in RF technology, new innovations and inventions are occurring at a rapid pace. In this paper, we will provide an introductory review of silicon germanium technology and ESD.     

Status and trends of silicon RF technology

The current research and development activities in silicon radio-frequency (RF) technologies are first reviewed, accompanied by an illustration of the most pronounced shortcomings of conventional silicon technology in the integrability of RF functions at high GHz frequencies. In the discussion on active RF devices mainly CMOS is investigated due to great interest in this mass-production technology. Issues related to the integration of spiral inductors on silicon are addressed, stressing in particular the difficulty of RF substrate potential definition. Silicon micromachining techniques are highlighted as potential solutions to the integration of RF passives and to reduce substrate losses and cross-talk on silicon. It is explained that micromachining techniques are the best introduced to the silicon mainstream by using post-processing and minimum process complexity.     

Substrate transfer for RF technologies

The constant pressure on performance improvement in RF processes is aimed at higher frequencies, less power consumption, and a higher integration level of high quality passives with digital active devices. Although excellent for the fabrication of active devices, it is the silicon substrate as a carrier that is blocking breakthroughs. Since all devices on a silicon wafer have a capacitive coupling to the resistive substrate, this results in a dissipation of RF energy, poor quality passives, cross-talk, and injection of thermal noise. We have developed a low-cost wafer-scale post-processing technology for transferring circuits, fabricated with standard IC processing, to an alternative substrate, e.g., glass. This technique comprises the gluing of a fully processed wafer, top down, to an alternative carrier followed by either partial or complete removal of the original silicon substrate. This effectively removes the drawbacks of silicon as a circuit carrier and enables the integration of high-quality passive components and eliminates cross-talk between circuit parts. A considerable development effort has brought this technology to a production-ready level of maturity. Batch-to-batch production equipment is now available and the technology and know-how are being licensed. In this paper, we present four examples to demonstrate the versatility of substrate transfer for RF applications.     

Design of RF integrated circuits using SiGe bipolar technology

We report on design aspects and the implementation of radio-frequency integrated circuits using TEMIC's SiGe technology. The differences between the device parameters of silicon bipolar junction transistor and silicon germanium heterojunction bipolar transistor technology and their influence on IC design are discussed. Design and measurement results of RFICs, including low noise amplifier, power amplifier, and single-pole, double-throw antenna switch for application in a 1.9 GHz digital enhanced cordless telecommunications RF front end are presented     

Computer-aided design of analog and mixed-signal integratedcircuits

This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs). Analog blocks typically constitute only a small fraction of the components on mixed-signal ICs and emerging systems-on-a-chip (SoC) designs. But due to the increasing levels of integration available in silicon technology and the growing requirement for digital systems to communicate with the continuous-valued external world, there is a growing need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits. This paper describes the motivation and evolution of these tools and outlines progress on the various design problems involved: simulation and modeling, symbolic analysis, synthesis and optimization, layout generation, yield analysis and design centering, and test. This paper summarizes the problems for which viable solutions are emerging and those which are still unsolved     

A thin-film bulk-acoustic-wave resonator-controlled oscillator on silicon

A composite ZnO bulk-acoustic-wave thin-film resonator (TFR) has been fabricated on a silicon substrate with a double-diffused BJT. Fabrication techniques unique to the integration of the TFR are discussed. The integrated TFR-BJT structure was configured as a VHF Pierce oscillator circuit with a fundamental frequency of 257 MHz. Phase noise is better than -90 dBc/Hz at a 1-kHz offset. Temperature stability is - 8.5 ppm/°C from 5°C to 65°C and - 3.75 ppm/°C from 55°C to 5°C. The integration of the TFR with active components is viewed as a development toward large-scale RF circuit integration.     

3-D Integration of 10-GHz Filter and CMOS Receiver Front-End

A 10-GHz filter/receiver module is implemented in a novel 3-D integration technique suitable for RF and microwave circuits. The receiver designed and fabricated in a commercial 0.18-mum CMOS process is integrated with embedded passive components fabricated on a high-resistivity Si substrate using a recently developed self-aligned wafer-level integration technology. Integration with the filter is achieved through bonding a high-Q evanescent-mode cavity filter onto the silicon wafer using screen printable conductive epoxy. With adjustment of the input matching of the receiver integrated circuit by the embedded passives fabricated on the Si substrate, the return loss, conversion gain, and noise figure of the front-end receiver are improved. At RF frequency of 10.3 GHz and with an IF frequency of 50 MHz, the integrated front-end system achieves a conversion gain of 19 dB, and an overall noise figure of 10 dB. A fully integrated filter/receiver on an Si substrate that operates at microwave frequencies is demonstrated.     

Near Quantum Limited Nb-Al-AlO x -Nb Mixers on 9 μm Thick Silicon Substrates around 350 GHz

We present design, performance measurements and simulations of Nb-Al-AlO _x -Nb superconductor-insulator-superconductor (SIS) mixers on silicon membranes mounted into waveguide mixerblocks with beam leads. The mixers are designed for use in astronomy for radio frequencies (RF) between 290 and 390 GHz and a 4-12 GHz intermediate frequency (IF) output band. Different mixer designs are discussed. Each design includes a pair of SIS junctions, connected in series or in parallel. Measurements confirm that silicon membrane substrates with beam lead contact technology support excellent cooling of the devices and show noise temperatures that can be limited to values between once and twice the quantum limit in the RF bandwidth. Measurement results are compared to simulations based on the Quantum Theory of Mixing (QTM). For the parallel junctions we use an adaption of the QTM to calculate the single-junction DC IV-characteristics separately. The resulting simulated DC IV-characteristics are in excellent agreement compared to 3D electromagnetic (EM) simulations and measurements.     

一种低噪声高线性度射频前端电路设计

介绍了超高频接收系统射频前端电路的芯片设计。从噪声匹配、线性度、阻抗匹配以及增益等方面详细讨论了集成低噪声放大器和下变频混频器的设计。电路采用硅基0.8μm B iCM O S工艺实现,经过测试,射频前端的增益约为18 dB,双边带噪声系数2.5 dB,IIP 3为+5 dBm,5 V工作电压下的消耗电流仅为3.4 mA。     

High-performance interconnects: an integration overview

The Information Revolution and enabling era of silicon ultralarge-scale integration (ULSI) have spawned an ever-increasing level of functional integration on-chip, driving a need for greater circuit density and higher performance. While traditional transistor scaling has thus far met this challenge, interconnect scaling has become the performance-limiting factor for new designs. The increasing influence of interconnect parasitics on crosstalk noise and R(L)C delay as well as electromigration and power dissipation concerns have stimulated the introduction of low-resistivity copper and low-permittivity (k) dielectrics to provide performance and reliability enhancement. Integration of these new materials into integrated circuit fabrication is a formidable task, requiring material, process, design, and packaging innovations. Additionally, entirely new technologies such as RF and optical interconnects may be required to address future global routing needs and sustain performance improvement     

数据传输系统的FPGA一体化设计与实现

当前的差分相移键控（DPSK）数据传输系统大多是采用独立的数据调制解调终端设备和收发信设备组成的,集成度低、可靠性较差,存在内部信号量化噪声。通过应用现场可编程门阵列（FPGA）加高速数字信号处理设计技术,将数据传输系统中的信号进行DPSK调制,基带到射频信号的数字上变频,以及信号的解调与射频到基带信号数字下变频进行一体化设计,解决了DPSK调制解调终端设备与射频信道设备相互独立所带来的集成度低、可靠性差,以及设备间信号变换引起信号受损等问题。     

Integrated LC oscillators for frequency synthesis in wirelessapplications

This article reviews the achievements in the full integration of low-noise silicon LC oscillators for wireless communications. Trade-offs in the design of the LC tank are discussed, and dominant contributions to phase noise are illustrated. State-of-the-art performance of fully integrated CMOS and bipolar oscillators is reported     

Temperature and Substrate Effects in Monolithic RF Inductors on Silicon With 6-$muhboxm$-Thick Top Metal for RFIC Applications

Comprehensive analyses of the effects of temperature (from$-hbox50 ^circhboxC$to 200$^circhboxC$), silicon substrate thickness, and proton implantation postprocess on the performances of a set of planar spiral inductors with 6-$muhboxm$-thick top metal are demonstrated. Quality-factor (Q-factor) and power gain$( G_ A)$decrease with increasing temperatures but show a reverse behavior within a higher frequency range. Stability-factor (K-factor) and noise figure (NF) increase with increasing temperatures but show a reverse behavior within a higher frequency range. The reverse frequencies$f_R$, which correspond to the zero temperature coefficient of$G_A$, K-factor, and NF, are almost the same. In addition, both the silicon substrate thinning and proton implantation are verified to be effective in improving the Q-factor and NF performances of inductors on silicon. The present analyses enable RF engineers to understand more deeply the Q-factor and NF behavior of inductors fabricated on a thin silicon substrate (20$muhboxm$) and hence are helpful for them to design high-performance fully on-chip low-noise-amplifiers and other RF integrated circuits.     

Self-Calibration of Output Match and Reverse Isolation in LNAs Based Switchable Resistor

With recent advances in CMOS process technology, the concept of system-on-a-chip (SoC) has been realized by integrating more and more digital and analog building blocks in a single chip [2, 9]. Additionally, these advances have brought several new types of processes faults (soft fault) and higher process variations to RF circuit resulting performances degradation. In order to compensate the RF circuit performance, a novel efficient self-calibration method for 865?C870?MHz low noise amplifiers (LNAs), which constitute a RF mixed-signal circuit, is developed. This technique detects any deviation from the output match and from reverse isolation using built-in self test (BIST) methods, and then provides a corrective measure to recalibrate these LNA performances to the possible optimal value. This proposed self-calibration technique uses a switchable resistor which has been designed to investigate its ability to compensate for output match S22 and reverse isolation S12 without affecting other LNA performances. The use of this method saves space on chip and prevents adding switch resistor noise. In addition, the new calibration design shows the ability to calibrate S22 and S12 due to the catastrophic fault.     

IP模块设计:实例研究

设计能力和硅芯片所能提供的集成能力增长差距的扩大阻碍了片上系统的有效开发 ,为此必须提高设计人员的设计能力 ,降低产品开发周期和成本。设计的重用是提高设计能力的有效方法。文中通过实际 IP模块的设计 ,分析研究了如何开发高质量的可重用 IP模块。     

Dielectric Resonator Antenna on Silicon Substrate for System On-Chip Applications

This paper presents for the first time the design and performance of a novel integrated dielectric resonator antenna fabricated on a high conducting silicon substrate for system on-chip applications. A differential launcher to excite the ${rm TE}_{01delta}$ mode of the high permittivity cylindrical dielectric resonator was fabricated using the IBM SiGeHP5 process. The proposed antenna integrated on a silicon substrate of conductivity 7.41 S/m has an impedance bandwidth of 2725 MHz at 27.78 GHz, while the achieved gain and radiation efficiency are 1 dBi and 45% respectively. The design parameters were optimized employing Ansoft HFSS simulation software. Very good agreement has been observed between simulation and experimental results. The results demonstrate that integration of dielectric resonator antennas on silicon is viable, leading to the fabrication of high efficient RF circuits, ultra miniaturization of ICs and for the possible integration of active devices.      

Investigation of Low-Frequency Noise in Silicon Nanowire MOSFETs

Low-frequency noise (LFN) in n-type silicon nanowire MOSFETs (SNWTs) is investigated in this letter. The drain–current spectral density exhibits significant dispersion of up to five orders of magnitude due to the ultrasmall dimensions of SNWTs. The measured results show that LFN in SNWTs can be well described by the correlated-mobility fluctuation model at low drain current, with the effective oxide trap density extracted and discussed. At high drain current, however, the input-referred noise spectral density increases rapidly with the drain current, which indicates the significant impact of the ultranarrow source/drain extension regions of SNWTs. As a result, design optimizations to reduce the impact of parasitic resistance in SNWTs are necessary for analog/RF applications.      

Joint compensation of IQ imbalance and phase noise in OFDM wireless systems

Physical impairments like IQ imbalance and phase noise can cause significant degradation in the performance of wireless communication systems. In this paper, the joint effects of IQ imbalance and phase noise on OFDM systems are analyzed, and a compensation scheme is proposed to improve the system performance in the presence of IQ imbalance and phase noise. The scheme consists of a joint estimation of channel and impairment parameters and a joint data symbol estimation algorithm. It is shown both by theory and computer simulations that the proposed scheme can effectively improve the signal-to-noise ratio at the receiver. As a result, the sensitivity of OFDM receivers to the physical impairments can be significantly lowered, simplifying the RF and analog circuitry design in terms of implementation cost, power consumption, and silicon fabrication yield.     

Wireless telecom silicon integration: analog design for radio,baseband and speech spectrum

The application today, pushing analog design for CMOS and RFbipolar into new frontiers is definitely the mobile radio telephony. New telecom systems like GSM, PCN, DECT, DCS, Wireless in the loop ... are all developing very rapidly and will enable us very soon to organise a complete telephone network with full coverage for your car, as well as in your kitchen and on your office desk. In Europe the major telecom companies have worked together to establish one common standard for cellular mobile radio communications at 900 MHz. Similar things are happening for other wireless personal communication systems. Basically the cellular radio telephone, the wireless PABX and the wireless SLIC are bringing the same challenges to analog circuit design: maximum integration of the basic radio functions into 1 or 2 silicon chips, CMOS, Bipolar or BiCMOS or GaAs. The analog circuit designer for radio telephone applications will need all the state of the art analog design knowhow available today, from RFmixers and GHz range low noise amplifiers and local oscillator synthesizers over base band 100 kHz CMOS analog to low frequency speech analog to digital conversion. And for all these circuits the message is: minimum power consumption for battery autonomy, minimum silicon area for maximum functional integration per die to obtain a small, low cost pocket size radio telephone.     

An Improved Solid-State Noise Source (Short Papers)

An improved solid-state noise source is discussed. By implementing such modifications as 1) heat sinking of a silicon avalanche noise diode, 2) proper dc RF decoupling, and 3) impedance matching, the stability of the National Bureau of Standards (NBS) solid-state noise source is improved significantly over that of typical commercial solid-state noise sources. These modifications, how they are implemented, and the resulting improvement in stability are described.