新品展台

业野首款+5 V低功耗一次性可编程“固定调节值” 的数字电位器 美国模拟器件公司推出业界最低功耗、最小封装、64分点数字电位器AD5273。这种一次性可编程(OTM)数字控制的可变电阻器(VR)具有与可变电阻器或电位器一样的电子调节功能,而且封装更小、性能更可靠。AD5273可以取代出厂时需要“固定调节值”的机械式电位器,而且节省时间和劳动力。一次性可编程能永久性固定电位器滑动点的位置,类似于在机械式电     

数模转换器AD5601

AD5601是美国模拟器件公司(ADI)的一款低功耗、小尺寸、易控制的8 位数模转换器,其通用三线串口可灵活地与SPI、QSPI、MICROWIRE、DSP 等接口标准兼容,主要用于消费类电子产品和手持设备、数字增益和偏移量调整、可编程电压源(可编程电流源)和可编程衰减器等场合,例如数码相机、PDA、蜂窝电话音量控制或背光显示屏亮度控制等方面。文中介绍了AD5601 的性能特点、内部结构、引脚排列和设计考虑,并给出了其和数字信号处理器ADSP2101 的接口应用电路。     

LA5621M／LA5621V锂离子电池充电控制IC

LA5621M/LA5621V是日本SANYO半导体公司生产的锂离子电池充电控制IC,能够结合充电电路和微控制器,对视频摄影机、数字静物照相机和蜂窝电话等用单节或两节锂离子电池进行充电。1.封装及引脚 LA5621M和LA5621V分别采用14脚MFP和16脚SSOP封装,引脚排列如图1所示。 LA5621M/LA5621V的引脚功用简述如表1。     

ADI公司推出新型多通道数模转换器

ADI（美国模拟器件公司）发布了业界最小、最灵活的DAC（多通道数模转换器）——AD57xx系列。该DAC能够满足特定DAC在高电压应用中设计工程师对其灵活性的需求，例如，工厂过程控制、仪表仪器和直流设定点控制应用等。该系列包括12款采用单电源或双电源宽电压范围、12～16bit双通道和四通道DAC。此外。还具有可灵活配置的软件和可编程功能，即DAC每通道可独立设置单极性和双极性电压输出范围，从而允许设计工程师无需选择大量的精密元件（如精密电阻器、开关和外部放大器）即可实现。该DAC采用小型引脚兼容薄小外形封装（TSSOP），比相近器件减小40％以上。由于无需采用分立元件和小封装尺寸特性，所以该DAC比现有分立解决方案节省70％的印制电路板面积。     

耗电流低于200μA的低功耗4mA至20mA过程控制电流环路解决方案

4 mA至20 mA电流环路广泛用于采用数字或模拟输入输出的可编程逻辑控制器(PLC)和分布式控制系统(DCS)。电路功能与优势图1所示电路是一个4 mA至20 mA电流环路发送器,用于过程控制系统与其执行器之间的通信。除具有高性价比外,此电路还是业界功耗最低的解决方案。电流环路接口之所以颇受青睐,是因为它能以高性价比方式进行长距离抗扰数据传输。低功耗双通道运算放大器AD8657、DACAD5621和基准电压源ADR125     

ADI新款AD8677尺寸为同类器件的1/4

美国模拟器件发布一款新的运算放大器AD8677,它的尺寸为同类器件的1/4,而其性能与诸如ADI公司的工业标准OP07这样的高性能、超低失调电压运算放大器相比具有更高的精度。为了满足诸如工业可编程逻辑控制器(PLC)、自动测量设备(ATE)平台和机械监测系统的应用需求,采用ADI公司新的iPOLAR沟道隔离制造工艺[链接到新闻稿]生产的AD8677将功耗减小40%,同时保持了75ΜV(最大值)的失调电压和1.3ΜV/℃(最大值)温度漂移。这款性能卓越的器件采用超小型3mm×3mmTSOT-23封装。AD8677具有的高精度、小尺寸和低功耗特性使其适合精密温度和电…     

可编程自稳零放大器简化了工业应用中的传感器校准

最新推出的AD8555是一款高集成度数字可编程精密放大器，用来提供一种从传感器输出到ADC的完整信号调理解决方案。利用ADI公司的低噪声自稳零和DigiTrim^TM专利技术，AD8555能够在一个很小的封装内提供一种精确和可靠的信号调理解决方案。     

产品

通用ICADI高精度和带宽仪表放大器美国模拟器件公司(ADI)发布了两款具有高精度和带宽的数字可编程增益仪表放大器。AD8250和AD8251可实现12MHz带宽。采用亚微型iCMOS(工业CMOS)工艺,这两款仪表放大器的拉电流只有3.5mA,比同类器件减小75%。10引脚超小外形塑料封装(MSOP)比同类最接近的仪表放大器减小90%。这些产品适合于要求大电压工作范围的工业和仪表仪器设备,它们采用±5V￣±12V电源供电,可提供0.5μs的建立时间,以及1μV/℃的失调电压和10ppm/℃增益漂移。AD8250和AD8251的千片批量报价为4.95美元。www.analog.com/pr/A…     

接收信号处理芯片AD6634及其在软件无线电中的应用

AD6634是Analog Devices公司的四通道宽带可编程数字接收信号处理芯片。文中介绍了AD6634的内部结构和基本功能特点，给出了基于AD6634的通用可编程中频软件无线接收系统的结构，同时给出了系统中AD转换、FIFO和DSP等器件的的选择方向，最后讨论了AD6634主要参数的设置方法。     

各国主要厂商集成电路型号命名意义(三)

‘士。里压3 Ingtrumontg,Ine. 德克萨斯铃件公司气美)A姚高级双极电路)SBP(双极微处理器)SMJ(Moe存贮器和徽处理器)SN(标准电路)已NJ(标准电路888B)TAO(CMOS逻辑阵列)TAL(小功率肖特基TTL逻辑 阵列)TAT(STL逻辑阵列)TL(线性电路)TLC(线性CM‘男电路)TIEP(阻抗变换放大器)T工日8(红外源电路)T工PPLA(双极场可编程逻辑阵)T工BPLA(双极可编程逻辑阵)TL 0728 E JG/883B词头编号温度范围封装屏蔽等级 SN 74 5188) 词头温度范围编号封装词头第一字母意义:T(模拟电路) U(数/模电路)词头第二字母愈义:无特殊意义词头第…     

A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package

A wireless interface by inductive coupling achieves aggregated data rate of 195 Gb/s with power dissipation of 1.2W among 4-stacked chips in a package where 195 transceivers with the data rate of 1 Gb/s/channel are arranged in 50-/spl mu/m pitch in 0.25-/spl mu/m CMOS technology. By thinning chip thickness to 10/spl mu/m, the interface communicates at distance of 15 /spl mu/m at minimum and 43 /spl mu/m at maximum. A low-power single-end transmitter achieves 55% power reduction for multiple connections. The transmit power is dynamically controlled in accordance with communication distance to reduce not only power dissipation but also crosstalk.     

Low-power realization of FIR filters on programmable DSPs

This paper addresses the problem of reducing power dissipation of finite impulse response (FIR) filters implemented on programmable digital signal processors (DSPs). We describe a generic DSP architecture and identify the main sources of power dissipation during FIR filtering. We present seven transformations to reduce power dissipated in one or more of these sources. These transformations complement each other and together operate at algorithmic, architectural, logic and layout levels of design abstraction. Each of the transformations is discussed in detail and the results are presented to highlight its effectiveness. We show that the power dissipation can be reduced by more than 40% using these transforms. The transformations have been encapsulated in a framework that provides a comprehensive solution to low-power realization of FIR filters on programmable DSP's     

A programmable thermal management interface circuit for PowerPC systems

A programmable thermal management interface circuit for PowerPC systems has been designed, implemented, and tested for the Integrated Thermal Management (ITEM) System [1]. Instead of worst-case design, the ITEM system approach is to target nominal power dissipation and have the system actively monitor its thermal activity and control cooling mechanisms to ensure operation within specification. Using a suitable combination of hardware and software, the interface design yields intricate control and optimal management with little system overhead and minimum hardware requirements, as well as provides the flexibility to support different management algorithms. This interface circuit was fabricated in the HP 0.5 μm single-poly 3-metal process through MOSIS.     

倒装焊器件封装结构设计

倒装焊是今后高集成度半导体的主要发展方向之一。倒装焊器件封装结构主要由外壳、芯片、引脚(焊球、焊柱、针)、盖板(气密性封装)或散热片(非气密性封装)等组成。文章分别介绍外壳材料、倒装焊区、频率、气密性、功率等方面对倒装焊封装结构的影响。低温共烧陶瓷(LTCC)适合于高频、大面积的倒装焊芯片。大功率倒装焊散热结构主要跟功率、导热界面材料、散热材料及气密性等有关系。倒装焊器件气密性封装主要有平行缝焊或低温合金熔封工艺。     

2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking

An inductive-coupling programmable bus for NAND flash memory access in solid state drive (SSD) is presented. Compared to the conventional SSD, this wireless interface using relayed transmission reduces power consumption to 1/2, I/O circuit-layout area to 1/40, and achieves a data rate of 2 Gb/s in 0.18 ?m CMOS process. In addition, since this wireless interface enables one package to contain 64 chips, the number of packages is reduced to 1/8.     

基于USB的DDS控制

采用符合USB2．0协议的FX2系列芯片中的CY7C68013,通过对其可编程接口控制逻辑的合理设计和芯片内部FIFO的有效运用,提出通过USB（通用串行总线）接口控制高性能的DDS（直接数字频率合成器）芯片AD9858的方法。USB接口具有速度快、功耗低、支持即插即用、使用安装方便等优惠。GPIF（通用可编程接口）具有快速、灵活等特点,可以根据需要进行编程,且运行中不需要CPU的干预,仅通过一些CPU标志和中断与增强型8051内核通信。AD9858是一款高性能的DDS器件,可方便快速地产生线性调频、单频脉冲及编码调制信号。因而此方法具有速度快、性能高、占用CPU资源少等特点。     

高密度陶瓷封装外壳散热问题探讨

集成电路组装密度不断增加,导致其功率密度也相应提高,集成电路单位体积发热量也有所增加。因此,解决高密度陶瓷封装外壳的散热问题刻不容缓,它也是集成电路陶瓷封装外壳需要攻克的难题之一。在外壳制造上可通过采取不同的结构设计、选择合适的散热片、对钎焊工艺进行改进、解决好散热片的电镀质量问题等措施,来保证高密度陶瓷封装外壳的热性能的要求。     

Low Power 1 GHz Frequency Synthesizer LSI's

To realize a low-power low-cost highly-reliable frequency synthesizer for a 1 GHz band radio, a bipolar presealer IC, and a CMOS LSI, consisting of a programmable counter, phase frequency comparator, and fixed divider, have been developed. The PLL synthesizer principle, using a pulse swallow counter, has been adopted for 1 GHz direct programmable count down. Adopting an advanced bipolar process and a diode AND circuit for the dual modulus presealer IC, high frequency operation at 1 GHz and 150 mW low power dissipation have been achieved simultaneously. To reduce the loop delay in the CMOS programmable counter, which limits the operating frequency, a new circuit configuration for the programmable counter and pulse swallow counter is adopted. As a result, 1 GHz frequency synthesizer LSI's have been developed with 150 mW low power dissipation for the presealer IC and 18 mW low power dissipation for CMOS LSI.     

Low-power analogue computational blocks based on high-performance floating-gate MOSFET resistor

This article proposes a new FGMOS-based programmable FGMOS resistor. A highly linear resistor is implemented by cancelling the non-term present in the drain current equation of MOSFET operating in the linear region. The inherited features of FGMOS resistor are simplicity, programmability, wider bandwidth and very low power dissipation without supply voltage. The power dissipation of the proposed FGMOS resistor is only 985 nW. Analogue computational blocks such as programmable reciprocal circuit, current to voltage converter and low-pass filter as applications of proposed programmable FGMOS resistor are also suggested. The power dissipation of reciprocal circuit and low-pass filter are 14.7 and 131 µW, respectively. To demonstrate the efficacy of the circuits, simulations are carried out using SPICE on 0.13 µm CMOS technology.     

基于现场可编程门阵列的数控延时器的设计

给出一种基于现场可编程门阵列(FPGA)的数控延时器的设计方法.首先详细介绍使用计数器的串联实现可控延时的方法,接着讨论不同延时范围下该数控延时器的改进方案,最后分析延时误差及延时精确度.延时器的外部接口仿照AD9501设计.