K-Band High-Power GaAs FET Amplifiers

Lumped-element internal matching techniques were successfully adopted for K-band power GaAs FET amplifiers. The developed 18-GHz band two-stage amplifier provides 1.05-W power output at 1-dB gain compression and 1.26-W saturated power output with 8.1-dB small-signal gain. The 20-GHz band single-stage amplifier has 1.04-W power output with 3-dB associated gain. Lumped-element internal matching circuit design as well as amplifier fabrication are described. Intermodulation distortion and AM-to-PM conversion characteristics are also presented.     

Intermodulation Distortion Analysis of Reflection-Type IMPATT Amplifiers Using Volterra Series Representation

Intermodulation distortion generated in a stable IMPATT amplifier is analyzed using Volterra series representation. An IMPATT amplifier model, which takes into account the interaction between the nonlinearities of the diode and its embedding circuitry, is described. The Volterra transfer functions are derived for this model. Nonlinear terms up to and including the fifth order are considered. Intermodulation distortion products are calculated for a low-level input signal consisting of two tones. The results of this analysis are extrapolated into the direction of increasing output power in order to obtain the third-order intercept point. Further, closed form expressions for the third-order intermodulation IM/sub 3/ and intercept point P/sub I/ are derived. The distortion of a specific 6-GHz IMPATT amplifier is evaluated for illustrative purposes; the predicted distortion behavior compares favorably with experimental results.     

Extreme chirped pulse oscillator (XCPO) using a theta cavity design

We demonstrate an extreme chirped pulse mode-locked laser, simultaneously generating near-transform-limited 3.9-ps optical pulses and /spl sim/510-ps linearly chirped output from the oscillator. The design overcomes fundamental limitations of energy extraction and nonlinearities induced by gain dynamics so that we can increase the dc current of the semiconductor optical amplifier up to 600 mA without distortion of the pulse characteristics. The maximum average power of the stretched pulses from the 1.95-GHz harmonically mode-locked semiconductor laser is measured to be 13.4 mW at 600 mA.     

Nonlinear Circuit Design Using the Modified Harmonic Balance Algorithm

A modification to a harmonic balance algorithm allows the nonlinear analysis of circuits driven by two nonharmonically related input frequencies. The algorithm was implemented on an IBM AT Personal Computer. Three examples are presented to illustrate the analysis. The first is a novel wide-band FET frequency doubler that achieves an average conversion loss of 3.5 dB over the 8-16-GHz output band. The second example illustrates a technique used in the design of a C-band power amplifier in which third-order intermodulation distortion was reduced by 8 dB with two tones of 34 dBm each at the output. The final example illustrates the gain suppression of a smaller tone in the presence of a larger one of slightly different frequency in a limiting amplifier. Simulations agree with measurements in which 2.5-dB gain suppression was observed in a 2-GHz FET feedback amplifier driven into saturation.     

Design Methodology for a 40-GSamples/s Track and Hold Amplifier in 0.18-$muhbox m$SiGe BiCMOS Technology

A 40-GSamples/s track and hold amplifier (THA) is designed and fabricated in 0.18-$muhbox m$SiGe BiCMOS and operates from a 3.6-V supply. The total power consumption is 540 mW with a chip area of 1.1$hbox mm^2$. Time domain measurements demonstrate 40-GHz sampling and$ S$-parameter measurements show a 3-dB bandwidth of 43 GHz in track mode. For 19-GHz input signals, a total harmonic distortion of$-hbox 27~dB$at the 1dB compression point has been measured and a spurious-free dynamic range of 35 dB has been achieved.     

Design and Performance of Monolithic GaAs Direct-Coupled Preamplifiers and Main Amplifiers

The design and performance of a GaAs direct-coupled preamplifier and main amplifier is described. The amplifiers are fabricated by the self-aligned implantation for n/sup +/ -Iayer technology (SAINT) process. The developed preamplifiers have 13-dB gain, 3-GHz bandwidth, and 4.8-dB noise figure for the one-stage amplifier, and 22-dB gain, 2.7-GHz bandwidth, and 5.6-dB noise figure for the two-stage amplifier. The developed four-stage main amplifier has 36-dB gain and 1.5-GHz bandwidth with a power consumption of 710 mW. These amplifiers are promising candidates for application to high-speed data communication systems.     

STS-768 multiplexer with full-rate output data retimer in InP HBT

A 16:1 STS-768 multiplexer IC has been designed and fabricated using the Vitesse Semiconductor VIP-1 process. This IC is part of a complete chip-set solution for a 40-Gb/s STS-768 optical communication transceiver module. The multiplexer IC features a full-rate clock multiplication unit and a data retimer in the output stage to reduce duty-cycle distortion and jitter in the output data eye. Because of its strict timing requirements, this approach needs fast logic gates with a very low gate delay. The Vitesse VIP-1 process, with 150-GHz f/sub t/ and 150-GHz f/sub max/ heterojunction bipolar transistor, is an obvious choice to implement this IC. The multiplexer IC typically dissipates 3.6 W from -3.6-V and -5.2-V power supplies. This paper discusses the design and development of a 40-Gb/s 16:1 multiplexer IC including current-mode logic gate circuit design, divide-by-two, 40-GHz clock tree, voltage-controlled oscillator, clock multiplication unit, and output driver. Layout design and package design are also discussed due to their significant roles in the IC performance.     

10-GHz Si bipolar amplifier and mixer ICs for coherent opticalsystems

Using a 30-GHz f_T silicon bipolar process, 10-GHz amplifier and mixer ICs for a multigigabit-per-second coherent optical-fiber communication system were fabricated. The dual-feedback amplifier with triple Darlington achieves a 10-GHz bandwidth and 20-dB gain. The Gilbert-cell mixer operates up to 10 GHz with a 10-dB conversion loss. The simulation technique, used for the design of these ICs includes an improved interconnect line model for the high-frequency region. The 10-GHz amplifier has a 1-mm² chip size and 210-mW power dissipation. The mixer has 2-mm² chip size and 550-mW power dissipation     

A 5-GHz 20-dBm Power Amplifier With Digitally Assisted AM-PM Correction in a 90-nm CMOS Process

This paper presents an integrated CMOS power amplifier and a technique for correcting AM-PM distortion in power amplifiers. The linearization technique uses a varactor as part of a tuned circuit to introduce a phase shift that counteracts the AM-PM distortion of the power amplifier. The varactor is controlled by the amplitude of the IQ baseband data in a feedforward fashion. The technique has been demonstrated in a 5-GHz class-AB CMOS power amplifier designed for WLAN applications and implemented in a 90-nm CMOS process. The power amplifier delivers 16 dBm of average power while transmitting at 54 Mb/s (64 QAM). The proposed linearization technique is shown to improve the efficiency of the power amplifier by a factor of 2.8.     

A fully balanced pseudo-differential OTA with common-mode feedforward and inherent common-mode feedback detector

A pseudo-differential fully balanced fully symmetric CMOS operational transconductance amplifier (OTA) architecture with inherent common-mode detection is proposed. Through judicious arrangement, the common-mode feedback circuit can be economically implemented. The OTA achieves a third harmonic distortion of -43 dB for 900 mV/sub pp/ at 30 MHz. The OTA, fabricated in 0.5-/spl mu/m CMOS process, is used to design a 100-MHz fourth-order linear phase filter. The measured filter's group delay ripple is 3% for frequencies up to 100 MHz, and the measured dynamic range is 45 dB for a total harmonic distortion of -46 dB. The filter consumes 42.9 mW per complex pole pair while operating from a /spl plusmn/1.65-V power supply.     

Quasi-linear amplification using self-phase distortion compensationtechnique

This paper demonstrates a self-phase distortion compensation technique to realize linear power amplifiers, in which the positive phase deviation from a common-source FET and the negative phase deviation from a common-gate FET cancel each other. It is confirmed both theoretically and experimentally that increasing the drain-to-source conductance, G_d, causes the self-phase distortion compensation effect. An experimental power amplifier for L-band personal communications systems, which employs the cascode connection, shows good phase deviation performance. More than 20-dB gain, 21-dBm output power, and 50% power added efficiency are obtained along with the adjacent channel interference of -52 dBc in 192-kHz bands at 600-kHz offset frequency from 1.9 GHz at the operating voltage of only 3 V. The demonstrated performances satisfy the specifications for the 1.9-GHz Japanese Personal Handy-phone System (PHS) utilizing the π/4-shift QPSK modulation scheme. The proposed technique is suitable for MMIC design, and allows the design of handsets that are small, lightweight, and have long operating times     

Development of multiband phase shifters in 180-nm RF CMOS technology with active loss compensation

We present the design and development of a novel integrated multiband phase shifter that has an embedded distributed amplifier for loss compensation in 0.18-/spl mu/m RF CMOS technology. The phase shifter achieves a measured 180/spl deg/ phase tuning range in a 2.4-GHz band and a measured 360/spl deg/ phase tuning range in both 3.5- and 5.8-GHz bands. The gain in the 2.4-GHz band varies from 0.14 to 6.6 dB during phase tuning. The insertion loss varies from -3.7 dB to 5.4-dB gain and -4.5 dB to 2.1-dB gain in the 3.5- and 5.8-GHz bands, respectively. The gain variation can be calibrated by adaptively tuning the bias condition of the embedded amplifier to yield a flat gain during phase tuning. The return loss is less than -10 dB at all conditions. The chip size is 1200 /spl mu/m/spl times/2300 /spl mu/m including pads.     

Monolithic ultra-broadband transimpedance amplifiers usingAlGaAs/GaAs heterojunction bipolar transistors

Monolithic ultra-broadband transimpedance amplifiers are developed using AlGaAs/GaAs HBTs. To realize good amplifier performances, two factors are mentioned: an affordable HBT fabrication process using the self-aligned method and an optimized circuit design considering large signal operations. The developed HBT fabrication process achieves excellent uniformity in DC characteristics and the effect on amplifier microwave performances, derived from the discrete device uniformity, is estimated. Amplifier circuit configurations are designed by harmonic balance simulation using the extracted large signal device parameters The fabricated amplifier exhibits a DC to 13.4-GHz bandwidth with an 18.1-dB gain. Fairly good uniformity is also achieved for the amplifier microwave performances. An optical receiver module is constructed mounting the developed HBT amplifier and InGaAs p-i-n photodiode chips. The optical receiver module provides a 9.4-GHz bandwidth and an optical receiver sensitivity of -15.7 dBm at 10-Gb/s data rate     

A 2-GHz optical receiver using commercially available components

A 2-GHz optical receiver consisting of a Ge avalanche photodiode and a four-stage bipolar transistor amplifier is described. Commercially available components are used. Characterization and optimization of the optical receiver were carried out by computer simulation. Responsivity, noise equivalent power, and group delay were measured up to 2.3 GHz.     

An 8-18-GHz YIG-Tuned FET Oscillator

We report here on the design and construction of a YIG- tuned FET oscillator tunable over the entire 8-18-GHz frequency range. The minimum output power from this device operating into a 50-omega load is about +6 dBm. The addition of a balanced buffer amplifier increases the power to about + 12-dBm minimum. When optimized for the 12-18-GHz band, the oscillator alone generates a minimum of + 10 dBm. The oscillator/ amplifier combination produces at least +15 dBm. We discuss a number of difficulties inherent in the design of broad-band oscillators, especially fixed frequency resonances, linearity, and power drop outs at the low end of the frequency range.     

38-GHz-band high-power MMIC amplifier module for satellites onboard use

The design and development results of 38-GHz high-power MMIC amplifier modules for use in the solid-state power amplifier (SSPA) to be carried aboard Engineering Test Satellite VI in 1993 are presented. This amplifier will be used in millimeter-wave intersatellite communication experiments. For the development of this amplifier, high-power, highly reliable FETs with 0.25-μm-long gates were designed. The FET large-signal impedance was accurately measured using an improved load-pull method and MMIC transformers. The measurements were used to design two types of MMICs: one composed of two FET cells with 600-μm-wide gates and the other of four FET cells with 400-μm-wide gates. A two-stage amplifier package consisting of two of these MMICs that can be used at 38 GHz is also developed. A P _o(1 dB) of 25 dBm and a gain of 11 dB are obtained. A 38-GHz test conducted during chip screening achieves a high production yield without circuits adjustment     

High average power, high repetition rate, picosecond pulsed fiber master oscillator power amplifier source seeded by a gain-switched laser diode at 1060 nm

We demonstrate a pulsed ytterbium-doped fiber master-oscillator power amplifier source at 1060 nm producing over 300 W of average power in 20-ps pulses at 1-GHz repetition rate. The pulses generated by a gain-switched diode were compressed by a chirped fiber Bragg grating and amplified without any distortion with excellent spectral quality. This fiber master oscillator power amplifier system offers versatility and potential for further power scaling.     

Simple, low-cost, subsystem fabrication

We have successfully developed a simple and low-cost 1.9-GHz, 25-W power amplifier by using only one prematched 50-mm PHEMT with external matching circuits on a FR-4 PCB. As the output stage integrated with other driver stages and dc control circuits, a completed four-stage power-amplifier subsystem is also demonstrated. When operating at 38.5-dBm output power with /spl pi//4-DQPSK signal, the proposed power amplifier subsystem shows low distortion, with better than 75-dBc ACPR (adjacent-channel leakage power ratio) at 600 kHz and 79-dBc ACPR at 900 kHz offset from the center frequency, and is suitable for PHS 500-mW base-station applications.     

A Graphical Method for the Design of Feedback Networks for Microwave Transistor Amplifiers: Theory and Applications

A new theory is presented that is very useful for the design of feedback transistor amplifiers, including considerations on stability, gain equalization, and matching. The theory is based on graphical feedback diagrams whose construction rides and practical circuit design techniques are described. The method provides insight into the effects of the feedback network elements and saves computer time and money. Three applications are presented: a tuned neutralized bipolar transistor amplifier; a broad-band medium power MESFET amplifier in the 3.7-4.2-GHz range; and a ultrawide-band matched MESFET amplifier covering the 0.1- 12-GHz frequency range.     

宽带卫星信道群时延的自适应均衡校正研究

在宽带卫星通信链路中,由于器件通带特性不理想和行波管放大器的工艺受限等原因使卫星信道的群时延波动较大,导致误比特性能恶化。群时延的补偿算法需要复杂的数学运算,因此工程上一般采用线性均衡对信道群时延特性进行校正。针对群时延失真严重情况下线性均衡效果下降的问题,对比研究了线性均衡、非线性均衡对信道群时延校正的性能,仿真分析了采用恒模算法的线性均衡和采用voherra模型的非线性均衡在群时延失真信道下的性能,得出了两类均衡器在群时延失真信道下的误码率性能曲线,结果表明低阶调制下采用非线性均衡可以较好的消除宽带卫星信道群时延的影响。