Digital based calibration technique for continuous-time bandpass sigma-delta analog-to-digital converters

In this paper, a calibration technique for Noise Transfer Function (NTF) optimization of Continuous-Time Bandpass Sigma Delta (CT BP ΣΔ) modulators is presented. The proposed technique employs a test tone applied at the input of the quantizer to evaluate the noise transfer function of the Analog-to-Digital Converter (ADC) using the capabilities of the Digital Signal Processing (DSP) platform usually available in mixed-mode systems. Once the ADC output bit stream is captured, necessary information to generate the control signals to tune the ADC parameters for best Signal-to-Quantization Noise Ratio (SQNR) performance is extracted via an LMS software-based algorithm. Simulation results show that notch frequency of the NTF due to process variations and temperature tolerances can be tuned using the proposed methodology. The proposed global calibration approach can be used during the system start-up and the idle system time. The proposed approach uses a single in-band calibration tone, but it can be expanded using out-of band test tones for background calibration schemes.     

The design of sigma-delta modulation analog-to-digital converters

The author examines the practical design criteria for implementing oversampled analog/digital converters based on second-order sigma-delta (ΣΔ) modulation. Behavioral models that include representation of various circuit impairments are established for each of the functional building blocks comprising a second-order Σ2gD modulator. Extensive simulations based on these models are then used to establish the major design criteria for each of the building blocks. As an example, these criteria are applied to the design of a modulator that has been integrated in a 3-μm CMOS technology. An experimental prototype operates from a single 5-V supply, dissipates 12 mW, occupies an area of 0.77 mm², and has achieved a measured dynamic range of 89 dB     

Exact design of continuous-time sigma-delta modulators with multiple feedback DACs

A technique for the exact design of the noise transfer function of Continuous-Time (CT) Sigma-Delta modulators with arbitrary and multiple DAC responses and real op-amps is here presented. The approach, that presupposes linear behavior of active blocks, produces a CT modulator with the same noise shaping as its Discrete-Time counterpart. The method operates entirely in the time domain and accounts for non-idealities of real implementations such as finite gain and bandwidth of integrators. The procedure can be effectively implemented with circuit simulators to allow the exact design with transistor level blocks. A design example on a third-order scheme confirms the effectiveness of the method.     

An overview of sigma-delta converters

Using sigma-delta A/D methods, high resolution can be obtained for only low to medium signal bandwidths. This article describes conventional A/D conversion, as well as its performance modeling. We then look at the technique of oversampling, which can be used to improve the resolution of classical A/D methods. We discuss how sigma-delta converters use the technique of noise shaping in addition to oversampling to allow high resolution conversion of relatively low bandwidth signals. We examine the use of sigma-delta converters to convert narrowband bandpass signals with high resolution. Several parallel sigma-delta converters, which offer the potential of extending high resolution conversion to signals with higher bandwidths, are also described     

On numerical optimization of communications system design

The limiting factor in the use of computer tools for the design of communications systems is often the amount of human intervention needed, rather than the actual computation time. A technique is presented by which a large proportion of the low-level decision making is delegated to the computer, thereby allowing the designer to concentrate on the engineering aspects and higher-level tradeoffs. The implementation described can be used with existing design programs (e.g., transmission simulators). The possibilities and limitations of the technique are discussed, and several examples of its application are given     

Analysis and design of high-performance asynchronous sigma-delta Modulators with a binary quantizer

Asynchronous sigma-delta modulators (ASDMs) are closed-loop nonlinear systems that transform the information in the amplitude of their input signal into time information in the output signal, without suffering from quantization noise such as in synchronous sigma-delta modulators. This is an important advantage with many interesting applications. In contrast with their synchronous counterparts, ASDMs have been underexposed. Both conceptually and analytically, they are quite complex. This paper investigates in detail the analysis, design and circuit-implementation aspects of ASDMs with a binary quantizer. In the ASDM, the amplitude-time transformation is done using an inherent self-oscillation denoted as a limit cycle. The oscillation frequency is addressed as the main design parameter that determines the spectral properties of the ASDMs and the quality of the amplitude-time transformation. Analytical and graphical derivations of the limit cycle frequency are treated. The impact of the filter order and the properties of the nonlinear element are elaborated on. Circuit implementations and the tradeoffs in the design are presented for a first- and a second-order ASDM that target the VDSL front-end specifications. Prototypes are implemented in a digital 0.18-/spl mu/m 1.8-V CMOS technology. The measured SFDR is 75dB in a frequency band of 8MHz for the first-order ASDM, and 72dB in a band of 12MHz for the second-order ASDM. The dissipated power is 1.5 mW and 2.2 mW, respectively.     

Compensation of finite gain-bandwidth induced errors in continuous-time sigma-delta modulators

This paper introduces a possible compensation for finite gain-bandwidth (GBW) induced errors in continuous-time sigma-delta modulators. Therefore, a novel model is derived which reduces the effect of a finite GBW to a corresponding integrator gain-error and feedback loop delays. Thus, previously published methods for the compensation of these errors can be adopted with some modification. The results are confirmed analytically and by simulations and show a possible GBW reduction of about one order of magnitude compared to current designs.     

Harmonic optimization of multilevel converters using genetic algorithms

In this letter, a genetic algorithm (GA) optimization technique is applied to determine the switching angles for a cascaded multilevel inverter which eliminates specified higher order harmonics while maintaining the required fundamental voltage. This technique can be applied to multilevel inverters with any number of levels. As an example, in this paper a seven-level inverter is considered, and the optimum switching angles are calculated offline to eliminate the fifth and seventh harmonics. These angles are then used in an experimental setup to validate the results.     

Multilevel optimization in the design of a high-performance GaAsmicrocomputer

Multilevel optimization in the design of an instruction cache for a high-performance GaAs microprocessor is discussed. The performance of the system is maximized by concurrently considering the interrelationships of (1) the time of flight of signals across the multichip module on which the processor and cache chips are mounted, (2) the clocking scheme that synchronizes these signals, and (3) the size of the cache. These three design issues are normally considered independently because they arise in different abstraction levels. Design automation tools developed to facilitate this multilevel optimization are described. This process, applied to various subsystems, has been used to gain substantial performance improvement in the GaAs microcomputer     

The design of high-order bandpass sigma-delta modulators using low-spread single-stage structure

A structure for single-stage high-order bandpass sigma-delta modulators (BPSDMs) is presented. The proposed structure introduces an additional internal path in each resonator, thus, adding one degree of freedom in coefficient determination. Coefficient spread can therefore be reduced, resulting in significantly reduced capacitance area in switched-capacitor BPSDM circuits. High-order BPSDMs with different quality factors (Q) are demonstrated. It shows that coefficient spread is significantly reduced, especially for high-Q applications. For comparable eighth-order 3-bit BPSDMs, the maximum coefficient spread are respectively 15369 and 7693 for conventional cascade-of-resonator-with-feedback (CRFB) and cascade-of-resonator-with-feedforward (CRFF) designs, and 114 for the proposed structure. For an eighth-order 1-bit example, these respective values are 8994, 2638, and 74. With coefficient mismatch, peak signal-to-noise ratio (PSNR) degradation of the proposed structure is less than those of the CRFB and CRFF structures, demonstrating reduced sensitivity to component mismatch. Hence, the proposed structure can reduce chip area and ease circuit implementation of BPSDMs.     

宽带∑-△A/D转换器中数字抽取滤波器的设计与验证

无线便携式移动设备与宽带intemet接入技术的发展,对∑-△A/D转化器的带宽要求越来越高。文中结合前端5阶宽带乏△调制器,设计了一种降低功耗与面积的数字抽取滤波器,应用于宽带高精度AD转换器中。MATLAB／simulink仿真结果表明,经过数字抽取滤波器滤波后信噪比为97．8dB,通带边界频率为1．8MHz,最小阻带衰减为70dB,通带内波纹0．0025dB,可满足设计要求。∑-△A/D转换器高精度、低功耗的优点,可广泛应用于中特种设备检验检测仪器仪表中。     

System level design and optimization of single-loop CT sigma-delta modulators for high resolution wideband applications

In this paper, the main resolution limitations in single-stage continuous-time sigma-delta modulators (CT ΣΔMs) are analytically estimated as the function of system level parameters for wideband applications. The analytical results are supported by simulation results. The power consumption of CT ΣΔMs is also analytically estimated as the function of system level parameters, and then, it is validated by the reported power consumption of several state-of-the-art fabricated prototypes. Based on analytical results, for a targeted resolution and bandwidth, an algorithm is proposed to design the system level parameters of CT ΣΔMs for the minimum power consumption. The estimation of power consumption and the designed parameters match well with the design of best state-of-the-art fabricated modulators.     

On the robustness of single-loop sigma-delta modulation

Sigma-delta modulation, a widely used method of analog-to-digital (A/D) signal conversion, is known to be robust to hardware imperfections, i.e., bit streams generated by slightly imprecise hardware components can be decoded comparably well. We formulate a model for robustness and give a rigorous analysis for single-loop sigma-delta modulation applied to constant signals (DC inputs) for N time cycles, with an arbitrary (small enough) initial condition u_o, and a quantizer that may contain an offset error. The mean-square error (MSE) of any decoding scheme for this quantizer (with u_o and the offset error known) is bounded below by 1/96N^-3. We also determine the asymptotically best possible MSE as N→∞ for perfect decoding when u_o=0 and u_o=½. The robustness result is the upper bound that a triangular linear filter decoder (with both u_o and the offset error unknown) achieves an MSE of 40/3N^-3. These results establish the known result that the O(1/N³) decay of the MSE with N is optimal in the single-loop case, under weaker assumptions than previous analyses, and show that a suitable linear decoder is robust against offset error. These results are obtained using methods from number theory and Fourier analysis     

The design of A/D converters using two-range comparators

In this paper, a new architecture for performing analog-to-digital conversion with the throughput of flash conversion, but with some relief from the high power and area requirements, is presented. The key element of this technique is the two-range comparator circuit. This new circuit compares the analog input with more than one reference voltage simultaneously, allowing for a large reduction in the total number of comparator circuits required. Simulation results are presented which show a performance increase of 20% in a converter implemented with the new comparator when compared to a conventional flash converter operated at the same power dissipation level.     

The design and optimization of high-performance, double-polyself-aligned p-n-p technology

The device design and performance of double-poly self-aligned p-n-p technology, featuring a low-resistivity p⁺ subcollector, thin p-epi, and boron-doped poly-emitter are described. Device isolation is provided by deep and shallow trenches which reduce the collector-to-substrate capacitance while maintaining a high breakdown voltage (⩾40 V). By utilizing a shallow emitter process in conjunction with an optimized arsenic-base implant, devices with emitter-base junction depths as shallow as 20 nm and base widths of less than 100 nm were obtained. Cutoff frequencies of up to 27 GHz were obtained, and the AC performance was demonstrated by an NTL-gate delay of 36 ps and an active-pull-down (APD) ECL-gate delay of 20 ps. This high-performance p-n-p technology was developed to be compatible with existing double-poly n-p-n technologies. The matching speed of p-n-p devices opens up new opportunities for high-performance complementary bipolar circuits     

Search for high-performance probe-fed stacked patches using optimization

High-performance circular probe-fed stacked patch antenna designs are explored through the use of numerical optimization. New trends are sought to aid understanding and to suggest novel solutions. We describe the optimization technique, present a new design trend relating efficiency and bandwidth to the choice of substrate dielectric, and propose and demonstrate a novel, optimized antenna achieving 33% bandwidth whilst maintaining greater than 80% surface wave efficiency.     

On chip testing data converters using static parameters

In this paper, built-in self-test (BIST) approach has been applied to test digital-to-analog (D/A) and analog-to-digital (A/D) converters. Offset, gain, integral nonlinearity (INL), and differential nonlinearity (DNL) errors and monotonicity are tested without using mixed-mode or logic test equipment. An off-line calibrating technique has been used to insure the accuracy of BIST circuitry and to reduce area overhead by avoiding the use of high quality analog blocks. The proposed BIST structure presents a compromise between test cost, area overhead, and test time. By a minor modification the test structure would be able to localize the fail situation. The same approach may be used to construct a fast low cost off-chip D/A converter tester. The BIST circuitry has been designed and evaluated using complementary metal-oxide-semiconductor (CMOS) 1.2 μm technology     

Analysis, design, and optimization of InGaP-GaAs HBTmatched-impedance wide-band amplifiers with multiple feedback loops

The realization of matched impedance wide-band amplifiers fabricated by InGaP-GaAs heterojunction bipolar transistor (HBT) process is reported. The technique of multiple feedback loops was used to achieve terminal impedance matching and wide bandwidth simultaneously. The experimental results showed that a small signal gain of 16 dB and a 3-dB bandwidth of 11.6 GHz with in-band input/output return loss less than -10 dB were obtained. These values agreed well with those predicted from the analytic expressions that we derived for voltage gain, transimpedance gain, bandwidth, and input and output impedances. A general method for the determination of frequency responses of input/output return losses (or S₁₁, S₂₂) from the poles of voltage gain was proposed. The intrinsic overdamped characteristic of this amplifier was proved and emitter capacitive peaking was used to remedy this problem. The tradeoff between the input impedance matching and bandwidth was also found     

Fast simulation of sigma-delta modulators using SPICE

Presents a fast simulation method using SPICE. We traded the prohibitive time-consuming simulation problem for a much less time-consuming problem, plus a little analysis work. This makes it possible for one to use SPICE simulation to optimize the parameters in the modulator within a reasonable time period. Rounding and truncation errors within the circuit simulation algorithms typically set an upper limit on the measurable SNR on the order of 90 dB. This implies that very high-resolution modulators cannot correctly be simulated by SPICE. Fortunately, 90 dB resolution is adequate for most modern communication baseband A/D converters     

A wide-band multiport planar power-divider design using matchedsectorial components in radial arrangement

This paper proposes a new multiport planar power-divider design by radially combining the sectorial components and the input and output matching networks. This design can achieve good input match over a wide bandwidth without resorting to transformer sections of high-impedance lines, which are difficult to realize. This approach is applied to the design of 4-and 14-way center-fed power dividers in microstrip structures with good input match (voltage standing-wave ratio (VSWR) <1.5) over a bandwidth of 30% and 15%, respectively. The return loss of output ports and the isolation among them in the 14-way divider are less than -13 dB. A simple analysis method using the radial transmission-line theory to model the microstrip sectorial components is employed to characterize the power dividers. The calculated scattering parameters are found to be in good agreement with the measured data