H．263 VIDEO CODEC IMPLEMENTATION BASED ON MULTIMEDIA DSP

This letter introduces the implementation of H.263 video codec based on multimedia DSP TM1300,and discuses several key problems related to video coding.     

Efficient HD video coding with joint first-order-residual (FOR) and second-order-residual (SOR) coding technique

A new video coding algorithm called the first-order-residual/second-order-residual (FOR/SOR) codec is proposed for high definition (HD) video coding in this work. Several advanced coding techniques are adopted in the proposed FOR/SOR codec. For the FOR codec, the well known block-based motion compensated predictive codec is used to exploit temporal and spatial correlations in input image frames. However, it is observed that there still exists structured residual signal after the FOR coding, and a SOR coder is developed to encode residual image frames efficiently. To improve the coding performance furthermore, we consider bit allocation between the FOR and SOR coders at the same block and determine their optimal quantization parameters systematically. It is shown by experimental results that the proposed FOR/SOR codec outperforms H.264/AVC significantly in HD video coding.     

基于双DSP结构的实时视频压缩编码器

本文讨论了实时视频压缩编码器的设计与实现，提出了一种DSP加运动协处理器的系统结构，给出了用单象素精度运动估计器实现1／2精度运动估计的方法，并列出了系统可实现的性能指标。     

基于Digital 21230芯片的数字图像监控系统

建立了一种适用保于高速信道的一代数字图像监控系统,并就涉及的关键技术和实现方法进行了讨论。采用Ｄｉｇｉｔａｌ２１２３０芯片硬件件实现视音频ＭＰＥＧ－１标准的实时压缩与解压缩,软件上基于Ｗｉｎｄｏｗｓ９ｘ／ＮＴ平台用ＶｓｕａｌＣ＋＋开发了一套完整的视音频编解码控制,同步步传输和系统多功能操作等应用程序。     

Perceptually driven video error protection using a distributed source coding approach

In video communication systems, the video signals are typically compressed and sent to the decoder through an error-prone transmission channel that may corrupt the compressed signal, causing the degradation of the final decoded video quality. In this context, it is possible to enhance the error resilience of typical predictive video coding schemes using as inspiration principles and tools from an alternative video coding approach, the so-called Distributed Video Coding (DVC), based on the Distributed Source Coding (DSC) theory. Further improvements in the decoded video quality after error-prone transmission may also be obtained by considering the perceptual relevance of the video content, as distortions occurring in different regions of a picture have a different impact on the user's final experience. In this context, this paper proposes a Perceptually Driven Error Protection (PDEP) video coding solution that enhances the error resilience of a state-of-the-art H.264/AVC predictive video codec using DSC principles and perceptual considerations. To increase the H.264/AVC error resilience performance, the main technical novelties brought by the proposed video coding solution are: (i) design of an improved compressed domain perceptual classification mechanism; (ii) design of an improved transcoding tool for the DSC-based protection mechanism; and (iii) integration of a perceptual classification mechanism in an H.264/AVC compliant codec with a DSC-based error protection mechanism. The performance results obtained show that the proposed PDEP video codec provides a better performing alternative to traditional error protection video coding schemes, notably Forward Error Correction (FEC)-based schemes.     

语音编解码算法G.729的软件实现

首先对G.729编解码算法的原理进行了简要分析,接着讨论了如何在定点DSP芯片ADSP218x上实现该算法,并指出了其关键技术,最后给出了运算量分析结果。     

A single-chip adaptive DPCM video codec

A differential pulse-code modulation (DPCM) video codec with two-dimensional intrafield prediction and adaptive quantizer is presented. An approach for the arithmetic implementation of the DPCM structure and the design of a test chip, fabricated in a 1.5 μm CMOS technology, is described. This is the first VLSI realization of a DPCM codec with adaptive quantizer. For the test chip transmitter or receiver mode, application as part of a three-dimensional interframe codec and processing of luminance or chrominance signals are optional. A line buffer and ten different quantizer characteristics are realized on-chip. Correct operation has been verified up to 26 MHz     

基于TMS320F2812的多通道实时语音编解码

介绍了自适应多码率语音编解码算法及其基于TMS320F2812定点DSP芯片的实现方案。利用TMS320F2812芯片集成的多路ADC和PWM,对方案进行了多通道的扩展。分析了在DSP芯片上实现实时语音编解码及多通道扩展的关键技术。最后分析了此多通道实时语音编解码方案所需的存储空间和计算复杂度。     

The big squeeze-a CELP speech codec

The coding algorithm widely recognised as offering the best prospects for delivering toll-quality speech at very low bit rates is called CELP (codebook-excited linear prediction) coding. The CELP codec by Delphi Systems operates in real time, uses a standard digital signal processing chip, and encodes speech at 4.8 and 6.5 kbit/s. The use of this speech compression codec (SCC) is also discussed     

Performance Analysis for MPEG‐4 Video Codec Based on On‐Chip Network

In this paper, we present a performance analysis for an MPEG‐4 video codec based on the on‐chip network communication architecture. The existing on‐chip buses of system‐on‐a‐chip (SoC) have some limitation on data traffic bandwidth since a large number of silicon IPs share the bus. An on‐chip network is introduced to solve the problem of on‐chip buses, in which the concept of a computer network is applied to the communication architecture of SoC. We compared the performance of the MPEG‐4 video codec based on the on‐chip network and Advanced Micro‐controller Bus Architecture (AMBA) on‐chip bus. Experimental results show that the performance of the MPEG‐4 video codec based on the on‐chip network is improved over 50% compared to the design based on a multi‐layer AMBA bus.     

六角变换方法在视频编码中的应用

介绍了一些有关DCT及其快速算法的关键技术,提出了六角变换方法及其应用于视频编码的近似整数实现.实验结果表明,六角变换方法不仅具有相比浮点DCT实现复杂度低、解码端无误差累积的优点,而且能提供相比其他整数近似变换更高的视频编码效率.     

Reconfigurable video coding on multicore

The current monolithic and lengthy scheme behind the standardization and the design of new video coding standards is becoming inappropriate to satisfy the dynamism and changing needs of the video coding community. Such scheme and specification formalism does not allow the clear commonalities between the different codecs to be shown, at the level of the specification nor at the level of the implementation. Such a problem is one of the main reasons for the typically long interval elapsing between the time a new idea is validated until it is implemented in consumer products as part of a worldwide standard. The analysis of this problem originated a new standard initiative within the International Organization for Standardization (ISO)/International Electrotechnical Commission (IEC) Moving Pictures Experts Group (MPEG) committee, namely Reconfigurable Video Coding (RVC). The main idea is to develop a video coding standard that overcomes many shortcomings of the current standardization and specification process by updating and progressively incrementing a modular library of components. As the name implies, flexibility and reconfigurability are new attractive features of the RVC standard. Besides allowing for the definition of new codec algorithms, such features, as well as the dataflow-based specification formalism, open the way to define video coding standards that expressly target implementations on platforms with multiple cores. This article provides an overview of the main objectives of the new RVC standard, with an emphasis on the features that enable efficient implementation on platforms with multiple cores. A brief introduction to the methodologies that efficiently map RVC codec specifications to multicore platforms is accompanied with an example of the possible breakthroughs that are expected to occur in the design and deployment of multimedia services on multicore platforms.     

Design of a DPCM codec for VLSI realization in CMOS technology

Current perspectives on broad-band communication services have made the realization of a DPCM system for video coding on a single integrated circuit particularly important. A nonadaptive intraframe DPCM system is designed for reducing video transmission bit rate by a factor of two. All functional blocks of a DPCM codec have been specified, and modifications have been investigated for reducing speed requirements. Alternative realizations of functional blocks, e.g., adders, subtractors, table look-up operations, are compared with respect to speed by a simple delay model. A one-chip VLSI implementation of an efficient DPCM codec will be possible with a 2-µm CMOS technology.     

基于H.264的可视电话软件开发

为了开发基于H.264标准的可视电话,采用高性能高速视频数字处理芯片(TMS320DM642)作视频编解码器,充分利用芯片的并行和流水处理功能,在单芯片上实现了视/音频编解码的并行实时处理,并达到可视电话实时通信要求.     

MPEG-4解码器芯片的比较

介绍了目前市场上比较流行的一些MPEG-4编解码芯片，比较了它们的应用前景和特性，并简要介绍了新一代视频编解码标准H．264的芯片产品。     

An ADPCM Receiver for NTSC Composite Video Signals

An ADPCM codec for carrying one broadcast quality NTSC color TV channel at a bit rate of 42.9 Mb/s has been proposed. The system uses 3 fsc sampling, adaptive intrafield contour prediction, adaptive quantization., 4/8-bit dual length coding, and horizontal blanking interval suppression techniques. The receiver of.the video codec is designed and implemented in ECL for recovery of the original signal. The receiver accepts.a 42.9 Mb/s serial data stream with a synchronous clock from the transmitter. The receiver detects the line synchronization code, demultiplexes the audio signal and video signal, and generates the horizontal blanking patterns which have been removed at the transmitter side. The 4/8-bit dual length code is decoded and fed to the ADPCM reconstruction loop to obtain the reconstructed active video signal. The generated horizontal blanking pattern is multiplexed with the reconstructed video=signal and sent through a D/A converter to form the reconstructed analog NTSC composite video signal.     

Cross-layer optimization for video transmission over multirate GMC-CDMA wireless links.

In this paper, we consider the problem of video transmission over wireless generalized multicarrier code division multiple access (GMC-CDMA) systems. Such systems offer deterministic elimination of multiple access interference. A scalable video source codec is used and a multirate setup is assumed, i.e., each video user is allowed to occupy more than one GMC-CDMA channels. Furthermore, each of these channels can utilize a different number of subcarriers. We propose a cross-layer optimization method to select the source coding rate, channel coding rate, number of subcarriers per GMC-CDMA channel and transmission power per GMC-CDMA channel given a maximum transmission power for each video user and an available chip rate. Universal rate distortion characteristics (URDC) are used to approximate the expected distortion at the receiver. The proposed algorithm is optimal in the operational rate distortion sense, subject to the specific setup used and the approximation caused by the use of the URDC. Experimental results are presented and conclusions are drawn.     

AND-OR tree-based mode selection for video coding

The conventional video coding approach is pragmatic in that researchers design different methods and compare their results to state-of-the-art methods. Although the H.264/AVC baseline is effective, there is a need to develop an abstract view of video coding, in the hope that new insights can be derived from the abstraction. In this paper, we propose a preliminary approach based on an AND-OR tree representation of video coding. We show that the H.264/AVC baseline can be represented as an AND-OR tree structure. Based on the AND-OR tree representation, we propose two video coding systems: one is a T+2D wavelet codec based on a motion-compensated temporal filtering (MCTF) lifting structure, and the other is the AND-OR tree implementation of the H.264/AVC baseline. We also compare the proposed systems’ coding performance in terms of the PSNR with that of H.264/AVC JM 16.2.     

Instruction Set Extensions for MPEG-4 Video

This paper describes instruction set extensions for the acceleration of MPEG-4 algorithms on programmable (RISC-) CPUs. MPEG-4 standardizes audio and video compression schemes for a variety of bit rates and scenarios. As MPEG-4 targets a much broader range of different applications than previously defined hybrid video coding standards like H.263 or MPEG-2, it employs a much higher number of different algorithms and coding modes. Therefore, MPEG-4 implementations will require a more software-oriented approach to be efficient. However, the total computational load for an optimized implementation of an MPEG-4 video codec is expected to exceed the performance levels of today's multimedia signal processors, making further hardware acceleration a necessity. For that purpose, we propose a number of instruction set extensions that add function-specific blocks to the data path of a CPU. These dedicated modules are highly adapted to the most computation-intensive processing schemes of MPEG-4, such as DCT, motion compensation, padding, shape coding, or bitstream parsing. The increased functionality of basic instructions results in a significant speed-up over standard RISC instruction sets, thus making MPEG-4 implementations feasible on programmable processor platforms. Possible target architectures include VLIW multimedia processors, MIMD-style multiprocessors, or coprocessor architectures     

基于SIP的H.264视频电话终端设计

考虑到实现的难易程度、生产成本和升级更新等因素,介绍了一种基于SIP的H.264视频电话终端的设计和实现方法。主要讨论了采用高速数字处理芯片TMS320DM643完成H.264编解码和利用ARM9芯片S3C2410实现SIP协议。给出具体的软、硬件设计方案,对研制的样机测试表明该视频电话终端能进行语音和视频信息的实时通信,遵循开放协议,具有良好的兼容性。