单向Hash函数SHA-256的研究与改进

对Hash函数SHA-256进行了研究,分析了SHA-256的算法逻辑,以及它所采用的压缩函数的构造,在此基础上研究设计了一个改进的Hash函数SHA-256,应用VC++开发工具对改进的Hash函数SHA-256完成了软件实现。利用理论分析和实现软件对字符串、文本文件进行Hash计算结果的比较,结果证实改进的Hash函数具有更好的非线性性、单向性、抗碰撞性、伪随机性和雪崩效应。     

一种基于循环展开结构的SHA-1算法实现

哈希算法在信息安全领域主要应用于验证数据完整性和签名认证。通过对SHA-1算法进行深入分析，提出了一种快速实现此算法的硬件方案。该方案改变了标准算法中的迭代结构，减少消息处理时钟周期数，进而提高吞吐量。与其他IP）核相比，该设计在面积、频率和吞吐量等方面表现出了较强的优势。     

SHA-2（256，384，512）系列算法的硬件实现

在同一系统中存在着对安全性要求不同的应用,可能需要对SHA--256、SHA-384、SHA一512算法进行选择,目前大部分研究只是对这几种算法单独地进行了硬件实现．本文提出了一种SHA--2（256,384,512）系列算法的VLSI结构,基于这种结构,根据不同的要求,每一种SHA-2算法都可以单独灵活地执行．本文还对该系列算法和各个独立sHA-2算法的FPGA实现进行了比较,结果表明,在面积较SHA-256实现增加40％,而与SHA-384／512基本相同的情况下,频率可达到74MHz．     

DCT快速算法及其VLSI实现

现在离散余弦变换（DCT）发展很快，本文概述了DCT的各种快速算法及其发展，将DCT算法进行了分类。文中详细地综述了适合于VLSI实现的各种DCT算法结构，并对这一领域的发展及应用前景进行了探讨。     

一种基于LMS算法的天线阵通道失配校正技术及VLSI实现

天线阵各通道之间的通道失配（幅相特性不一致）会严重影响阵列信号处理的性能[1,2],为此在进行阵列信号处理前必须对各通道的幅相特性进行均衡.本文针对天线阵通道之间与频率无关的恒定通道失配问题,提出了一种基于LMS好地校正与频率无关的通道失配.本算法的易于工程实现的通道校正技术.计算机仿真结果表明,采用这种技术可以很文最后还给出了该算法在VLSI（超大规模集成电路）平台上的实现结构.     

SHA-256算法的安全性分析

现有算法MD5、SHA-1等的相继破译,严重威胁到SHA-256、SAH-384等算法的安全性.本文介绍了SHA-256的算法逻辑及压缩函数的构造,探讨了生日攻击碰撞阈值和攻击步骤,分析了SHA-256在生日攻击下的安全性.通过对Chabaud-Joux攻击SHA-256的分析,找到了一个部分碰撞,其复杂度为,却无法找到SHA-256的一个整体碰撞.所以,在抵抗生日攻击和抵御现有差分攻击方面,SHA-256比MD5和SHA-1等具有更高的安全性.     

矢量量化算法的VLSI实现结构

本文通过将全搜索矢量量化算法（Full Search Vector Quantization）的计算转换成内积（inner product）运算，并利用Baugh-Wooley算法，阐述了FSVQ算法的一种新的有效的基于二进制补码的VLSI实现结构。由于该结构的规则性（regularity）和模块性（modularity），它可以被高效地应用在语音、图像、和视频编码的VLSI实现中。     

TEA密码算法的VLSI实现

提出了两种实现 TEA的结构 ,并采用其中一种结构设计了 TEA加解密处理器电路模块 ,将其成功地应用在非接触的智能 IC卡中 .该加解密处理器硬件模块可分别实现加密和解密运算 ,循环迭代次数具有可编程特性 .该处理器模块占用较小的芯片面积 ,具有很小的功耗 ,可以方便地与 8位微处理器连接 ,适用于各种嵌入式系统中 .     

TEA密码算法的VLSI实现

提出了两种实现TEA的结构,并采用其中一种结构设计了TEA加解密处理器电路模块,将其成功地应用在非接触的智能IC卡中．该加解密处理器硬件模块可分别实现加密和解密运算,循环迭代次数具有可编程特性．该处理器模块占用较小的芯片面积,具有很小的功耗,可以方便地与8位微处理器连接,适用于各种嵌入式系统中．     

高吞吐率、低能耗的SHA-1加密算法的硬件实现

安全散列算法被广泛应用于数据完整性验证、数字签名等领域,目前最常用的是SHA-1算法.为了满足实际应用对SHA-1计算速度和能耗的要求,提出了一种新的硬件实现方法,通过改变迭代结构,一次执行两轮操作,将80轮操作简化为40轮,进而大幅度提高SHA-1的吞吐率,并降低能耗.采用UMC0.25μm工艺实现该电路,相比于传统的实现方法,最大吞吐率提高了31%,能耗降低了20%.     

一种单芯片DVB-C解调器的VLSI实现

设计了一个单芯片实现的用于DVB-C的QAM解调器．片上集成有3.3V 10位精度的40MSPS模数转换器及FEC前向纠错解码器．该芯片支持4～256QAM多种模式，最高码率达80Mbps，具有宽的载波频偏捕获范围．采用改进的算法及VLSI实现结构，性能稳定，面积优化．采用SMIC 0.25μm 1P5M混合信号CMOS工艺制造，面积为3.5mm×3.5mm，最大功耗为447mW．     

一种单芯片DVB-C解调器的VLSI实现

设计了一个单芯片实现的用于DVB-C的QAM解调器.片上集成有3.3V 10位精度的40MSPS模数转换器及FEC前向纠错解码器.该芯片支持4～256QAM多种模式,最高码率达80Mbps,具有宽的载波频偏捕获范围.采用改进的算法及VLSI实现结构,性能稳定,面积优化.采用SMIC 0.25μm 1P5M混合信号CMOS工艺制造,面积为3.5mm×3.5mm,最大功耗为447mW.     

一种高速自适应Reed-Solomon译码结构及其VLSI优化实现

该文给出了一种自适应Reed-Solomon(RS) 译码器结构。该结构可以自适应地处理长度变化的截短码编码数据块,适合于高速译码处理。该结构使译码处理不受数据块间隙长短的约束,既可以处理独立的编码数据块也可以处理连续发送的编码数据块。另外本译码器结构可以保证输出数据块间隔信息的完整性,满足无线通信和以太网中特殊业务的要求。本文还基于该结构对RS(255,239)译码器予以实现,该译码器经过Synopsys综合工具综合并用TSMC 0.18 CMOS工艺实现,测试结果验证了该译码器的自适应功能和译码正确性,其端口处理速率可达1.6Gb/s。     

VLSI Implementation of An Adaptive Equalizer for ATSC Digital TV Receivers

An adaptive equalizer for ATSC standard HDTV receivers is developed and implemented in VLSI. This equalizer is based on the G-pseudo algorithm that combines the advantages of the decision directed and blind algorithms. It also conducts ghost cancellation for the reception of NTSC analog TV signals. A programmable error calculation unit is employed for a flexible implementation of several equalization algorithms. The filter coefficients have a long internal word-length for a satisfactory operation in the blind adaptation mode, but only parts of them are used for output calculation to reduce the hardware complexity. The performance of the system for seven GA reference channels is evaluated according to the adaptation algorithms, the number of delays for the adaptation, and the word-length of the filter coefficients. The chip area and power consumption according to the time multiplexing ratio are estimated.Wonyong Sung received the B.S. degree in electronic engineering from the Seoul National University in 1978, the M.S. degree in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST) in 1980, and the Ph.D. degree in electrical and computer engineering from the University of California, Santa Barbara, in 1987.From 1980 to 1983, he worked at the Central Research Laboratory of the Gold Star (currently LG electronics) in Korea. During his Ph.D. study, he developed parallel processing algorithms, vector and multiprocessor implementation, and low-complexity FIR filter design. He has been a member of the faculty of the Seoul National University since 1989. From May of 1993 to June of 1994, he consulted the Alta Group for the development of the Fixed Point Optimizer, automatic word-length determination and scaling software. From January of 1998 to December of 1999, he worked as a chief of the SEED (System Engineering and Design center) in Seoul National University. He was an associate editor of the IEEE Tr. Circuits and Systems II from 2000 to 2001, is a design and implementation technical committee member of the IEEE Signal Processing Society, and is a VLSI systems and application technical committee member of the IEEE Circuits and Systems Society. He was the general chair of the IEEE Workshop on Signal Processing Systems in 2003. He founded a venture company, Edumedia Technologies, in 2000, and has developed a handheld educational device for kids, SpeakingPartner, for mass production.His major research interests are the development of fixed-point optimization tools, implementation of VLSI for digital signal processing, and development of multimedia software for handheld devices and VLIW digital signal processors.Youngho Ahn received the B.S. and M.S. degrees in electronic engineering from Seoul National University, Seoul, Korea, in 1997 and 1999 respectively. From 1999 to 2000, he was with Samsung Electronics, Kyunggi-Do, Korea, where he was involved in the ASIC design and development of ATSC digital television receivers. Since 2001, he has been with GCT Semiconductor, Inc., where he works in the communications IC design group. His research interests include wireless communications and ASIC design of communications systems.Eunjoo Hwang was born in Taegu, Korea on April 7, 1974. She received the B.S and M.S degrees in electrical engineering from Seoul National University in 1997 and 1999, respectively. Currently, she works for Silicon Image in Sunnyvale, California, USA as a digital circuit design engineer. Her research interests include blind equalization, joint timing recovery algorithm and storage network design.     

一种用于IC卡的加密算法的VLSI实现

对传输数据进行加密,是提高ＩＣ卡安全性的一个重要手段。文中对一种用于ＩＣ卡芯片的加密算法的ＶＬＳＩ实现进行了研究,并用硬件描述语言ＶＨＤＬ对该算法进行了设计和验证。门级仿真结果表明设计正确。