Impact of nitrogen (N14) implantation into polysilicongate on high-performance dual-gate CMOS transistors

The effect of nitrogen (N₁₄)implant into dual-doped polysilicon gates was investigated. The electrical characteristics of sub-0.25-μm dual-gate transistors (both p- and n-channel), MOS capacitor quasi-static C-V curve, SIMS profile, poly-Si gate R_s , and oxide Q_bd were compared at different nitrogen dose levels. A nitrogen dose of 5×10¹⁵ cm^-2 is the optimum choice at an implant energy of 40 KeV in terms of the overall performance of both p- and n-MOSFETs and the oxide Q_bd. The suppression of boron penetration is confirmed by the SIMS profiles to be attributed to the retardation effect in bulk polysilicon with the presence of nitrogen. High nitrogen dose (1×10¹⁶ cm^-2) results in poly depletion and increase of sheet resistance in both unsilicided and silicided p⁺ poly, degrading the transistor performance. Under optimum design, nitrogen implantation into poly-Si gate is effective in suppressing boron penetration without degrading performance of either p- or n-channel transistors     

Electrical properties of heavily doped polycrystallinesilicon-germanium films

The electrical properties of polycrystalline silicon-germanium (poly-Si_1-xGe_x) films with germanium mole fractions up to 0.56 doped by high-dose ion implantation are presented. The resistivity of heavily doped p-type (P⁺) poly-Si_1-x Ge_x is much lower than that of comparably doped poly-Si, because higher levels of boron activation and higher hole mobilities are achieved in poly-Si_1-xGe_x. The resistivity of heavily doped n-type (N⁺) poly-S_1-xGe_x is similar to that of comparably doped poly-Si for x<0.45; however, it is considerably higher for larger Ge mole fractions due to significant reductions in phosphorus activation. Lower temperatures (~500°C), as well as lower implant doses, are sufficient to achieve low resistivities in boron-implanted poly-Si_1-xGe_x films, compared to poly-Si films. The work function of P⁺ poly-Si_1-xGe_x decreases significantly (by up to ~0.4 Volts), whereas the work function of N⁺ poly-Si_1-xGe_x decreases only slightly, as Ge content is increased. Estimates of the energy bandgap of poly-Si_1-xGe_x show a reduction (relative to the bandgap of poly-Si) similar to that observed for unstrained single-crystalline Si_1-xGe_x for a 26% Ge film, and a reduction closer to that observed for strained single-crystalline Si _1-xGe_x for a 56% Ge film. The electrical properties of poly-Si_1-xGe_x make it a potentially favorable alternative to poly-Si for P⁺ gate-material applications in metal-oxide-semiconductor technologies and also for p-channel thin-film transistor applications     

Observation of reduced boron penetration and gate depletion forpoly-Si0.8Ge0.2 gated PMOS devices

Poly-Si_0.8Ge_0.2-and poly-Si-gated PMOS capacitors with very thin gate oxides were fabricated. Boron penetration and poly-gate depletion effects (PDE) in these devices were both analyzed. Observations of smaller flat-band voltage shift and superior gate oxide reliability suggest less boron penetration problem in poly-Si _0.8Ge_0.2-gated devices. Higher dopant activation rate, higher active dopant concentration near the poly/SiO₂ interface and therefore improved PDE were also found in boron-implanted poly-Si_0.8Ge_0.2-gated devices as compared to poly-Si-gated devices. A larger process window therefore exists for a poly-Si_0.8Ge_0.2 gate technology with regard to the tradeoff between boron penetration and poly-gate depletion     

Impact of boron penetration at P+-poly/gate oxideinterface on deep-submicron device reliability for dual-gate CMOStechnologies

In this paper, we investigate the onset of boron penetration at the P⁺-poly/gate oxide interface. It is found that conventional detection methods such as shifts in flatband voltage or threshold voltage (V_t) and charge-to-breakdown (Q_BD) performance in accumulation mode failed to reveal boron species near this interface. On the contrary, under constant current stressing with inversion mode bias conditions, significantly lower Q_BD and large V_t shift have been observed due to boron penetration near the P⁺-poly/gate oxide interface. These results suggest that onset of boron penetration at the P⁺ -poly/gate oxide interface does not alter fresh device characteristics, but it induces severe reliability degradation for the gate oxide. Tradeoffs of boron penetration and poly depletion are also studied in this work with different combinations of polysilicon thickness, BF₂ implant energy and dose, and the post-implant RTA temperature     

Suppression of boron penetration through thin gate oxides by nitrogen implantation into the gate electrode in PMOS devices

PMOS devices with and without nitrogen implant into the gate electrode before doping with boron and with nitridation of the gate oxide were manufactured. The influence of nitrogen on the penetration of boron ions into the substrate through ultra-thin gate oxides was investigated by electrical and SIMS measurements. Boron diffusion can be effectively prevented by high nitrogen concentrations located immediately above the gate oxide and within the polysilicon gate electrode.     

Improvement in threshold voltage control by minimizing boronpenetration in a LV-GCMOS technology

Maintaining tight threshold voltage (V_T) control for a low-voltage CMOS process is critical due to the large impact of V_T on circuit performance at low power supply voltages. In this paper, PMOS V_T was shown to be sensitive to poly gate thickness and BF₂⁺ source/drain implant energy. This data helped identify boron penetration as a prime contributor to PMOS threshold voltage variation. SIMS measurements were used to investigate boron diffusion through the poly gate at various stages in the process flow. These SIMS profiles pointed to the low-temperature thermal cycle of the nitride spacer deposition as a key step which influenced the amount of boron penetration and thus the final device threshold voltage. Experimental evidence shows that the temperature gradient across the nitride spacer deposition furnace causes a variable amount of boron penetration resulting in a large variation in PMOS V_T. We adopted a process flow change which virtually eliminated boron penetration and significantly reduced the sensitivity of the devices to manufacturing variations. Threshold voltage variation was reduced by a factor of two     

Electrical characteristics of rapid thermal nitrided-oxide gate n and p-MOSFET's with less than 1 atom% nitrogen concentration

The characteristics and reliability of nitrided-oxide gate n- and p-MOSFET's with less than 1 atom% nitrogen concentration in the gate films were investigated in detail. These very light nitridations were accomplished using NH₃ gas at low temperatures-from 800° C to 900° C. Nitrogen concentrations as low as 0.13 atom% were successfully measured by SIMS and AES. The region of optimum nitrogen concentration for deep-submicron devices is discussed. We explain how good drivability and good hot-carrier reliability were attained simultaneously with a nitrogen concentration of around 0.5 atom%, which is equivalent to that of oxynitride gate MOSFETs using N₂O gas. The suppression of boron penetration is also discussed. Light nitridation by ammonia gas is particularly desirable for deep-submicron processes because it can be accomplished at a relatively low temperature of about 900°C     

The effects of boron penetration on p+ polysilicon gatedPMOS devices

The penetration of boron into and through the gate oxides of PMOS devices which employ p⁺ doped polysilicon gates is studied. Boron penetration results in large positive shifts in V_FB , increased PMOS subthreshold slope and electron trapping rate, and decreased low-field mobility and interface trap density. Fluorine-related effects caused by BF₂ implantations into the polysilicon gate are shown to result in PMOS threshold voltage instabilities. Inclusion of a phosphorus co-implant or TiSi₂ salicide prior to gate implantation is shown to minimize this effect. The boron penetration phenomenon is modeled by a very shallow, fully-depleted p-type layer in the silicon substrate close to the SiO ₂/Si interface     

A variable-work-function polycrystalline-Si1-xGex gate material for submicrometer CMOS technologies

P⁺ poly-Si_1-xGe_x is a promising candidate for the gate material in submicrometer CMOS technologies due to its improved resistivity and its work function (which can be modified to achieve more-scalable NMOS and PMOS devices). The work function of P ⁺ poly-Si_1-xGe_x decreases with increasing Ge content, by more than 0.3 V from 0 to 60%. Because of its ease of formation and compatibility with VLSI fabrication techniques, assimilating poly-Si_1-xGe_x into an existing CMOS process should be relatively simple     

Suppression of boron penetration through thin gate oxides by nitrogen implantation into the gate electrode of PMOS devices

PMOS devices with different amounts of nitrogen implanted into the gate electrode before doping with BF₂ implantation and implant anneal were manufactured. The thicknesses of the gate oxides grown in dry oxygen by RTP were 4.1 down to 2.8 nm. The implant anneal was also performed by RTP. The influence of the nitrogen on the penetration of boron ions through the ultra-thin gate oxides into the channel region was investigated by electrical and SIMS measurements. Boron was effectively prevented from diffusion by high nitrogen concentrations at the polysilicon/gate oxide interface without degrading the reliability. In return, increased sheet resistivities and gate depletion have to be taken into account by high nitrogen concentrations within the polysilicon gate electrode.     

The effect of fluorine from BF2 source/drain extensionimplants on performance of PMOS transistors with thin gate oxides

Boron penetration from the gate electrode into the Si substrate presents a significant problem in advanced PMOS device fabrication. Boron penetration, which causes a degradation of many transistor parameters, is further enhanced when BF₂ is used to dope the gate electrode. It is known that pile-up of fluorine from the BR gate implant at the polysilicon/gate oxide interface is responsible for the enhanced boron penetration. However, no reports have been made that address enhanced boron penetration due to fluorine from the source/drain (S/D) implants. It is shown here that fluorine from the S/D extension implants is also a significant problem, degrading transistor performance for gate oxide thickness less than 27 Å and gate lengths less than 0.5 μm     

氮注入多晶硅栅对超薄SiO_2栅介质性能的影响

p+ 多晶硅栅中的硼在 Si O2 栅介质中的扩散会引起栅介质可靠性退化 ,在多晶硅栅内注入 N+ 的工艺可抑制硼扩散 .制备出栅介质厚度为 4 .6 nm的 p+栅 MOS电容 ,通过 SIMS测试分析和 I- V、C- V特性及电应力下击穿特性的测试 ,观察了多晶硅栅中注 N+工艺对栅介质性能的影响 .实验结果表明 :在多晶硅栅中注入氮可以有效抑制硼扩散 ,降低了低场漏电和平带电压的漂移 ,改善了栅介质的击穿性能 ,但同时使多晶硅耗尽效应增强、方块电阻增大 ,需要折衷优化设计 .     

Thickness dependence of boron penetration through O2 and N2O-grown gate oxides and its impact on threshold voltagevariation

We report on a quantitative study of boron penetration from p⁺ polysilicon through 5- to 8-nm gate dielectrics prepared by rapid thermal oxidation in O₂ or N₂O. Using MOS capacitor measurements, we show that boron penetration exponentially increases with decreasing oxide thickness. We successfully describe this behavior with a simple physical model, and then use the model to predict the magnitude of boron penetration, N_B, for thicknesses other than those measured. We find that the minimum t_ox required to inhibit boron penetration is always 2-4 nm less when N₂O-grown gate oxides are used in place of O₂- grown oxides. We also employ the boron penetration model to explore the conditions under which boron-induced threshold voltage variation can become significant in ULSI technologies. Because of the strong dependence of boron penetration on t_ox, incremental variations in oxide thickness result in a large variation in N_B , leading to increased threshold voltage spreading and degraded process control. While the sensitivity of threshold voltage to oxide thickness variation is normally determined by channel doping and the resultant depletion charge, we find that for a nominal thickness of 6 nm, threshold voltage control is further degraded by penetrated boron densities as low as 10¹¹ cm^-2     

A comprehensive study on p+ polysilicon-gate MOSFET'sinstability with fluorine incorporation

It is reported that fluorine can jeopardize p⁺-gate devices under moderate annealing temperatures. MOSFETs with BF₂ or boron-implanted polysilicon gates were processed identically except at gate implantation. Evidence of boron penetration through 12.5-nm oxide and a large quantity of negative charge penetration (10 ¹² cm^-2) by fluorine even at moderate annealing conditions is reported. The degree of degradation is aggravated as fluorine dose increases. A detailed examination of the I-V characteristics of PMOSFET with fluorine incorporated p⁺-gate revealed that the long gate-length device had abnormal abrupt turn-on I_d-V_g characteristics, while the submicrometer-gate-length devices appeared to be normal. The abnormal turn-on I_d-V_g characteristics associated with long-gate-length p⁺-gate devices vanished when the device was subjected to X-ray irradiation and/or to a high-voltage DC stressing at the source/drain. The C-V characteristics of MOS structures of various gate dopants, processing ambients, doping concentrations, and annealing conditions were studied. Based on all experimental results, the degradation model of p⁺-gate devices is presented. The incorporation of fluorine in the p⁺ gate enhances boron penetration through the thin gate oxide into the silicon substrate and creates negative-charge interface states. The addition of H/OH species into F-rich gate oxide will further aggravate the extent of F-enhanced boron penetration by annealing out the negative-charge interface states     

Argon ion-implantation on polysilicon or amorphous-silicon forboron penetration suppression in p+ pMOSFET

In this paper, a technique to use Ar ion-implantation on the p⁺α-Si or poly-Si gate to suppress the boron penetration in p⁺ pMOSFET is proposed and demonstrated. An Ar-implantation of a dose over 5×10¹⁵ cm^-2 is shown to be able to sustain 900°C annealing for 30 min for the gate without having the underlying gate oxide quality degraded. It is believed to be due to gettering of fluorine, then consequently boron, by the bubble-like defects created by the Ar implantation in the p⁺ gate region to reduce the B penetration. Excellent electrical characteristics like dielectric breakdown (E_bd), interface state density (D_it), and charge-to-breakdown (Q_bd) on the gate oxide are obtained. The technique is compatible to the present CMOS process. The submicron pMOSFET fabricated by applying this technique exhibit better subthreshold characteristics and hot carrier immunity     

Suppression of the boron penetration induced dielectric degradationby using a stacked-amorphous-silicon film as the gate structure forpMOSFET

This work proposes a stacked-amorphous-silicon (SAS) film as the gate structure of the p⁺ poly-Si gate pMOSFET to suppress boron penetration into the thin gate oxide. Due to the stacked structure, a large amount of boron and fluorine piled up at the stacked-Si layer boundaries and at the poly-Si/SiO₂ interface during the annealing process, thus the penetration of boron and fluorine into the thin gate oxide is greatly reduced. Although the grain size of the SAS film is smaller than that of the as deposited polysilicon (ADP) film, the boron penetration can be suppressed even when the annealing temperature is higher than 950°C. In addition, the mobile ion contamination can be significantly reduced by using this SAS gate structure. This results in the SAS gate capacitor having a smaller flat-band voltage shift, a less charge trapping and interface state generation rate, and a larger charge-to-breakdown than the ADP gate capacitor. Also the Si/SiO₂ interface of the p⁺ SAS gate capacitor is much smoother than that of the p⁺ SAS gate capacitor     

Suppression of boron penetration in p+ polysilicon gateP-MOSFETs using low-temperature gate-oxide N2O anneal

It has been reported that high-temperature (~1100°C) N₂ O-annealed oxide can block boron penetration from poly-Si gates to the silicon substrate. However, this high-temperature step may be inappropriate for the low thermal budgets required of deep-submicron ULSI MOSFETs. Low-temperature (900~950°C) N₂O-annealed gate oxide is also a good barrier to boron penetration. For the first time, the change in channel doping profile due to compensation of arsenic and boron ionized impurities was resolved using MOS C-V measurement techniques. It was found that the higher the nitrogen concentration incorporated at Si/SiO₂ interface, the more effective is the suppression of boron penetration. The experimental results also suggest that, for 60~110 Å gate oxides, a certain amount of nitrogen (~2.2%) incorporated near the Si/SiO₂ interface is essential to effectively prevent boron diffusing into the underlying silicon substrate     

Flatband voltage shift in PMOS devices caused by carrier activationin p+-polycrystalline silicon and by boron penetration

After discovering that the annealing-time dependence of the flatband voltage shifts of a p⁺-polysilicon gate MOS diode can be attributed to boron activation in polysilicon instead of boron penetration through gate M₂, we proposed a boron activation model for polysilicon in which the carrier activation is related to the grain size of the polysilicon. Using this model, we analyzed the characteristics of pMOSFETs with polysilicon gates of different grain sizes and found that they depend on the grain size, as expected. Using the model, we quantitatively identified process windows for p⁺-polysilicon gate pMOSFETs, assuming that enough boron is activated in the polysilicon without the boron penetrating through the gate SiO₂     

Optimization of gate oxide N2O anneal for CMOSFET's atroom and cryogenic temperatures

This paper presents a study of the impact of gate-oxide N₂ O anneal on CMOSFET's characteristics, device reliability and inverter speed at 300 K and 85 K. Two oxide thicknesses (60 and 110 Å) and five N₂O anneal conditions (900~950°C, 5~40 min) plus nonnitrided process and channel lengths from 0.2 to 2 μm were studied to establish the correlation between the nitrogen concentration at Si/SiO₂ interface and the relative merits of the resultant devices. We concluded that one simple post-oxidation N₂O anneal step can increase CMOSFET's lifetime by 4~10 times, effectively suppress boron penetration from the P⁺ poly-Si gate of P-MOSFET's without sacrificing CMOS inverter speed. We also found that the benefits in terms of the improved interface hardness and charge trapping characteristic still exist at cryogenic temperature. All these improvements are found to be closely correlated to the nitrogen concentration incorporated at the Si/SiO₂ interface. The optimal N₂O anneal occurs somewhere at around 2% of nitrogen incorporation at Si/SiO₂ interface which can be realized by annealing 60~110 Å oxides at 950°C for 5 min or 900°C for 20 min     

Fluorine diffusion on a polysilicon grain boundary network inrelation to boron penetration from P+ gates

The combined effect of boron penetration and fluorine transport from P⁺ polycrystalline gates on flat-band voltage is studied. The SIMS concentration depth profiles elucidate the effect of annealing temperature on the fluorine transport, which in turn affects the boron penetration induced change in flat-band voltage. The fluorine diffusion in the poly gate is dominated by grain boundary diffusion. The identification of this mechanism is supported by SIMS profiles and a simulation based on a new methodology of network diffusion