A High-Voltage DC–DC Converter With Vin/3—Voltage Stress on the Primary Switches

A high-voltage dc-dc converter with low voltage stress on the power switches and high output current capacity is presented. This converter exhibits three distinct features. First, the voltage stress on the primary switches is only one-third of the input voltage, so that switches of low voltage rating and thus of low on-resistance can be used. This leads to reduced conduction loss. Second, all the switches are soft-switched, so that the switching loss can be reduced. Third, the rectifier is a current tripler, so that the output current capacity, and thus the power handling capacity of the converter are increased. A 5.1-kW, 1000-V/48-V dc-dc converter prototype has been built and tested. Experimental results are favorably compared with theoretical predictions.     

Coupled Input-Series and Output-Parallel Dual Interleaved Flyback Converter for High Input Voltage Application

This paper proposes an integrated magnetic dc-dc converter suitable for high input voltage application. The converter is based on a coupled input-series and output-parallel dual interleaved Flyback converter concept. All the center and outer legs are gapped, and the transformers are integrated into one magnetic core with not so tight coupling. The gap is beneficial for suppressing current spike caused by the voltage mismatch between the windings. The two transformers are inversely coupled, and current ripple reduction can be achieved with suitable coupling design. A prototype with 350-450-V input and 24-V/4-A output is built. Experimental results verify the performance of the new topology.     

Development of a low cost fuel cell inverter system with DSP control

In this paper, the development of a low cost fuel cell inverter system is detailed. The approach consists of a three-terminal push-pull dc-dc converter to boost the fuel cell voltage (48V) to /spl plusmn/200 VDC. A four switch [insulated gate bipolar transistor (IGBT)] inverter is employed to produce 120-V/240-V, 60-Hz ac outputs. High performance, easy manufacturability, lower component count, safety and cost are addressed. Protection and diagnostic features form an important part of the design. Another highlight of the proposed design is the control strategy, which allows the inverter to adapt to the requirements of the load as well as the power source (fuel cell). A unique aspect of the design is the use of the TMS320LF2407 DSP to control the inverter. Two sets of lead-acid batteries are provided on the high voltage dc bus to supply sudden load demands. Efficient and smooth control of the power drawn from the fuel cell and the high voltage battery is achieved by controlling the front end dc-dc converter in current mode. The paper details extensive experimental results of the proposed design on Department of Energy (DoE) National Energy Technology Laboratory (NETL) fuel cell.     

A Bidirectional DC–DC Converter for an Energy Storage System With Galvanic Isolation

This paper addresses a bidirectional dc-dc converter suitable for an energy storage system with an additional function of galvanic isolation. An energy storage device such as an electric double layer capacitor is directly connected to a dc side of the dc-dc converter without any chopper circuit. Nevertheless, the dc-dc converter can continue operating when the voltage across the energy storage device drops along with its discharge. Theoretical calculation and experimental measurement reveal that power loss and peak current impose limitations on a permissible dc-voltage range. This information may be useful in design of the dc-dc converter. Experimental results verify proper charging and discharging operation obtained from a 200-V, 2.6-kJ laboratory model of the energy storage system. Moreover, the dc-dc converter can charge the capacitor bank from zero to the rated voltage without any external precharging circuit.     

Low Profile Integratable Inductor Fabricated Based on LTCC Technology for Microprocessor Power Delivery Applications

A novel low profile power inductor suitable for planar integration is designed and fabricated based on low temperature co-fired ceramics technology for microprocessor power delivery applications. The inductor was designed to operate at a switching frequency of 4 to 5MHz, carrying a nominal dc current of 20A with a ripple current of 8 to 10A in a 5-V to 1-V dc-dc converter. The design and fabrication procedure is discussed in this paper, followed by small signal measurement and magnetic characterization results. The inductor was implemented in a prototype converter and the large signal measurement results are presented and its performance evaluated     

A New Approach to Reducing Output Ripple in Switched-Capacitor-Based Step-Down DC–DC Converters

Rapidly dropping power supply voltages and tight voltage regulation requirements for integrated circuits challenges power supply designers. A novel interleaved discharging (ID) approach is presented to reduce the output ripple in step-down switched-capacitor (SC) dc-dc converters. Simulation and experimental results of a four-stage SC dc-dc converter show that the ID approach can reduce the output ripple by a factor of three. The proposed approach also improves the converter efficiency by 7%. The ID method provides flexibility in the design optimization of step-down SC dc-dc converters     

A Multistage Interleaved Synchronous Buck Converter With Integrated Output Filter in 0.18 μm SiGe Process

The design and analysis of a fully integrated multistage interleaved synchronous buck dc-dc converter with on-chip filter inductor and capacitor is presented. The dc-dc converter is designed and fabricated in 0.18 mum SiGe RF BiCMOS process technology and generates 1.5 V-2.0 V programmable output voltage supporting a maximum output current of 200 mA. High switching frequency of 45 MHz, multiphase interleaved operation, and fast hysteretic controller reduce the filter inductor and capacitor sizes by two orders of magnitude compared to state-of-the-art converters and enable a fully integrated converter. The fully integrated interleaved converter does not require off-chip decoupling and filtering and enables direct battery connection for integrated applications. This design is the first reported fully integrated multistage interleaved, zero voltage switching synchronous buck converter with monolithic output filters. The fully integrated buck regulator achieves 64% efficiency while providing an output current of 200 mA.     

Low cost fuel cell converter system for residential power generation

The high installation cost is the major obstacle of the commercialization of the solid oxide fuel cell for distributed power generation. This paper presents a new low cost 10-kW converter system to overcome this obstacle. The proposed system consists of an isolated dc-dc converter to boost the fuel cell voltage to 400 V dc and a pulse-width modulated inverter with filter to convert the dc voltage to two split-phase 120-V ac. The dc-dc converter uses phase shifting to control power flow through a transformer with a metal oxide semiconductor field effect transistor full bridge on the low voltage side and a voltage doubler on the high voltage side. One IPM is used to realize the voltage doubler and the dc-ac inverter. Compared to the existing fuel cell converter systems, the proposed circuit has low cost, less component count, smaller size, and reduced dc-dc converter peak current. Simulation and experimental results are demonstrated.     

Current-Fed Dual-Bridge DC–DC Converter

A new isolated current-fed pulsewidth modulation dc-dc converter-current-fed dual-bridge dc-dc converter-with small inductance and no deadtime operation is presented and analyzed. The new topology has more than 3times smaller inductance than that of current-fed full-bridge converter, thus having faster transient response speed. Other characteristics include simple self-driven synchronous rectification, simple housekeeping power supply, and smaller output filter capacitance. Detailed analysis shows the proposed converter can have either lower voltage stress on all primary side power switches or soft switching properties when different driving schemes are applied. A 48-V/125-W prototype dc-dc converter with dual output has been tested for the verification of the principles. Both simulations and experiments verify the feasibility and advantages of the new topology     

A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package

We demonstrate an integrated buck dc-dc converter for multi-V/sub CC/ microprocessors. At nominal conditions, the converter produces a 0.9-V output from a 1.2-V input. The circuit was implemented in a 90-nm CMOS technology. By operating at high switching frequency of 100 to 317 MHz with four-phase topology and fast hysteretic control, we reduced inductor and capacitor sizes by three orders of magnitude compared to previously published dc-dc converters. This eliminated the need for the inductor magnetic core and enabled integration of the output decoupling capacitor on-chip. The converter achieves 80%-87% efficiency and 10% peak-to-peak output noise for a 0.3-A output current and 2.5-nF decoupling capacitance. A forward body bias of 500 mV applied to PMOS transistors in the bridge improves efficiency by 0.5%-1%.     

An Improved Topology of SEPIC Converter With Reduced Output Voltage Ripple

An improved version of a single-ended primary inductor converter (SEPIC) is presented. The converter consists of a conventional SEPIC converter plus an additional high-frequency transformer and diode to maintain a freewheeling mode of the dc inductor currents during the switch on state. The voltage conversion ratio characteristics and semiconductor device voltage and current stresses are characterized. The main advantages of this converter are the continuous output current, smaller output voltage ripple, and lower semiconductors current stress compared with the conventional SEPIC converter. The design and simulation of the concept is verified by an experiment with a 48-V input and 12-V/3.75-A output converter.      

An integrated one-cycle control buck converter with adaptive output and dual loops for output error correction

An integrated adaptive-output switching converter is presented. This converter adopts one-cycle control for fast line response and dual error correction loops for tight load regulation. A dc level shifting technique is proposed to eliminate the use of negative supply and reference voltages in the controller and make the design compatible with standard digital CMOS process. The design accommodates both continuous and discontinuous conduction operations. To further enhance the efficiency, dynamic loss control on the power transistors is proposed to minimize the sum of switching and conduction losses. The design can be extended to other dc-dc and ac-dc conversions. The prototype of the buck converter was fabricated with a standard 0.5-/spl mu/m digital CMOS process. Experimental results show that the converter is well regulated over an output range of 0.9-2.5 V, with a supply voltage of 3.3 V. The tracking speeds are 12.25 /spl mu/s/V for a 1.6-V step-up output change and 13.75 /spl mu/s/V for a 1.6-V step-down output change, respectively, which are much faster than existing counterparts. Maximum efficiency of 93.7% is achieved and high efficiency above 75% is retained over an output power ranging from 10 to 450 mW.     

Interleaved ZVS Converter With Ripple-Current Cancellation

In this paper, an interleaved soft-switching converter with ripple-current cancellation is presented to achieve zero- voltage-switching (ZVS) turn-on and load current sharing. In order to achieve ZVS turn-on, an active snubber is connected in parallel with the primary winding of the transformer. The energy stored in the transformer leakage inductance and magnetizing inductance can be recovered so that the peak voltage stress of switching devices is limited. The resonance at the transition interval is used to realize ZVS turn-on of all switches. In order to achieve three-level pulsewidth-modulation (PWM) scheme, an addition fast-recovery diode is used in the converter. Three-level PWM scheme can reduce the ac ripple current on the output inductor such that the output inductor can be reduced. The current-doubler rectifier is adopted in the secondary side of the transformer to reduce the transformer secondary-winding current and output voltage ripple by canceling the current ripple of two output inductors. The output voltage is controlled at the desired value using the interleaved PWM scheme. These features make the proposed converter suitable for the dc-dc converter with high output current. The operation principles, steady state analysis, and design equations of the proposed converter are provided in detail. Finally, experiments based on a 600-W (12 V/50 A) prototype are provided to verify the effectiveness and feasibility of the proposed converter.     

A Two-Point Modulation Technique for CMOS Power Amplifier in Polar Transmitter Architecture

A two-point modulation technique is presented that improves the performance of nonlinear power amplifiers (PAs) in polar transmitters. In this scheme, the output amplitude modulation is performed by controlling the current of the PA. The current control technique enables the PA to provide wideband amplitude modulation, as well as high power control dynamic range. In addition, the supply voltage of the PA is adjusted based on the output power level. The voltage supply adjustment substantially improves the effective power efficiency of the PA. The voltage supply control is performed using a second-order sigma-delta dc-dc converter, which presents an efficiency of over 95% in its operational range. The PA operates at 900 MHz with maximum output power of 27.8 dBm and power efficiency of 34% at maximum output power. The proposed PA achieves 62-dB power control dynamic range with amplitude modulation bandwidth of over 17.1 MHz. The circuits are fabricated in a CMOS 0.18 mum process with a 3.3-V power supply.     

A novel self-oscillating, boost-derived DC-DC converter with load regulation

This paper proposes a novel self-oscillating, boost-derived (SOBD) dc-dc converter with load regulation. This proposed topology utilizes saturable cores (SCs) to offer self-oscillating and output regulation capabilities. Conventionally, the self-oscillating dc transformer (SODT) type of scheme can be implemented in a very cost-effective manner. The ideal dc transformer provides both input and output currents as pure, ripple-free dc quantities. However, the structure of an SODT-type converter will not provide regulation, and its oscillating frequency will change in accordance with the load. The proposed converter with SCs will allow output-voltage regulation to be accomplished by varying only the control current between the transformers, as occurs in a pulse-width modulation (PWM) converter. A control network that combines PWM schemes with a regenerative function is used for this converter. The optimum duty cycle is implemented to achieve low levels of input- and output-current ripples, which are characteristic of an ideal dc transformer. The oscillating frequency will spontaneously be kept near-constant, regardless of the load, without adding any auxiliary or compensation circuits. The typical voltage waveforms of the transistors are found to be close to quasisquare. The switching surges are well suppressed, and the voltage stress of the component is well clamped. The turn-on/turn-off of the switch is zero-voltage switching (ZVS), and its resonant transition can occur over a wide range of load current levels. A prototype circuit of an SOBD converter shows 86% efficiency at 48-V input, with 12-V, 100-W output, and presents an operating frequency of 100 kHz.     

Analysis and Implementation of a High Efficiency, Interleaved Current-Fed Full Bridge Converter for Fuel Cell System

An interleaved current-fed full bridge (ICFFB) dc-dc converter is proposed in this paper that has low input current ripple to meet the fuel cell demands. By interleaving two isolated CFFB converters with parallel input and series output connection, both input current ripple and output voltage ripple can be reduced. In addition, the size of the magnetic components and current stress of the semiconductor devices on the input side are also reduced. Similarly, smaller voltage rating components can be used on the output side. Only one digital signal processor microcontroller is used to generate phase-shifted gate signals and to implement a cascaded digital control system. The main features of the proposed converter are high efficiency, small passive component size, and small input current ripple. Experimental results for a 1.2-kW interleaved CFFB converter are provided in the paper     

Digital Predictive Feed-Forward Controller for a DC–DC Converter in Plasma Display Panel

This paper describes a new digital control method to enhance the dynamic performance of a dc-dc converter used in plasma display panel (PDP). A simple digital PID compensator with duty ratio feed-forward control is proposed to minimize the output voltage variation while the load current is continuously changing. The duty ratio feed-forward is calculated using noise-free load current information which is predicted by the available video data of the PDP. No separate current sensing circuit is required. A small signal z-domain feed-forward model is derived for the performance analysis and controller design. The proposed control method is experimentally verified on an asymmetrical half bridge dc-dc converter which supplies power to a 42 in PDP.     

Voltage loop of boost PWM DC-DC converters with peak current-mode control

A new transfer function from control voltage to duty cycle, the closed-current loop, which captures the natural sampling effect is used to design a controller for the voltage-loop of a pulsewidth modulated (PWM) dc-dc converter operating in continuous-conduction mode (CCM) with peak current-mode control (PCM). This paper derives the voltage loop gain and the closed-loop transfer function from reference voltage to output voltage. The closed-loop transfer function from the input voltage to the output voltage, or the closed-loop audio-susceptibility is derived. The closed-loop transfer function from output current to output voltage, or the closed loop output impedance is also derived. The derivation is performed using an averaged small-signal model of the example boost converter for CCM. Experimental verification is presented. The theoretical and experimental results were in good agreement, confirming the validity of the transfer functions derived.     

The fast response double buck DC-DC converter (FRDB): operation and output filter influence

The fast response double buck (FRDB) dc-dc converter was presented like a low output voltage dc-dc converter with fast transient response, in order to feed devices such as microprocessors and digital signal processors (DSPs). The topology of the FRDB is composed of two buck converters connected in parallel, each one of them with different features and aims, and controlled by means of the novel linear-non-linear (LnL) control. In this paper, the topology, the control strategy and the operation principle are shown. Finally, experimental results in different prototypes are presented to show both, the transient response and the recovery time when these prototypes are subjected to load current steps, and the influence of the output filter on these parameters.     

Dual-Mode Multiple-Band Digital Controller for High-Frequency DC–DC Converter

An integrated digital controller design for dc-dc converter is proposed in this paper. The proposal presents a multiple- band dual-stage (MBDS) delay line A/D converter (ADC) for wide dynamic range of operation with reduced ripple, chip area, and power consumption. This proposal also introduces a novel folding logic for digital error calculation and dual-mode error control PID for improving transient response. A complete closed-loop experimental prototype is demonstrated on a field-programmable-gate- array-based setup. The feasibility and functionality of the proposed digital controller is verified with a closed-loop synchronous buck converter prototype that switches at 1 MHz and regulates over a wide output voltage range of 1.6-3.3 V. The proposed MBDS delay line ADC is fabricated with discrete logic gates and flip-flops. The integrated digital controller is also implemented using standard cell-based design methodology in 0.5-mum CMOS technology. The design reduces 33 % on-chip area compared to an equivalent of 64 tap delay line ADC. The complete digital controller chip takes less than 0.7 mm² of silicon area and consumes an average current of 92 muA at 1-MHz switching frequency. The voltage-mode digital loop achieves tracking time of less than 10 mus for 1-V step change of the reference voltage and settling time of 20 mus. Post layout simulation and experimental results are demonstrated.