220GHz低噪声放大器研究

基于IHP锗硅BiCMOS工艺,研究和实现了两种220 GHz低噪声放大器电路,并将其应用于220 GHz太赫兹无线高速通信收发机电路。一种是220 GHz四级单端共基极低噪声放大电路,每级电路采用了共基极（Common Base, CB）电路结构,利用传输线和金属-绝缘体-金属(Metal-Insulator-Metal, MIM)电容等无源电路元器件构成输入、输出和级间匹配网络。该低噪放电源的电压为1.8 V,功耗为25 mW,在220 GHz频点处实现了16 dB的增益,3 dB带宽达到了27 GHz。另一种是220 GHz四级共射共基差分低噪声放大电路,每级都采用共射共基的电路结构,放大器利用微带传输线和MIM电容构成每级的负载、Marchand-Balun、输入、输出和级间匹配网络等。该低噪放电源的电压为3 V,功耗为234 mW,在224 GHz频点实现了22 dB的增益,3 dB带宽超过6 GHz。这两个低噪声放大器可应用于220 GHz太赫兹无线高速通信收发机电路。     

A 5-GHz CMOS wireless LAN receiver front end

This paper presents a 12.4-mW front end for a 5-GHz wireless LAN receiver fabricated in a 0.24-μm CMOS technology. It consists of a low-noise amplifier (LNA), mixers, and an automatically tuned third-order filter controlled by a low-power phase-locked loop. The filter attenuates the image signal by an additional 12 dB beyond what can be achieved by an image-reject architecture. The filter also reduces the noise contribution of the cascode devices in the LNA core. The LNA/filter combination has a noise figure of 4.8 dB, and the overall noise figure of the signal path is 5.2 dB. The overall IIP3 is -2 dBm     

Millimeter-wave wide-band amplifiers using multilayer MMICtechnology

This paper describes millimeter-wave wide-band single-ended and balanced amplifiers using novel multilayer monolithic microwave/millimeter-wave integrated circuit (MMIC) technology. The fundamental characteristics of thin-film transmission lines and a 50-GHz-band multilayer MMIC directional coupler are described through measurements up to 60 GHz. A single-ended amplifier fabricated in a 1.1 mm×0.8 mm area, shows a gain of about 12 dB with a noise figure of better than 5 dB around 50 GHz. A balanced amplifier fabricated using the multilayer MMIC directional couplers and single-ended amplifiers, shows a gain of 10-17 dB with input and output return losses of better than 14 dB from 33 to 53 GHz. The transmission lines and directional couplers can be effectively combined with millimeter-wave active circuits without degrading the circuit performance or increasing the circuit area. To our knowledge, these are the first millimeter-wave active circuits employing multilayer MMIC technology     

应用于802.11b无线局域网的低噪声高线性度的CMOS射频接收机

实现了一个单片集成、直接转换结构的2.4GHz CMOS接收机. 这个正交接收机作为低成本方案应用于802.11b无线局域网系统,所处理的数据传输率为该系统的最大速率--11Mbps. 基于系统设计以及低噪声高线性度考虑,设计了低噪声放大器、直接转换混频器、增益可变放大器、低通滤波器、直流失调抵消电路及其他辅助电路. 该芯片采用中芯国际0.18μm 1p6m RF CMOS工艺流片,所测的接收机性能如下：噪声系数为4.1dB,高增益设置下低噪声放大器与混频器的输入三阶交调点为-7.5dBm,整个接收机的输入三阶交调点为-14dBm,相邻信道干扰抑制能力在距中心频率30MHz处达到53dBc,输出直流失调电压小于5mV. 该接收机采用1.8V电源电压,I, Q两路消耗的总电流为44mA.     

A Zero-IF 60 GHz 65 nm CMOS Transceiver With Direct BPSK Modulation Demonstrating up to 6 Gb/s Data Rates Over a 2 m Wireless Link

This paper presents a directly modulated, 60 GHz zero-IF transceiver architecture suitable for single-carrier, low-power, multi-gigabit wireless links in nanoscale CMOS technologies. This mm-wave front end architecture requires no upconversion of the baseband signals in the transmitter and no analog-to-digital conversion in the receiver, thus minimizing system complexity and power consumption. All circuit blocks are realized using sub-1.0 V topologies, that feature only a single high-frequency transistor between the supply and ground, and which are scalable to future 45 nm, 32 nm, and 22 nm CMOS nodes. The transceiver is fabricated in a 65 nm CMOS process with a digital back-end. It includes a receiver with 14.7 dB gain and 5.6 dB noise figure, a 60 GHz LO distribution tree, a 69 GHz static frequency divider, and a direct BPSK modulator operating over the 55–65 GHz band at data rates exceeding 6 Gb/s. With both the transmitter and the receiver turned on, the chip consumes 374 mW from 1.2 V which reduces to 232 mW for a 1.0 V supply. It occupies 1.28$,times,$0.81 mm$^{2}$. The transceiver and its building blocks were characterized over temperature up to 85$^{circ}$ C and for power supplies down to 1 V. A manufacturability study of 60 GHz radio circuits is presented with measurements of transistors, the low-noise amplifier, and the receiver on slow, typical, and fast process splits. The transceiver architecture and performance were validated in a 1–6 Gb/s 2-meter wireless transmit-receive link over the 55–64 GHz range.      

3GHz低功耗低相位噪声的带自偏置电流源的LC压控振荡器

利用0.18μm CMOS工艺实现了一个全集成的工作于3GHz的低功耗、低相位噪声的压控振荡器,且带有自偏置电流源.通过对改进的电流源进行优化,在噪声与功耗之间达到了折中.该压控振荡器可工作于2.83至3.25GHz频段内,调谐范围达到13.8%.当工作于3.22GHz时,测得的相位噪声在1MHz频偏处为-111dBc/Hz.在1.8V电源电压下,核心模块消耗电流小于2mA.表明该电路适合5GHz的无线局域网接收机以及3.4至3.6GHz的全球微波互联接入(WiMAX)应用.     

Low-power transceiver analog front-end circuits for bidirectional high data rate wireless telemetry in medical endoscopy applications

State-of-the-art endoscopy systems require electronics allowing for real-time, bidirectional data transfer. Proposed are 2.4-GHz low-power transceiver analog front-end circuits for bidirectional high data rate wireless telemetry in medical endoscopy applications. The prototype integrates a low-IF receiver analog front-end [low noise amplifier (LNA), double balanced down-converter, bandpass-filtered automatic gain controlled (AGC) loop and amplitude-shift keying (ASK) demodulator], and a direct up-conversion transmitter analog front-end [20-MHz IF phase-locked loop (PLL) with well-defined amplitude control circuit, ASK modulator, up-converter, and power amplifier] on a single chip together with an internal radio frequency oscillator and local oscillating (LO) buffers. Design tradeoffs have been made over the boundaries of the different building blocks to optimize the overall system performance. All building blocks feature circuit topologies that enable comfortable operation at low power consumption. The circuits have been implemented in a 0.25-microm CMOS process. The measured sensitivity of the receiver analog front-end is -70 dBm with a data rate of 256 kbps, and the measured output power of the transmitter analog front-end could achieve -23 dBm with a data rate of 1 Mbps. The integrated circuit consumes a current of 6 mA in receiver mode and 5.6 mA in transmitter mode with a power supply of 2.5 V. This paper shows the feasibility of achieving the analog performance required by the wireless endoscopy capsule system in 0.25 microm CMOS.     

应用于802.11b无线局域网的低噪声高线性度的CMOS射频接收机

实现了一个单片集成、直接转换结构的2.4GHz CMOS接收机.这个正交接收机作为低成本方案应用于802.11b无线局域网系统,所处理的数据传输率为该系统的最大速率--11Mbps.基于系统设计以及低噪声高线性度考虑,设计了低噪声放大器、直接转换混频器、增益可变放大器、低通滤波器、直流失调抵消电路及其他辅助电路.该芯片采用中芯国际0.18μm 1p6m RF CMOS工艺流片.所测的接收机性能如下:噪声系数为4.1dB,高增益设置下低噪声放大器与混频器的输入三阶交调点为-7.5dBm,整个接收机的输入三阶交调点为-14dBm,相邻信道干扰抑制能力在距中心频率30MHz处达到53dBc,输出直流失调电压小于5mV.该接收机采用1.8V电源电压,I,Q两路消耗的总电流为44mA.     

一种适用于5G通信的分布式低噪声放大器

宽带低噪声放大器是5G无线通信系统中的关键模块。针对6 GHz以下5G通信应用频段,基于65 nm CMOS工艺,设计了一种三级均匀分布式宽带低噪声放大器。在增益单元电路中,采用噪声抵消技术降低了噪声,同时实现了信号的单转双变换,并通过电流复用技术提升了增益。栅极人工传输线的终端采用了RL型负载,进一步改善了放大器的噪声性能。仿真结果表明,该分布式低噪声放大器的带宽为0.5~5.7 GHz,带内增益达到24.2 dB,噪声系数低于4.5 dB,而最小噪声系数仅为2.7 dB。     

低功耗IR-UWB接收机和LNA设计研究

在分析各种超宽带(UWB)接收机系统结构的基础上,提出了一种低功耗IR-UWB接收机结构.该结构基于非相干通信机制,使用自混频技术和脉冲宽度调制方式(PPM).在该结构中,低噪声放大器(LNA)的低功耗优化是系统低功耗实现的关键.综合分析各种宽带LNA结构,提出了一种低功耗LNA设计.该LNA采用65 nmCMOS标准...     

Design of Adaptive Multimode RF Front-End Circuits

Migration towards higher data rates and higher capacities for multimedia applications, and provision of various services (text, audio, video) from different wireless standards with the same device require integrated designs that work across multiple standards, can easily be reused, and achieve maximum hardware share at minimum power consumption. This can be achieved by using adaptive circuits that are able to trade off power consumption for performance. The design of an adaptive multimode image-reject downconverter (oscillator and two mixers) is presented in this paper. In the highest performance mode, the image-reject downconverter (the quadrature mixers) has an IIP3 of +5.5 dBm, a single-side band noise figure of 13.9dB and a conversion gain of 1.4 dB, while drawing 10mA from a 3 V supply. The adaptive oscillator achieves -123 dBc/Hz phase noise at 1MHz offset from a 2.1 GHz carrier with a bias current of 6 mA in the highest performance mode. Adaptivity in the downconverter is achieved by trading off RF performance for current consumption, ranging from 10 mA for the relaxed mode (e.g., DECT) to 20 mA in the highest performance mode (e.g., DCS1800) of operation     

Low-Power Analog Integrated Circuits for Wireless ECG Acquisition Systems

This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a low-power analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successive-approximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs.     

V-band Low-noise Integrated Circuit Receiver

A compact low-noise V-band integrated circuit receiver has been developed for space communication systems, The receiver accepts an RF input of 60-63 GHz and generates an IF output of 3-6 GHz. A Gunn oscillator at 57 GHz is phaselocked to a low-frequency reference source to achieve high stability and low FM noise. The receiver has an overall single sideband noise figure of less than 10.5 dB and an RF to IF gain of 40 dB over a 3-GHz RF bandwidth. All RF circuits are fabricated in integrated circuits on a Duroid substrate.     

An 800-MHz–6-GHz Software-Defined Wireless Receiver in 90-nm CMOS

A software-defined radio receiver is designed from a low-power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters. To cover the major frequency bands in use today, a wideband RF front-end, including the low-noise amplifier (LNA) and a wide tuning-range synthesizer, spanning over 800 MHz to 6 GHz is designed. The wideband LNA provides 18-20 dB of maximum gain and 3-3.5 dB of noise figure over 800 MHz to 6 GHz. A low 1/f noise and high-linearity mixer is designed which utilizes the passive mixer core properties and provides around +70 dBm IIP2 over the bandwidth of operation. The entire receiver circuits are implemented in 90-nm CMOS technology. Programmability of the receiver is tested for GSM and 802.11g standards     

S波段雷达接收机前端低噪声放大器

采用0.35μm SiGe BiCMOS工艺设计了用于S波段雷达接收机前端电路的低噪声放大器。对于现代无线接收机来说,其动态范围和灵敏度很大程度上都取决于低噪声放大器的噪声性能和线性度。相对于CMOS工艺来说,SiGe BiCMOS工艺具有更高的截止频率、更好的噪声性能和更高的电流增益,非常适合微波集成电路的设计。该低噪声放大器采用三级放大器级联的结构以满足高达30dB的增益要求。在5V的电源电压下,满足绝对稳定条件,在3GHz-3.5GHz频段内,功率增益为34.5dB,噪声系数为1.5dB,输出1dB功率压缩点为11dBm。     

一种解决无线局域网直下变频接收机直流漂移的方法

提出了一种符合IEEE802.11a无线局域网的5GHz直下变频接收机解决直流漂移的方法.该方法利用双平衡混频器输出端的模拟反馈环路消除直流漂移.该混频器经过测试,在5.15GHz频率下具有9.5dB的转换增益,13.5dB的噪声系数和7.6dBm的三阶交调,在3.3V电源电压条件下67mW的功耗,以及1.73mV的直流漂移,并能使直流漂移减少76%.该方案及整个直下变频的WLAN接收机已经采用0.35μm SiGe BiCMOS工艺流片并测试.     

A 9.8-mW 1.2-GHz CMOS frequency synthesizer with a low phase-noise LC-VCO and an I/Q frequency divider

A 1.2 GHz frequency synthesizer integrated in a RF receiver for Beidou navigation is implemented in standard 0.18μm CMOS technology.A distributed biased varactor LC voltage-controlled oscillator is employed to achieve low tuning sensitivity and optimized phase noise performance.A high-speed and low-switching-noise divider-by-2 circuit based on a source-coupled logic structure is adopted to generate a quadrature(I/Q) local oscillating signal.A high-speed 8/9 dual-modulus prescaler(DMP),a programmable-delay phase frequency detector without dead-zone problem,and a programmable-current charge pump are also integrated into the frequency synthesizer. The frequency synthesizer demonstrates an output frequency from 1.05 to 1.30 GHz,and the phase noise is-98.53 dBc/Hz at 100-kHz offset and -121.92 dBc/Hz at 1-MHz offset from the carrier frequency of 1.21 GHz. The power dissipation of the core circuits without the output buffer is 9.8 mW from a 1.8 V power supply.The total area of the receiver is 2.4×1.6 mm~2.     

CMOS blocks for on-chip RF test

In this paper we present two designs of CMOS blocks suitable for integration with RF frontend blocks for test purposes. Those are a programmable RF test attenuator and a reconfigurable low noise amplifier (LNA), optimized with respect to their function and location in the circuit. We discuss their performances in terms of the test- and normal operation mode. The presented application model aims at a transceiver under loopback test with enhanced controllability and detectability. The circuits are designed for 0.35μm CMOS process. Simulation results of the receiver frontend operating in 2.4 GHz band are presented showing tradeoffs between the performance and test functionality.     

High-performance RF mixer and operational amplifier BiCMOS circuits using parasitic vertical bipolar transistor in CMOS technology

The electrical characteristics of the parasitic vertical NPN (V-NPN) BJT available in deep n-well 0.18-/spl mu/m CMOS technology are presented. It has about 20 of current gain, 7 V of collector-emitter breakdown voltage, 20 V of collector-base breakdown voltage, 40 V of Early voltage, about 2 GHz of cutoff frequency, and about 4 GHz of maximum oscillation frequency at room temperature. The corner frequency of 1/f noise is lower than 4 kHz at 0.5 mA of collector current. The double-balanced RF mixer using V-NPN shows almost free 1/f noise as well as an order of magnitude smaller dc offset compared with CMOS circuit and 12 dB flat gain almost up to the cutoff frequency. The V-NPN operational amplifier for baseband analog circuits has higher voltage gain and better input noise and input offset performance than the CMOS ones at the identical current. These circuits using V-NPN provide the possibility of high-performance direct conversion receiver implementation in CMOS technology.     

3.6 mw low power wireless RF receiver front end using creative current recycle technique

This paper presents the design of low noise amplifier and mixer (LIXER) circuit for wireless receiver front ends using 65 nm CMOS technology. The circuit is implemented with CMOS transistors and uses 65 nm CMOS process. Proposed LIXER circuit achieves a maximum gain of 25 dB and DSB noise figure of 3.5 dB. In the given circuit, current shunt paths had created by using LC tank circuit with transistors Q5 and Q6. By using the creative current recycle technique circuit consumes 3.6 mW power with 1.2 V power supply. The operating frequency of the proposed structure is 2.4 GHz with 25 dB conversion gain and ?13 dBm IIP3. The operating of the receiver front end is 2.4 GHz is used for IEEE 802.11a WLAN, Bluetooth, and ZigBee applications.