Active-clamp ZVS converter with step-up voltage conversion ratio

This article presents the circuit implementation and design considerations of a zero voltage switching (ZVS) converter with voltage step-up for battery-based applications. An active-clamp circuit including one auxiliary switch and one clamp capacitor is connected in parallel with the main switch to allow resonant behaviour by the output capacitances of switches and transformer leakage inductance during the transition interval. Thus, the ZVS turn-on of switches can be achieved. The switching losses and thermal stresses of the semiconductors are reduced. The circuit configuration, operation principle and design considerations of the converter are discussed in detail. Finally, experiments conducted on a laboratory prototype rated at 200 W are provided to verify the theoretical analysis and the effectiveness of the proposed converter.     

Improved voltage clamping scheme for ZVS PWM three-level converter

This paper proposes an improved zero-voltage-switching pulsewidth-modulation (ZVS PWM) three-level converter, which is improved from the original ZVS PWM three-level converter by merely exchanging the position of the resonant inductance and the transformer, such that the transformer is connected with the lagging switches. The improved converter has several advantages over the original, e.g., the clamping diodes conduct only once in a switching period, and the resonant inductance current is smaller in zero state, leading to a higher efficiency and reduced duty-cycle loss. A blocking capacitor is usually introduced to the primary side to prevent the transformer from saturating. This paper analyzes the effects of the blocking capacitor in different positions, and a best scheme is determined. A 2.5-kW prototype converter verifies the effectiveness of the improved converter and the best scheme for the blocking capacitor.     

An isolated bridgeless AC-DC PFC converter using a LC resonant voltage doubler rectifier

This paper proposed an isolated bridgeless AC–DC power factor correction (PFC) converter using a LC resonant voltage doubler rectifier. The proposed converter is based on isolated conventional single-ended primary inductance converter (SEPIC) PFC converter. The conduction loss of rectification is reduced than a conventional one because the proposed converter is designed to eliminate a full-bridge rectifier at an input stage. Moreover, for zero-current switching (ZCS) operation and low voltage stresses of output diodes, the secondary of the proposed converter is designed as voltage doubler with a LC resonant tank. Additionally, an input–output electrical isolation is provided for safety standard. In conclusion, high power factor is achieved and efficiency is improved. The operational principles, steady-state analysis and design equations of the proposed converter are described in detail. Experimental results from a 60 W prototype at a constant switching frequency 100 kHz are presented to verify the performance of the proposed converter.     

Simplified clock voltage doubler

A simple clock voltage doubler based on the Nakagome charge pump, is described. It prevents the latch-up of the output switch without requiring an extra charge-pump voltage doubler     

A high-efficiency CMOS voltage doubler

A charge pump cell is used to make a voltage doubler using improved serial switches. A complete power efficiency theory is presented which fits the measurements. The importance of capacitors is shown with plots of power efficiency versus load and stray capacitors. Several problems arising at low voltage or high frequency are developed and some optimizations are presented. The substrate current is totally suppressed by the technique of bulk commutation. A power efficiency of 95% has been reached using external capacitors. A fully integrated charge pump is also presented and shows a maximum power efficiency of 75%     

A flying-capacitor ZVS PWM 1.5 kW DC-to-DC converter with half ofthe input voltage across the switches

This paper introduces an isolated flying-capacitor DC-to-DC converter which features half of the input voltage across the switches, zero-voltage-switching, operation at constant frequency, regulation by pulse-width-modulation, and low RMS current stress upon power switches. The complete operating principle, theoretical analysis, relevant equations and design example are provided in this paper. The experimental results of a 1.5 kW converter with 60 V, 25 A output. 600 V input, operating at 50 kHz switching frequency are also presented and discussed in the paper. The proposed converter is an alternative to the full-bridge ZVS-PWM DC-to-DC converter in high-input voltage applications     

A high-power-factor half-bridge doubler boost converter without commutation losses

This paper proposes a high-power-factor half-bridge doubler boost converter without commutation losses, which provides high output voltages, i.e., from 600 to 900 V. The voltages across the semiconductor devices are low and approximately equal to the output voltage, as doubled output voltages and reduced high-frequency ripple can be achieved. A detailed mathematical analysis concerning its operation is presented, and simulation and experimental results describe the converter performance.     

A comparison of piezoelectric transformer AC/DC converters with current doubler and voltage doubler rectifiers

The objective of this study was to develop recommendations for an optimal design of piezoelectric transformer (PT) AC/DC converters. The paper presents a comprehensive comparison of the two commonly used rectifier topologies in a PT based power converters: current doubler and voltage doubler rectifiers. The advantages and disadvantages of the two rectifiers were investigated and the range of their applications with respect to output current, voltage, power capability, load resistance etc.-was delineated. Generic parameters are proposed and used to derive normalized and closed form equations that can help choosing a PT for a given set of requirements. Simulation and experimental results were found to be in a good agreement with the derivation of the theoretical analysis.     

ZVS移相全桥变换器的优化设计与仿真

针对传统的零电压(ZVS)、零电压零电流(ZVZCS)移相全桥变换器的各种缺陷以及实际参数选取困难的问题,采用一种改进型零电压移相全桥软开关变换器,即在原边钳位两个超快恢复二极管与一隔直电容来降低副边电路的寄生震荡以防止变压器进入磁饱和,为进一步提高变换器的效率,副边采用全波整流。对所设计的电路进行细致的原理分析,给出若干关键值的优化计算过程,并以UC3875作为控制芯片,通过saber仿真验证理论分析的合理性,结果表明电路在实现软开关的同时也抑制了副边整流器件的电压应力,证明了所提优化方案的可靠性。     

A leakage-inductance-based ZVS two-inductor boost converter with integrated magnetics

A two-inductor boost converter topology has conduction loss and transformer utilization advantages in converting low-voltage higher current inputs to high output voltages. In this letter, a new zero-voltage switching (ZVS) two-inductor boost converter with integrated magnetics is proposed. In the new topology, the two current source inductors, a resonant inductor and a two-winding transformer, are integrated into one single magnetic core with three windings. Two windings simultaneously perform the functions of the current source inductors and the transformer primary. The transformer leakage inductance forms the resonant inductance. This leads to a much more compact converter design with a significant reduction in the number of core and winding components. A theoretical analysis establishes the operating point of the ZVS converter. Both of the theoretical and experimental waveforms, including flux waveforms for the legs of the integrated core structure, are presented at the end of the letter.     

利用推挽DC／DC转换器固有特性的倍压器

本设计实例能以最少的元件数实现利用单变压器推挽DC/DC转换器的固有倍压特性的宽范围倍压器.它采用高压达林顿晶体管阵列驱动器ULN2023A来实施.该电路具有5V～30V的较宽输入电压范围,并能以适宜的效率提供了1W～4W的典型电源输出.     

Quasi-continuous current transformer converter and new associated ZVS structure

This paper presents a voltage changer optimized to multiply or to divide the input voltage by an integer factor of 2, 3, 4, ..., with a very high efficiency. The paper first introduces a review of the quasi-continuous current transformer converter in a step by step fashion. The last step presents the full bidirectional zero voltage switching (ZVS) converter. The theoretical study demonstrates the way to achieve ZVS operation by only decreasing the value of the transformer magnetizing inductance. ZVS conditions (developed in the paper) lead to an interesting way to control the converter, and a discrete variable frequency control is proposed. Allowing triangular current in the transformer leads to ZVS in the expanse of higher root-mean-square (RMS) current. The evaluation of this current is also carried out in the theoretical study. An experimental implementation shows an efficiency higher than 97.5% and confirms the accuracy of the theoretical study.     

ZVS Buck-Boost LLC cascade converter with all soft switched switches

A Buck-Boost LLC cascade converter is proposed in this paper. In virtue of the Zero-Voltage-Switching (ZVS) modulation strategy for Buck-Boost circuit, all the switches can be soft switched with wide conversion range and full load range. By sharing one of the two bridge legs, the magnetizing current needed to realize the ZVS of switches decreases. Then, the power density and efficiency of the proposed converter increase. Theoretical analysis and characteristics of the proposed converter are presented and verified on a 210 V–400 V input 12 V/400 W output experimental prototype. The experimental results show that the proposed converter can achieve a peak efficiency of 95.6% at 1 MHz. The power density of the proposed converter is as high as 414 W/in³ with the help of GaN transistors and planar transformers.     

电压模式 Buck变换器典型工作状态分析

电压控制型Buck变换器是典型的非线性电路系统。根据DC-DC Buck变换器的工作特性,建立了研究其非线性现象的仿真模型,分析了Buck变换器的分岔稳定性和混沌化特性,揭示了以输入电压和电感作为分叉参数的混沌现象及系统输出特性;从时域角度分析参考电压波形与输出电压波形交点的变化对变换器工作状态的影响,在相图中得到系统由稳定到混沌的演化过程,并验证了该模型的合理性和可行性。该研究方法也为其他模式DC-DC变换器的分岔与混沌现象提供理论和实验基础。     

Analysis,design and implementation of an interleaved three-level PWM DC/DC ZVS converter

This paper presents a new parallel three-level soft switching pulse-width modulation (PWM) converter. The proposed converter has two circuit cells operated by the interleaved PWM modulation. Thus, the ripple currents at input and output sides are reduced. Each circuit cell has two three-level zero voltage switching circuits sharing the same power switches. Therefore, the current and power rating of the secondary side components are reduced. Current double rectifier topology is selected on the secondary side to decrease output ripple current. The main advantages of the proposed converter are soft switching of power switches, low ripple current on the output side and low-voltage rating of power switches for medium-power applications. Finally, the performance of the proposed converter is verified by experiments with 1 kW prototype circuit.     

Parallel full-bridge converter with wide ZVS and low freewheeling current

The main objective of this paper is to present a direct current to direct current topology with high circuit efficiency. In this studied circuit, two full-bridge circuits and a half-bridge circuit connected in parallel are introduced to achieve the advantages of low switching loss, less primary current, low conduction loss and low filter size compared to the traditional parallel full-bridge converters. The circuit diagram, operation principles, steady-state analysis and experiments are provided to demonstrate the effectiveness of the studied topology. Finally, a 1.44-kW laboratory prototype is constructed to verify the validity of the theoretical analysis. Experimental results show that highest efficiency of 95.3% can be achieved.     

Switching noise and shoot-through current reduction techniques for switched-capacitor voltage doubler

Switching noise and shoot-through current reduction techniques for switched-capacitor voltage doublers based on cross-coupled structure are presented. The intuitive analysis of the shoot-through current and switching noise generation processes in the doubler is first reported. Break-before-make mechanism is adopted to minimize the shoot-through current, thereby greatly reducing the no-load supply current dissipation and improving the light-load power efficiency of the voltage doubler. In addition, by employing gate-slope reduction technique at the serial power transistor during turn-on, the switching noise of the voltage doubler is significantly lowered. Two voltage doublers with and without the proposed circuit techniques have been fabricated in a 0.6-/spl mu/m CMOS process. Experimental results verify that the total supply current at no-load condition of the proposed voltage doubler is reduced by two fold and its switching noise is decreased by 2.5 times.     

Automated thermal voltage converter intercomparisons

An automated system for the intercomparison of thermal voltage converters at the National Bureau of Standards--Gaithersburg is described. It employes a two-channel comparator with components interfaced using the IEEE-488 bus standard. The design and performance of this system are presented and several advantages and disadvantages of this and other automated comparator systems are discussed.     

Four-wire current-regulated PWM voltage converter

Shunt active power filters are connected in parallel with the electricity supply network. If the AC mains has a neutral conductor, it is desirable to compensate the mains harmonic currents zero-sequence components. This can be achieved with a four-wire pulsewidth modulation voltage converter connected to the AC mains. In this case, the three-phase and the neutral AC currents must be controlled. A generalization of the space-vector-based current controller in the αβo coordinate system is presented in this paper. With this current controller, all the current harmonic systems of positive, negative, and zero sequence can be injected by the converter and, thus, compensated on the AC mains. The system is also useful to compensate unbalanced currents of fundamental frequency. A useful benefit of this system is that it is possible to control the converter four-wire currents with equal hysteresis errors. Simulation and experimental results are presented