基于FPGA片上PowerPC实现动态重构

文章介绍了FPGA动态部分重构的实现原理及实现方法,以FPGA内嵌PowerPC处理器内核为基础,通过ICAP内部配置访问通道,控制可重构模块进行在线局部重构,完成了系统动态重构的流程,充分利用了系统的硬件资源,实现了部分动态重构技术在SOPC中的应用。     

一种适于FPGA芯片的SRAM单元及外围电路设计

静态存储器(SRAM)功耗是整个芯片功耗的重要组成部分,并且大规模SRAM的仿真在芯片设计中也相当费时。提出了一种基于40 nm CMOS工艺、适用于FPGA芯片的SRAM单元结构,并为该结构设计了外围读写控制电路。仿真结果表明,该结构的SRAM单元在保证正确的读写操作下,静态漏电电流远远小于同工艺下普通阈值CMOS管构造的SRAM单元。同时,为了FPGA芯片设计时大规模SRAM功能仿真的需要,为SRAM单元等编写了verilog语言描述的行为级模型,完成了整个设计的功能验证。     

基于FPGA部分动态可重构的信号解调系统的实现

针对调制样式在不同环境下的变化,采用了FPGA部分动态可重构的新方法,通过对不同调制样式信号的解调模块的动态加载,来实现了不同环境下针对不同调制样式的解调。这种方式比传统的设计方式具有更高的灵活性、可扩展性,并减低了成本和功耗。该设计方案同时也介绍了FPGA部分动态可重构的概念和特点,可以对其它通信信号处理系统设计提供一定的参考。     

基于DSP的FPGA动态重构系统研究与设计

为了提高现场可编程门阵列（FPGA）的资源利用率,在介绍FPGA重构技术的原理和分类的基础上,讨论了Virtex-4系列FPGA的配置原理和动态重构的方法,并设计出数字信号处理器（DSP）配置FPGA的硬件方案来实现可重构系统。FPGA采用SelectMAP配置方式,实现配置逻辑的快速重构和局部动态重构,最后根据Virtex-4的配置流程和时序关系,给出了可重构系统配置的软件流程。经实验测试,该系统稳定可靠,可在1 s内完成5 Mbyte配置程序的动态重构。     

基于SRAM编程技术的PLD核心可重构电路结构设计

CPLD相对于FPGA更适合实现时序逻辑较少而组合逻辑相对复杂的功能,比如复杂的状态机和译码电路等。CPLD的EEPROM编程技术不适合动态可重构的应用。本文针对CPLD的核心可编程结构：P-Term和可编程互连线,采用2．5V、0．25μm CMOS工艺设计了功能相近的基于SRAM编程技术的可重构电路结构。新的电路结构可以通过可编程方式有效控制功耗和速度的折衷,并且相对于传统的CPLD互联结构减少了50％的编程数据。在动态可重构系统中,采用上述新结构的PLD相对于FPGA可以更有效地实现可重构的复杂状态机和译码电路等应用。     

基于FPGA动态自重构的嵌入式系统设计

本文提出了一种设计动态自重构系统的设计方法。这种方法可以有效地利用现有的IP核,将其经过处理就可以作为动态重构系统的可重构IP核使用。该方法可降低开发成本,缩短设计周期,同时应用动态重构技术的系统层设计是目前的研究热点。本设计使用Xilinx公司新推出的ISE8．2i、EDK8．2i和PlanAhead9．2．7FPGA开发工具,依托XUP Virtex-ⅡPro xc2vp30 FF896-7 FPGA开发板为平台,以其内嵌微处理器为核心搭建了一个可重构系统。该设计有3个重构区域,每个区域有至少两个配置文件,可根据需要在软件程序的调配下实现动态配置。由此系统功能的灵活性和硬件资源的利用率将得到改善。     

基于FPGA的动态自重构系统原理与实现

现场可编程门阵列(Field Programmable Gate Array,FPGA)提供了强大的可编程接口,支持灵活的现场可编程能力。动态可重构设计方法可以在尺寸、重量、功率和成本等方面优化传统的FPGA应用。目前控制、存储和接口组成的动态可重构实现系统,虽然可以实现对FPGA的动态可重构,但需要额外增加多个器件,反而使FPGA应用系统更加复杂。基于动态可重构原理,提出了一种动态自重构系统的原理和实现方法。该方法通过在静态逻辑中添加自重构模块,对自身可重构分区进行功能修改,从而实现对自身的动态重构。设计了两种LED灯的闪烁方式模块,实验结果证明:通过自重构技术,可以实现这两种闪烁方式的切换,证明了自重构技术的可行性。     

卷积神经网络的FPGA并行加速设计与实现

为提高目前硬件设备上运行卷积神经网络的速度和能效,针对主流的卷积神经网络提出了一种基于现场可编程门阵列(Field Programmable Gate Array,FPGA)的流水线并行加速方案,设计优化了数据存储模块、卷积计算模块、池化模块以及全连接模块,结合高层次综合技术构建了基于FP GA的卷积神经网络基本单元.为了降低加速系统的硬件开销,在保证卷积神经网络精度损失很小的前提下,采用数据量化的方式将网络参数从32位浮点数转化为16位定点数.系统测试使用MNIST数据集和CIFAR-10数据集,实验结果显示,所提出的卷积神经网络FPGA加速具有更快的识别效果,并且该方案在资源和功耗较少的情况下可以提供更好的性能,同时能够高效地利用FP GA上的硬件资源.     

一种提高SRAM型FPGA抗单粒子翻转能力的系统设计方案

本文基于国产智能刷新控制芯片,为星载SRAM型FPGA提供了一款高可靠性系统设计方案,具有定时刷新、重载、回读、在轨重构等功能,极大提高了SRAM型FPGA电路的抗单粒子事件能力,满足星载产品空间应用的需求。     

FPGA动态重构技术在算术逻辑单元中的应用

基于Virtex2-Pro ML310开发环境,使用基于模块(Module-based)的部分动态可重构方式,实现了动态重构技术在算术逻辑单元中的运用.实验数据结果表明使用普通方法需要下载的文件大小是使用部分动态重构方法的5.82倍,部分动态重构以较小容量的硬件资源,实现了较大的时序系统整体功能,减小了算术逻辑单元的面积,增加了电路的下载速度并且提高了硬件利用率.     

Towards the implementation of Multi‐band Multi‐standard Software‐Defined Radio using Dynamic Partial Reconfiguration

The vast evolution of fixed and mobile standards urges upgrading the hardware to be compatible with them. An efficient approach to reduce the required cost and effort is hardware reusability, which in turn can be achieved by a dynamically reconfigurable field programmable gate array (FPGA). This flexible hardware time multiplexing allows more logic to fit within the same area, which means fitting bigger designs into smaller less expensive devices, with more optimization of power consumption. This work shows the advantages of using the dynamic partial reconfiguration (DPR) technique, on a fine‐grained block level, in implementing a baseband physical layer processing module for software‐defined radio (SDR) chain that supports 3G, long‐term evolution (LTE), and WIFI standards. The benefits increase when the reconfiguration is not only dynamic but also takes place in run‐time without the need to switch off the system. A comparison is held on Xilinx Virtex 5 design kit XUPV5‐LX110T between the implementation of the baseband processing module with and without using the DPR technique in the 3G, long‐term evolution, and WIFI standards. The comparison addresses the area, power, memory, and time overhead. Experimental results reveal that the DPR technique improves the area and the power consumption with an acceptable increase in memory and latency. Xilinx ISE 14.7 is used for modules implementation, Xilinx PlanAhead is used in floorplanning for the different designs and applying the DPR technique, and Xilinx Power Analyzer is used to measure the power consumption.     

FPGA Implementation of SDR Based CFO Estimation and Compensation Circuit for OFDM System

Based on software defined radio (SDR) architecture, this paper develops a reconfigurable CORDIC vectoring module (CVM) and CORDIC rotation module (CRM) in FPGA to implement the carrier frequency offset (CFO) estimation and compensation circuits of an orthogonal frequency division multiplexing (OFDM) system. The experimental results show that the proposed SDR-pipelined architecture can save power and hardware resource compared with conventional pipelined architecture, because the designed CVM and CRM modules can be reused in the processing modules of CFO estimation and compensation circuit. The performance trade-off for CVM and CRM implemented with different quantized float number in FPGA is presented. Furthermore, the hardware reconfiguration function of CVM and CRM is also validated.     

一种基于SDR硬件平台的可重构方式设计

基于目前多通信体制共存的局面和通信技术高速发展的趋势,本文在对可重构技术进行研究的基础上,提出一种适合清华大学“软硬件可重构的新一代无线通信统一平台”硬件平台的可重构方式,即寄存器参数重配置方式和模块切换方式相结合的动态重构方式。该动态重构方式可节省资源消耗,同时可获得良好的可扩展性和灵活性。     

动态可重构技术浅述

动态可重构技术可以利用可重配置硬件的灵活性,使可重配置硬件不同时刻完成不同的功能.分析表明,通过对可重配置硬件的复用进而扩大硬件的等效规模,可以节省硬件资源的面积、输入/输出管脚和系统的功耗等.研究了动态可重构技术包含的内容,讨论了动态可重构系统设计过程中需要考虑的问题并描述了其发展趋势.     

Deployment of Run-Time Reconfigurable Hardware Coprocessors Into Compute-Intensive Embedded Applications

Day after day, embedded systems add more compute-intensive applications inside their end products: cryptography or image and video processing are some examples found in leading markets like consumer electronics and automotive. To face up these ever-increasing computational demands, the use of hardware accelerators synthesized in field-programmable gate arrays (FPGA) lets achieve processing speedups of orders of magnitude versus their counterpart CPU-based software approaches. However, the inherent increment in physical resources penalizes in cost. To address this issue, dynamically reconfigurable hardware technology definitively reached its maturity. SRAM-based reconfigurable logic goes beyond the classical conception of static hardware resources distributed in space and held invariant for the entire application life cycle; it provides a new design abstraction featured by the temporal partitioning of such resources to promote their continuous reuse, reconfiguring them on the fly to play a different role in each instant. This new computing paradigm lets balance the design of embedded applications by partitioning their functionality in space and time—through a series of mutually-exclusive processing tasks synthesized multiplexed in time on the same set of resources—and achieving thus cost savings in both area and power metrics. However, the exploitation of this system versatility requires special attention to avoid performance degradation. Such technical aspects are addressed in this work intended to be a survey on reconfigurable hardware technology and aimed at defining an open, standard and cost-effective system architecture driven by flexible coprocessors instantiated on demand on reconfigurable resources of an FPGA. This concept fits well with the functional features demanded to many embedded applications today and its feasibility has been proved with a state-of-the-art commercial SRAM-based FPGA platform. The achieved results highlight dynamic partial reconfiguration as a potential technology to lead the next computing wave in the industry.     

Applying Dynamic Reconfiguration for Fault Tolerance in Fine-Grained Logic Arrays

This paper presents the realization of a fault tolerance technique for a dynamically reconfigurable array of programmable cells. The three parts of the technique, fault detection, fault reconfiguration, and fault recovery, are implemented completely in hardware and form a self-contained system. Each of the parts can be exchanged by an alternative implementation without affecting the remaining parts too much, thus making the concept adaptable to different reconfigurable circuits. A hardware realization for the core mechanism is discussed and a prototypical design of a field-programmable gate array implementing the complete system is described. The technological development towards nanoscale feature sizes and the growing influence of deep-submicrometer effects will result in an inherent unreliability of the individual components of future circuit implementations and a higher vulnerability towards external influences. The technique discussed can be used to exploit dynamic reconfiguration capabilities of programmable arrays to alleviate system vulnerability towards these effects and thus to enhance their overall reliability.     

星载环境下可重构技术分析

针对卫星在宇宙空间运行易受到各种高能粒子辐射,产生的单粒子现象会影响卫星正常工作的问题,通过总结传统的抗单粒子效应的几种方法、可重构技术的发展与分类,分析研究了星载可重构系统设计方法用来抗空间环境辐射效应。通过硬件平台的动态重构可以有效克服单粒子效应的影响,实现远程故障维修、硬件可升级、可靠性提高和成本降低等目标。     

Dynamic reconfiguration schemes for megabit BiCMOS SRAMs and performance evaluation

In this paper two dynamic configuration schemes are discussed for megabit BiCMOS static random access memories (SRAMs). Dynamic reconfiguration schemes allows failure detection at the chip level and automatic reconfiguration to fault free memory cells within the chip. The first scheme is a standby system approach where the I/O lines of the memory can be dynamically switched to spare bit slices in the SRAM. This scheme is implemented through a switching network at the memory interface. Every memory access is controlled by a fault status table (FST) which memorizes the fault conditions of each memory block. This FST is implemented outside the memory system. A second dynamic reconfiguration scheme for BiCMOS SRAMs is addressed through a graceful degradation approach. Basic design considerations and performance evaluation of megabit BiCMOS SRAMs using dynamic reconfiguration schemes are presented. The basic properties of the proposed schemes and a prototype VLSI chip implementation details are discussed. BiCMOS SRAM access time improvement of about 35%, chip area of 25%, and chip yield of 10% are achieved, respectively, as compared to conventional methods. A comparison of reliability improvement of 1 Mb BiCMOS SRAMs using dynamic configuration schemes is presented. These two dynamic reconfiguration schemes have considerable importance in reliability improvement when compared to conventional methods. The major advantage is that the size of reconfiguration of the system can be considerably reduced.     

可重构计算平台的硬件结构设计

针对现有可重构计算硬件平台配置时间长、灵活性受限的缺陷问题,介绍了一种基于PC机的FPGA可重构硬件平台结构的设计方法,该结构允许PCI总线快速重构,整个系统的硬件设计可以按以下两个部分进行设计:固定部分和可重构部分。最后在FPGA资源上的验证结果表明该设计能够有效实现FPGA的硬件重构,而且其物理硬件设计简单。     

基于SoC的可重构短波功放数字预失真线性化

在对功率放大器的非线性放大特性研究的基础上,提出了在SoC为核心的硬件平台上对短波功放进行可重构预失真线性化的方法。文章重点对改进型Hammerstein 模型进行了改进,修改后的模型不仅在硬件上易于实现,而且具备模式切换功能,可以根据需求选择不同的有记忆模型或无记忆模型。实验结果证实了修改后的模型能有效地抑制短波功放的带外寄生辐射。提出的基于SoC 硬件平台的预失真线性化实现方案可以很方便地实现各种不同的预失真非线性模型,节省系统硬件资源,具有重要的工程实际应用价值。