Design and finite element analysis of weighted-stiffnessmicroelectromechanical digital-to-analogue converters

A microelectromechanical digital-to-analogue converter (DAC) based on the weighted-stiffness (WS) principle analogous to a weighted-resistor DAC for use in electronic circuits is proposed. To convert the digital voltage input to the analogue displacement, the stiffness of the vertical beams is employed as the scale factor. Finite element analysis and design optimisation are performed. Simulation shows that the error for the proposed DAC is less than 0.001 μm     

BIST scheme for DAC testing

A low-cost, built-in self-test (BIST) scheme for a digital-to-analogue converter (DAC) is presented. The basic idea is to convert the DAC output voltages corresponding to different input codes into different oscillation frequencies through a voltage controlled oscillator (VCO), and further transfer these frequencies to different digital codes using a counter. According to the input and output codes, performances of a DAC, such as offset error, gain error, differential nonlinearity (DNL), integral nonlinearity (INL), could be effectively detected by simply using digital circuits rather than complex analogue ones. In addition, the annoying DAC output noise could be naturally filtered out by this BIST method     

C-2C digital-to-analogue converter on insulator

A new C-2C digital-to-analogue converter (DAC) has been investigated, which uses C and 2C capacitors. It is difficult to realise the C-2C DAC scheme on a silicon wafer because of the large parasitic capacitance. However, the C-2C DAC can be fabricated on glass or quartz substrates. The C-2C DACs require considerably less area and power than conventional weighted-capacitor (WC) DACs, and operate at a much higher conversion rate. Simulation results show that an 8 bit C-2C DAC can operate at a settling time of 5.3 ns for a unit capacitance of 1 pF     

Influence of the feedback DAC delay on continuous-time bandpassΣΔ coverter

An analysis of the effect of the feedback digital-to-analogue converter (DAC) delay on the synthesis results of continuous-time ΣΔ bandpass modulators is presented. It is shown that non-null values of the feedback DAC delay can be optimal with respect to the filter gain margin     

Digital compensation of DAC mismatches in multibit delta-sigma ADCs

A digital compensation technique to overcome the effects of the digital-to-analogue converter (DAC)'s mismatches in multibit delta- sigma modulators is described. The technique is purely digital, does not require the injection of a pilot signal and is compatible with binary-weighted element DACs. Simulation results confirm the validity of the compensation technique for a four-bit, fifth-order lowpass modulator with an oversampling ratio of 12 and 1% mismatch in the DAC elements. The compensated modulator exhibits a peak signal- to-noise-and-distortion ratio of 74.5 dB; that is within 0.5 dB of the ideal system without mismatch.     

Digitally tuned Gm-C filter with VDD/temperature-compensating DAC

A digitally tuned Gm-C filter with a V_DD/temperature-compensating digital-to-analogue converter (DAC) is presented. By using the proposed DAC, the bandwidth sensitivities to V_DD and temperature variations of a Gm-C filter can be decreased without repeated frequency tuning. The measured bandwidth sensitivities are as low as 1.2%/100degC and 1.7%/V for temperature and V_DD, respectively     

Mismatch-shaping switching for two-capacitor DAC

A mismatch-shaping scheme is proposed for a two-capacitor digital-to-analogue converter (DAC). It uses a delta-sigma loop for finding the optimal switching sequence for each input word. Simulations indicate that the scheme can be used for the realisation of DACs with 16 bit linearity and SNR performance     

雷达伺服系统中DAC位数和数字PWM位数的选择

雷达伺服系统是全闭环伺服系统。文中分析了D／A变换器（DAC）的工作特性以及在全闭环伺服系统中的应用特点。由于DAC和齿轮减速比都影响着伺服系统的开环增益,当系统开环增益一定时,DAC位数的实际作用和减速比的选择相互限制,在设计雷达伺服系统中需注意。文中同时指出,数字式PWM的实质也是一种DAC,它的位数选择同样遵循DAC的选择原则。     

3V 10b 70 MHz CMOS D/A converter for video applications

This work describes a 10 b 70 MHz CMOS digital-to-analogue converter (DAC) for video applications. The proposed DAC is composed of a unit decoded matrix for 7 MSBs and a binary weighted array for 3 LSBs, considering linearity, power consumption, routing area and glitch energy. A new switching scheme for the unit decoded matrix is developed to further improve the linearity. Cascode current sources and differential switches with a new deglitching circuit improve the dynamic performance     

基于MAX5307和DSP的多回路测控系统设计

提出了一种多回路测控系统的设计方案.该方案仅使用一个DSP(数字信号处理器)及一个多通道集成的D/A转换器件MAX5307,不仅同时保证了多个测控回路的实时性及控制精度,而且实现简单,成本低廉.文中结合实际系统,给出了其具体的硬件和软件实现.该方法具有广泛的适用性,对类似系统的设计具有参考价值.     

BIST structure for DAC testing

A built-in self-test (BIST) structure for digital-to-analogue converter (DAC) testing is presented. The basic idea is to divide the input codes (0, 1, ..., 2ⁿ-1) of the DAC under test into a number of segments. The DAC output voltages corresponding to different codes in the same segment are amplified to the same voltage value. Such that one single reference voltage can be used to test all codes in the same segment. By this method, the number of reference voltages required for DAC testing can be greatly reduced. We show that offset error, gain error, integral nonlinearity (INL) and differential nonlinearity (DNL) are effectively detected in the proposed BIST structure     

一种基于PWM的电压输出DAC电路设计

对实际应用中的脉宽调制(PWM)波形的频谱进行了理论分析．指出通过一个低通滤波器可以把PWM调制的数模转换信号解调出来．实现从PWM到DAC的转换。论文还对转换误差产生的因素进行了分析，指出了减少误差的方法，论文给出了两种从PWM到0～5V电压输出的电路实现方法，第2种电路具有很高的转换精度。     

Ratiometric current-mode rational DAC

By exploring the principle of current division, a ratiometric current-steering rational implementation of a rational digital-to-analogue converter (DAC) is proposed. In this implementation, current scaling is achieved through ratios and, as a result, achieve greater independence from actual physical parameters and their associated non-idealities, resulting in the potential for achieving higher accuracy.     

Switched-capacitor logarithmic DAC

An accurate. low-power, switched-capacitor (SC) digital-to-analogue converter (DAC) with exponential characteristics is presented. The design represents a significant improvement in performance and reduction in complexity over previously reported logarithmic DACs     

10 bit 200 MS/s CMOS D/A converter employing high-speed limiter

A 10 bit 200 MS/s CMOS current-steering digital-to-analogue converter (DAC) employing a new voltage limiter to reduce the feedthrough of the control signals is presented. For high-speed operation of the limiter, a design technique based on the parasitic capacitor of a PMOS transistor is proposed. At 200 MS/s, a spurious-free dynamic range of 65 dBc for a 40 MHz output signal has been achieved from the proposed DAC.     

An ultra-low power CMOS DC–DC buck converter with double-chain digital PWM technique

In present-day integrated digital circuits are become attractive choice for the DC–DC buck converters. This paper proposes a novel approach of CMOS DC–DC buck converter with double-chain digital pulse width modulation (PWM) for ultra-low power applications. The proposed digital PWM architecture consists of double delay lines which is to reduce power consumption and improves ripple voltage with the resolution. An algorithm is proposed that describes the operation of digital PWM. The double chain digital PWM is implemented and analyzed in cadence platform using commercial 180 nm TSMC design kit. The promising results reveals that the power consumption is reduces up to 1.16 µW with occupies less area under the operating frequency of 100 kHz. The DC–DC buck converter with proposed PWM achieves peak efficiency of 92.6% including a load current range of 4–10 mA. This proposed digital PWM method demonstrates its ability to minimize the ripple voltage by 49% and enables to DC–DC converter for compose in a compact chip area as compared to conventional converters. Measured and Simulated power efficiency are made good agreement with each other.     

36-GHz, 16× 6-Bit ROM in InP DHBT Technology Suitable for DDS Application

A 16times6-bit read-only memory (ROM), employing an architecture suitable for use as a phase to amplitude converter for direct digital synthesizers (DDS), has been implemented in InP double heterojunction bipolar transistor (DHBT) technology. The ROM uses a -3.8 V power supply and dissipates 1.13 W of power. The ROM is implemented in a test circuit that includes an 8-bit accumulator and a 6-bit digital-to-analog converter (DAC) to facilitate demonstration of high-speed operation. The maximum operating clock frequency is measured to be 36 GHz     

Background digital calibration of successive approximation adc with adaptive equalisation

An equalisation-based digital background error-correction technique for successive approximation analogue-to-digital converters (SA-ADCs) is presented. This technique enables the size of the sampling capacitors to be scaled down to the kT/C limit without matching concerns. Therefore, for SA-ADCs with resolutions of 10 bits and above, the proposed low-cost, power-efficient digital calibration technique indicates a large power saving and scalability improvement in deeply scaled CMOS technology. Computer simulation validates the effectiveness of this technique for a SA-ADC with 12-bit resolution and 10% mismatch in its digital-to-analogue converter component. The effective number of bits is improved from 4.8 to 12.     

A tight signal-band power bound on mismatch noise in a mismatch-shaping digital-to-analog converter

Many applications employ digital-to-analog converters (DACs) to obtain the advantages of digital processing (e.g., low power and physical size, resilience to noise, etc.) to generate signals, such as voltages, that are analog in nature. Given the appropriate numerical representation of its input, the DAC ideally behaves as a linear gain element. However, as a result of inevitable component mismatches, the output of a multibit DAC (i.e., a DAC designed to output more than two analog levels) is a nonlinear function of its input. The resulting distortion, called DAC noise , limits the overall signal-to-noise ratio (SNR) and hence the obtainable accuracy of the DAC. Mismatch-shaping DACs exploit built-in redundancy to suppress the DAC noise in the input signal's frequency band. Although mismatch-shaping DACs are widely used in commercial products, little theory regarding the structure of their DAC noise has been published to date. Consequently, designers have been forced to rely upon simulations to estimate DAC noise power and behavior, which can be misleading because the DAC noise depends on the DAC input. This paper addresses this problem. It presents an analysis of the DAC noise power spectral density (PSD) in a commonly used mismatch-shaping DAC: the dithered first-order low-pass tree-structured DAC. This design ensures that its DAC noise has a spectral at dc (i.e., zero frequency) by generating digital, dc-free sequences using the same techniques that have been developed for line codes. An expression is derived for the DAC noise PSD that depends on the statistics of these sequences and is used to show various properties of the DAC noise. Specifically, an attainable bound is derived for the signal-band DAC noise power that can be used to predict worst case performance in practical circuits.     

Narrow Pulse Elimination PWM for Multilevel Digital Audio Power Amplifiers Using Two Cascaded H-Bridges as a Nine-Level Converter

This paper presents a methodology to reduce total harmonic distortion (THD) in digital audio power amplifiers, using two new approaches: 1) a multilevel converter made of two cascaded full-bridges, with suitable power supplies to operate as a nine-level hybrid type converter and 2) a new pulsewidth modulation (PWM) technique called narrow pulse elimination (NPE) PWM. The proposed nine-level converter uses only eight MOSFETs. Unlike conventional PWM, the NPE PWM does not generate excessively narrow pulses, so that power semiconductors nonideal delays and switching times are still negligible. Therefore, the nine-level output voltage THD, mostly introduced in the power stage, is strongly reduced. With the NPE technique, the resolution of the generated PWM is no longer limited by the switching speed of the output switches, but only by the frequency of digital processing circuit. Simulation and experimental results from a laboratory prototype are presented in order to show the effectiveness of the proposed approaches