A coupled efficient and systematic full-wave time-domain macromodeling and circuit Simulation method for signal integrity analysis of high-speed interconnects

This paper presents an accurate and systematic approach for analysis of the signal integrity of the high-speed interconnects, which couples the full-wave finite difference time domain (FDTD) method with scattering (S) parameter based macromodeling by using rational function approximation and the circuit simulator. Firstly, the full-wave FDTD method is applied to characterize the interconnect subsystems, which is dedicated to extract the S parameters of the subnetwork consisting of interconnects with fairly complex geometry. Once the frequency-domain discrete data of the S parameters of the interconnect subnetwork is constructed, the rational function approximation is carried out to establish the macromodel of the interconnect subnetwork by employing the vector fitting method, which provides a more robust and accurate solution for the overall problem. Finally, the analysis of the signal integrity of the hybrid circuit can be fulfilled by using the S parameters based macromodel synthesis and simulation program with integrated circuits emphasis (SPICE) circuit simulator. Numerical experiments demonstrate that the proposed approach is accurate and efficient to address the hybrid electromagnetic (interconnect part) and circuit problems, in which the electromagnetic field effects are fully considered and the strength of SPICE circuit simulator is also exploited.     

A circuit model of a system of VLSI interconnects for time responsecomputation

A novel computational model based on the spectral-domain approach for the characterization of a dispersive multiconductor system is developed for time response computation. The model consists of two identical impedance networks and equivalent voltage-controlled voltage sources, and it is particularly suitable for timing analysis. Since the model is constructed based on full-wave analysis, the hybrid nature of the VLSI interconnects is taken care of, and thus the model is valid at high frequencies when the longitudinal field components are no longer negligible. Signal distortions due to the dispersive nature of a multiconductor system are demonstrated by an example     

High-speed and low-power repeater for VLSI interconnects

This paper proposes a repeater for boosting the speed of interconnects with low power dissipation. We have designed and implemented at 45 and 32 nm technology nodes. Delay and power dissipation performances are analyzed for various voltage levels at these technology nodes using Spice simulations. A significant reduction in delay and power dissipation are observed compared to a conventional repeater. The results show that the proposed high-speed low-power repeater has a reduced delay for higher load capacitance. The proposed repeater is also compared with LPTG CMOS repeater, and the results shows that the proposed repeater has reduced delay. The proposed repeater can be suitable for high-speed global interconnects and has the capacity to drive large loads.     

PCB信号完整性影响因素探讨

3G时代的到来,对现在的产品使用的材料是一个挑战。随着产品的传输频率越来越高,传输速度也越来越快,趋肤效应越来越明显。铜箔的毛面和光面的粗糙度成为影响信号完整性一个关键因素,本次试验的目的就是从理论设计出发,选择不同介质损耗的板材,配合不同粗糙度的铜箔和不同内层表面处理方式,根据终端信号的模拟,找到介质损耗和铜箔粗糙度对信号传输的影响,为后续终端设计师对板材和铜箔的选择做好理论和实践准备。     

面向高清媒体处理器的内存控制器的信号完整性验证方法

传统的PCB系统级仿真是提取电路的RLC Model,结合IBIS Model来表征整个电路的参数性能,但是随着芯片集成度越来越高,系统的信号频率越来越高,对整个系统的要求也越来越高,单纯的靠ibis Model仿真已经不能非常准确的反应实际的结果。把微波领域中的S参数应用到电路系统中,通过端口能量的传递关系,用频域信号表征时域信号,能更准确的表征整个电路的性能,更优化设计,节约资源。文中介绍了一种内存控制器的仿真方法,利用s参数和Hspice仿真,为后期系统设计,PCB layout设计提供有力的证明依据。     

高速电路中的信号完整性分析

随着嵌入式系统速度的提高,信号完整性(Signal Integrity,SI)问题受到越来越多的关注。由于信号质量不理想而造成系统崩溃的现象经常出现。结合系统设计中的实例,对高速信号传输的信号完整性问题作了较为详细的论述。在电路设计初期,通过PROTEL软件对和信号完整性进行分析,仿真结果指导PCB板的设计,可以有效地提高信号的完整性,极大地缩短设计周期,降低设计成本。     

Optimization and scaling of CMOS-bipolar drivers for VLSI interconnects

In this paper, rules are presented for the optimized design of CMOS-bipolar drivers for large capacitive loads typical of VLSI interconnects. Simulations and closed-form solutions show that the n-p-n bipolar transistors have to be operated in the high-level injection mode, and that their sizes have to be tailored to the two-thirds power of the load, and it scales with the two-thirds power of the base width of the n-p-n transistor and with the one-third power of the channel length of the MOS transistor. For comparison, the CMOS cascade with a tailored second stage is shown to have competitive potential at the expense of an area being approximately 2.5 times larger than that of a CMOS-bipolar stage.     

Analytical nonlinear HEMT model for large signal circuit simulation

A new nonlinear high electron mobility transistor (HEMT) model based on the Curtice model is described. This model introduces terms for the leakage current for subthreshold bias, drain voltage dependencies of knee voltage, drain conductance and threshold voltage, transconductance enhancement at high frequencies caused by DX centers, and the bias dependence of capacitance. Applying this model to pseudomorphic double-recessed gate HEMT's gives an average error of 2.6% for DC current and 10% for S-parameters     

Optimization of throughput performance for low-power VLSI interconnects

The technique of optimal voltage scaling and repeater insertion is analyzed in this paper to reduce power dissipation on global interconnects. An analytical model for the maximum bit-rate of a very large scale integration interconnect with repeaters has been derived and results are compared with HSPICE simulations. The analytical model is also used to study the effects of interconnect length and scaling on throughput. The throughput-per-bit-energy is analyzed to determine an optimum combination of supply voltage and repeaters for a low-power global interconnect with 250 nm /spl times/ 250 nm cross-sectional dimensions implemented with the 180 nm micro-optical silicon system technology node. It is shown that the optimal supply voltage is approximately equal to twice the threshold voltage. A case study illustrates that a combination of 1 V supply along with one repeater per millimeter increases the throughput-per-bit-energy to over three times that of a latency-centric interconnect of 2 V, which results in a 70% reduction in power dissipation without any loss of throughput performance.     

高速电路信号完整性问题研究及其仿真分析

针对高速电路信号完整性,在介绍信号完整性基本概念的基础上,重点研究了信号反射问题.分析了反射形成的原因和解决方法,阐述了信号完整性仿真分析的相关内容,最后结合实际的应用说明了利用Mentor Graphics公司的HyperLynx仿真工具解决信号反射的方法.     

半导体激光器改进电路模型的大信号验证

实现了一种可以对于反射系数进行精确建模的半导体激光器电路模型并且与传统模型进行了比较。在ADS(Advanced Design Systems)中使用了SDD(Symbolic Defined Devices)器件实现,对于速率方程进行了变形以改进模型的收敛性,该模型可用于大信号仿真。对于不同偏置条件下的半导体激光器的反射系数进行了仿真并且和测量结果进行了对比。首次在大信号仿真中验证了改进模型的精确性。     

面向远端串扰的电路信号降扰研究

电路板信号间的远端串扰对信号的完整性具有较大的影响。为研究降低远端串扰的方法,本文利用Ansoft HFSS软件对线间串扰进行电磁仿真研究。研究表明通过添加防护线、覆盖介质层等措施可以降低远端串扰的影响。在一定频率范围内增加RSR结构中金属贴片的长度和数量,使金属贴片厚度接近微带线厚度等措施,会具有更好的效果;选择具有较高相对介电常数的覆盖介质层材料及增大介质层的厚度也可以降低远端串扰的影响。     

A comprehensive 2-D inductance modeling approach for VLSI interconnects: frequency-dependent extraction and compact circuit model synthesis

Although three-dimensional (3-D) partial inductance modeling costs have decreased with stable, sparse approximations of the inductance matrix and its inverse, 3-D models are still intractable when applied to full chip timing or crosstalk analysis. The 3-D partial inductance matrix (or its inverse) is too large to be extracted or simulated when power-grid cross-sections are made wide to capture proximity effect and wires are discretized finely to capture skin effect. Fortunately, 3-D inductance models are unnecessary in VLSI interconnect analysis. Because return currents follow interconnect wires, long interconnect wires can be accurately modeled as two-dimensional (2-D) transmission lines and frequency-dependent loop impedances extracted using 2-D methods . Furthermore, this frequency dependence can be approximated with compact circuit models for both uncoupled and coupled lines. Three-dimensional inductance models are only necessary to handle worst case effects such as simultaneous switching in the end regions. This paper begins by explaining and defending the 2-D modeling approach. It then extends the extraction algorithm to efficiently include distant return paths. Finally, a novel synthesis technique is described that approximates the frequency-dependent series impedance of VLSI interconnects with compact circuit models suitable for timing and noise analysis.     

S-parameter-measurement-based high-speed signal transientcharacterization of VLSI interconnects on SiO2-Si substrate

A new S-parameter-based signal transient characterization method for very large scale integrated (VLSI) interconnects is presented. The technique can provide very accurate signal integrity verification of an integrated circuit (IC) interconnect line since its S-parameters are composed of all the frequency-variant transmission line characteristics over a broad frequency band. In order to demonstrate the technique, test patterns are designed and fabricated by using a 0.35 μm complementary metal-oxide-semiconductor (CMOS) process. The time-domain signal transient characteristics for the test patterns are then examined by using the S-parameters over a 50 MHz to 20 GHz frequency range. The signal delay and the waveform distortion presented in the interconnect lines based on the proposed method are compared with the existing interconnect models. Using the experimental characterizations of the test patterns, it is shown that the silicon substrate effect and frequency-variant transmission line characteristics of IC interconnects can be very crucial     

Influence of the ground line position on the signal integrity of product-related interconnects in the frequency and time domain

The impact of the ground line position on the line parameters of signal interconnects built in a 110-nm CMOS technology is investigated in the presence of a conductive substrate. Characteristic line parameters obtained from simulations are validated with two-port network analyzer measurements of specially designed test structures in a frequency range up to 50 GHz. In addition, the influence of the ground line position on time-domain signals in product-related bus systems is explored. It is shown that the impact of substrate effects on the line parameters, and consequently on the signal shape in the time domain, strongly depends on the relative position of the ground line with respect to the signal lines and, as expected, on the length of the line system. The authors show that for short on-chip bus systems (shorter than 2 mm), the influence of the ground line positioning on time-domain signals is negligible. However, for long bus systems (e.g., 5 mm), this influence becomes significant and can no longer be neglected.     

A novel dimension-reduction technique for the capacitanceextraction of 3-D VLSI interconnects

In this paper, a new capacitance extraction method called the dimension-reduction technique (DRT) is presented for three-dimensional (3-D) very large-scale integration (VLSI) interconnects. The DRT converts a complex 3-D problem into a series of cascading simple two-dimensional (2-D) problems. Each 2-D problem is solved separately, thus we can choose the most efficient method according to the arrangement of conductors. We have used the DRT to extract the capacitance matrix of multilayered and multiconductor crossovers, bends, vias with signal lines, and open-end. The results are in close agreement with those of Ansoft's SPICELINK and the Massachusetts Institute of Technology's (MIT) FastCap, but the computing time and memory size used by the DRT are several (even ten) times less than those used by SPICELINK and FastCap     

Modeling strategies of the input admittance of RC interconnects for VLSI CAD tools

In this paper, models of input admittance of RC interconnects are discussed in depth to understand and evaluate their loading effects on driving CMOS gates. From a detailed analysis of input admittance pole-zero location, arguments are derived to prove that their input admittance can be accurately approximated to that of a low-order equivalent RC circuit, in contrast to the case of timing analysis of RC wires. More specifically, 1st- or 2nd-order equivalent circuits are derived analytically via the moment matching approach, in contrast to previous analyses that rely on purely numerical approaches. Moreover, simple analytical rules to extend results to arbitrarily complex networks are derived, as opposed to the usual approach that requires numerical estimation of moments. Being fully analytical, the proposed approach permits one to develop models that are extremely simple (i.e. computationally efficient), as well as to gain an insight into the properties of input admittance of RC interconnects.The proposed equivalent circuits are evaluated and validated in situations that occur in real CAD design flows, where RC wire loading effects are estimated by CAD tools to perform the timing/power analysis of the buffer driving the wire. The analysis is validated through extensive simulations on a 65 nm CMOS technology. Well-defined criteria are also derived to select the appropriate model of RC wire input admittance for accurate timing/power estimations in VLSI CAD tools.     

Fast VLSI algorithms for division and square root

Real time digital signal processing demands high performance implementations of division and square root. This can only be achieved by the design of fast and efficient arithmetic algorithms which address practical VLSI architectural design issues. In this paper, new algorithms for division and square root are described. The new schemes are based on pre-scaling the operands and modifying the classical SRT method such that the result digits and the remainders are computed concurrently and the computations in adjacent rows are overlapped. Consequently, their performance exceeds that of the SRT methods. The hardware cost for higher radices is considerably more than that of the SRT methods but for many applications, this is not prohibitive. A system of equations is presented which enables both an analysis of the method for any radix and the parameters of implementations to be easily determined. This is illustrated for the case of radix 2 and radix 4. In addition, a highly regular array architecture combining the division and square root method is described.     

VLSI array algorithms and architectures for RSA modularmultiplication

We present two novel iterative algorithms and their array structures for integer modular multiplication. The algorithms are designed for Rivest-Shamir-Adelman (RSA) cryptography and are based on the familiar iterative Horner's rule, but use precalculated complements of the modulus. The problem of deciding which multiples of the modulus to subtract in intermediate iteration stages has been simplified using simple look-up of precalculated complement numbers, thus allowing a finer-grain pipeline. Both algorithms use a carry save adder scheme with module reduction performed on each intermediate partial product which results in an output in carry-save format. Regularity and local connections make both algorithms suitable for high-performance array implementation in FPGA's or deep submicron VLSI. The processing nodes consist of just one or two full adders and a simple multiplexor. The stored complement numbers need to be precalculated only when the modulus is changed, thus not affecting the performance of the main computation. In both cases, there exists a bit-level systolic schedule, which means the array can be fully pipelined for high performance and can also easily be mapped to linear arrays for various space/time tradeoffs