Rapid thermal annealing effects on Si p+-n junctionsfabricated by low-energy FIB Ga+ implantation

Effects of rapid thermal annealing (RTA) on sub-100 nm p⁺ -n Si junctions fabricated using 10 kV FIB Ga⁺ implantation at doses ranging from 10¹³ to 10¹⁵ cm ^-2 are reported. Annealing temperature and time were varied from 550 to 700°C and 30 to 120 s. It was observed that a maximum in the active carrier concentration is achieved at the critical annealing temperature of 600°C. Temperatures above and below the critical temperature were followed by a decrease in the active concentration, leading to a `reverse' annealing effect     

6H-SiC p+-n junctions fabricated by berylliumimplantation

The use of beryllium (Be) as an alternate p-type dopant for implanted silicon carbide (SiC) p⁺-n junctions is experimentally demonstrated. The implanted layers have been characterized with photoluminescence (PL) as well as secondary ion mass spectrometry (SIMS) measurements. In comparison with boron implanted p ⁺-n junctions, Be-implanted junctions show improvement in the forward characteristics while exhibiting slightly higher reverse leakages. The activation energies extracted from the forward conduction and reverse leakage characteristics of the Be-diodes are 1.5 eV, and 0.13 eV, respectively. Moreover, activation energy extraction in the forward ohmic region reveals the Be impurity level at 0.38±0.04 eV. The minority carrier lifetime extracted from reverse recovery measurements is as high as 160 ns for the Be-diodes compared to 82 ns obtained for the B-diodes     

Electrical properties of Si p+-n junctions for sub-0.25μm CMOS fabricated by Ga FIB implantation

p⁺-n junction diodes for sub-0.25-μm CMOS circuits were fabricated using focused ion beam (FIB) Ga implantation into n-Si (100) substrates with background doping of N_b=(5-10)×10 ¹⁵ and N_b⁺=(1-10)×10¹⁷ cm^-3. Implant energy was varied from 2 to 50 keV at doses ranging from 1×10¹³ to 1×10¹⁵ cm^-2 with different scan speeds. Rapid thermal annealing (RTA) was performed at either 600 °C or 700°C for 30 s. Diodes fabricated on N_b⁺ with 10-keV Ga⁺ exhibited a leakage current (^I_R) 100× smaller than those fabricated with 50-keV Ga⁺. Tunneling was determined to be the major current transport mechanism for the diodes fabricated on N_b⁺ substrates. An optimal condition for I_R on N_b⁺ substrates was obtained at 15 keV/1×10¹⁵ cm^-2. Diodes annealed at 600°C were found to have an I_R 1000× smaller than those annealed at 700°C. I-V characteristics of diodes fabricated on N_b substrates with low-energy Ga⁺ showed no implant energy dependence. I-V characteristics were also measured as a function of temperature from 25 to 200°C. For diodes implanted with 15-keV Ga ⁺, the cross-over temperatures between I_diff and I_g-r occurred at 106°C for N_b ⁺ and at 91°C for N_b substrates     

Simultaneous formation of silicide ohmic contacts and shallow p+-n junctions by ion-beam mixing and rapid thermal annealing

Low-resistivity, uniform molybdenum silicide layers, and shallow p⁺-n junctions with good electrical characteristics have been formed using ion-beam mixing and rapid thermal annealing (RTA). Detailed reverse leakage current data on RTA annealed diodes, which were formed by implanting BF2⁺into Si substrates through the molybdenum films deposited on Si, are presented. The process has a great potential for CMOS fabrication with self-aligned silicided source, drain, and gate.     

0.2-μm p+-n junction characteristics dependent onimplantation and annealing processes

Junction depth, sheet resistance, dopant activation, and diode leakage current characteristics were measured to find out the optimal processing conditions for the formation of 0.2-μm p⁺-n junctions. Among the 2×10¹⁵ cm^-2 BF₂ implanted crystalline, As or Ge preamorphized silicon, the crystalline and Ge preamorphized samples exhibit excellent characteristics. The thermal cycle of furnace anneal (FA) followed by rapid thermal anneal (RTA) shows better characteristics than furnace anneal, rapid thermal anneal, or rapid thermal anneal prior to furnace anneal     

Very-shallow low-resistivity p+-n junctions for CMOS technology

Shallow p-n junctions 110 nm deep have been fabricated using rapid thermal diffusion from a spin-on oxide source. Surface concentrations greater than 3 × 10²⁰cm^-3are possible, with sheet resistivities less than 100 Ω/sq and a maximum reverse-bias leakage at 5 V of 3 nA.cm^-2. Results from 150-nm junctions are also given and are compared with BF2ion implantation.     

p^＋—n^——n结的势垒分布

GaP:N绿色LED发光效率的提高有赖于对其结构参数的优化。根据载流子分布的连续性,由泊松方程自治求解,得出了半导体n^--n结势垒分布的计算方法。在此基础上,计入n^-区内的电位降,计算了商用光二极管p^ -n^--n结构的势垒分布,为整体结构的参数优化准备了必要的条件。     

Characterization of ultra-shallow p+-n junction diodesfabricated by 500-eV boron-ion implantation

Ultrashallow gated diodes have been fabricated using 500-eV boron-ion implantation into both Ge-preamorphized and crystalline silicon substrates. Junction depths following rapid thermal annealing (RTA) for 10 s at either 950°C or 1050°C were determined to be 60 and 80 nm, respectively. These are reportedly the shallowest junctions formed via ion implantation. Consideration of several parameters, e.g. reduced B⁺ channeling, increased activation, and reduced junction leakage current, lead to the selection of 15 keV as the optimal Ge preamorphization energy. Transmission electron microscope results indicated that an 850°C/10-s RTA was sufficient to remove the majority of bulk defects resulting from the Ge implant. Resulting reverse leakage currents were as low as 1 nA/cm² for the 60-nm junctions and diode ideality factors for crystalline and preamorphized substrates ranged from 1.02 to 1.12. Even at RTA temperatures as low as 850°C, the leakage current was only 11 nA/cm ². The final junction depths were found to be approximately the same for both preamorphized and nonpreamorphized samples after annealing at 950°C and 1050°C. However, the preamorphized sample exhibited significantly improved dopant activation     

Damage removal/dopant diffusion tradeoffs in ultra-shallowimplanted p+-n junctions

The tradeoffs between implant damage annealing and shallow junction formation are investigated. For very-low-energy amorphizing implants the time for damage anneal has a fourth-power dependence on depth below the Si surface. The depth effect depends on the type of amorphizing ion. It is shown that as a result, implanted B in Ge-preamorphized Si diffuses with no detectable self-interstitial supersaturation if the damage is <600 Å deep. Conditions for forming defect-free, shallow p⁺-n junctions are described in design curves and comparisons are made between several junction-formation approaches. Implantation of B at energies below 2 keV offers an attractive way of achieving 500-Å junctions     

Fully implanted InP JFET with an abrupt p+-n junction

We report the first fully implanted InP junction field-effect transistor (JFET) with an abrupt p⁺-n junction. The device was made on a semi-insulating InP substrate with Si⁺⁺implant for the n-channel and Be/P co-implant for the p⁺-region. A novel self-aligned process was used to reduce the gate-source spacing and thus minimize the series resistance. Good pinch-off characteristics and very low gate leakage current were obtained. The extrinsic transconductance is approximately 40 mS/mm for a gate length of 5 µm and a channel doping of 6 × 10¹⁶/cm³.     

Formation of shallow p+-n junctions using boron-nitride solid diffusion source

Shallow p⁺-n junctions on the order of 0.1-µm deep have been fabricated using boron-nitride (BN) solid diffusion sources. The process combines the hydrogen-injection method and rapid thermal processing (RTP). Sheet resistivities, in ranges from 50 to 130 Ω/sq with junction depths from 0.1 to 0.19 µm, are possible in this technique. Diode characteristics of 0.11-µm junctions show low reverse leakage current, of the order of 10 nA/cm², indicating the possibility of this method to form PMOS source-drain contacts.     

Abnormal junction profile of silicided p+/n shallowjunctions: a leakage mechanism

The leakage mechanism in p⁺/n shallow junctions fabricated using Co silicidation and shallow trench isolation processes has been investigated using transmission electron microscopy (TEM) combined with selective chemical etching. TEM and TSUPREM-4 simulation results show that dopant profiles bend upward near the edge of the active region. The formation of the abnormal profile is attributed to transient enhanced diffusion induced by source/drain implantation. Based on the TEM and simulation results, it is suggested that the shallower junctions formed near the active edge can serve as a source for leakage current in the silicided p+ /n shallow junctions     

The reverse anneal of junction characteristics in forming shallow p+-n junction by BF2+ implantation intothin Co films on Si substrate

Silicided shallow p⁺-n junctions, formed by BF₂ ⁺ implantation into thin Co films on Si substrates and subsequently annealed, showed a reverse anneal of junction characteristics in the temperature range between 550 and 600°C. The reverse anneal means behavior showing degradation of the considered parameters with increasing annealing temperature. A higher implant dosage caused a more distinct reverse anneal. The reverse anneal of electrical characteristics was associated with the reverse anneal of substitutional boron. A shallow p⁺-n junction with a leakage current density lower than 3 nA/cm₂, a forward ideality factor of better than 1.01, and a junction depth of about 0.1 μm was achieved by just a 550°C anneal     

Low-temperature fabrication of p+-n diodes with300-Å junction depth

Gas immersion laser doping (GILD) was used to fabricate p⁺ -n diodes with 300-Å junction depth. These diodes exhibit ideality factors of 1.01-1.05 over seven decades of current, reverse leakage current densities ⩽10 nA/cm² at -5-V reverse bias, breakdown voltages above 100 V, and electrical activation of the boron impurity to concentrations approaching 1×10²¹ atoms/cm³. This behavior is achieved without the use of a furnace or rapid thermal anneal     

Formation of TiN/TiSi2/p+-Si/n-Si by rapid thermal annealing (RTA) silicon implanted with boron through titanium

A low temperature method of fabricating conductive (3.5 Ω/ sq.) p⁺/n junction diodes possessing excellentI-Vcharacteristics with reverse-bias leakage less than -3 nA.cm^-2at -5 V is described. Single crystal n-type 〈100〉 Si is implanted with 60 keV¹¹B+through 0.028-µm thick sputtered Ti film. Rapid thermal annealing (RTA) in an N2ambient simultaneously forms a 0.36-µm deep p⁺/n junction and a 0.063-µm thick bilayer of TiN and TiSi2with a resistivity of 22 µΩ.cm. The electrical properties of these diodes are not degraded by annealing for 30 min at 500°C, suggesting that the outer layer of TiN is an effective diffusion barrier between TiSi2and Al.     

Composite TaSi2/n+poly-Si formation by rapid thermal annealing

Composite TaSi2/n+ poly-Si structures have been formed by rapid thermal annealing (RTA). Polysilicon films 0.2 µm thick were deposited on oxidized Si wafers by LPCVD and heavily doped with phosphorus by diffusion. A layer of TaSix0.22 µm thick was then cosputtered on polysilicon from separate targets. The as-deposited samples were annealed by RTA using high-intensity tungsten lamps. Uniform stoichiometric low-resistivity tantalum disilicide was formed by RTA in 1 s at 1000°C. The sheet resistance and grain size of the silicide layers are comparable to those formed by conventional furnace anneals. The surface morphology of the RTA samples is superior to that obtained by furnace annealing. These results show that RTA technique has a great potential for low-resistivity tantalum silicide formation in VLSI circuits.     

Enhancement of oxide break-up by implantation of fluorine inpoly-Si emitter contacted p+-n shallow junctionformation

In this study, it is demonstrated that the incorporation of fluorine can enhance poly-Si/Si interfacial oxide break-up in the poly-Si emitter contacted p⁺-n shallow junction formation. The annealing temperature for breaking up the poly-Si/Si interfacial oxide has been found to be as low as 900°C. As a result, the junction depth of the BF₂-implanted device is much larger than that of the boron-implanted device     

Improving low-temperature APCVD SiO2 passivation byrapid thermal annealing for Si devices

The quality of low-temperature (≈400°C) atmospheric pressure chemical vapor deposited (APCVD) silicon dioxide (SiO₂ ) films has been improved by a short time rapid thermal annealing (RTA) step. The RTA step followed by a low temperature (400°C) forming gas anneal (FGA) results in a well-passivated Si-SiO₂ interface, comparable to thermally grown conventional oxides. Efficient and stable surface passivation is obtained by this technique on virgin silicon as well as on photovoltaic devices with diffused (n⁺p) emitter surface while maintaining a very low thermal budget. Device parameters are improved by this APCVD/RTA/FGA passivation process     

p+-n junction formed by dual implantation of Zn and As in GaAs junction field-effect transistors

The performance of a p+-n junction formed in GaAs by dual implantation of Zn and As was investigated. The transconductance in linear operation of the junction field-effect transistors (JFET's) in which the p+-gate was formed by the dual implantation was measured and analyzed on a simple one-dimensional model. As the dose of As was increased, the devices showed negatively shifted pinchoff voltage and higher transconductance. It was found that the co-implantation of As significantly decreased the width of the compensated layer in the junction, which improved the JFET's performance.     

Integral heat-sink IMPATT diodes fabricated using p+etch stop

The problems in batch fabrication of integral heat-sink IMPATT diodes are greatly simplified through a newly developed preferential etching technique. Devices fabricated utilizing the new technique have thermal resistance (θjc) values of 17-20°C/W for an active area of 2 × 10^-4cm².