Sub-100 nm CMOS circuit performance with high-K gate dielectrics

In this paper we look at the effect of fringing fields on the circuit performance by use of high permittivity (K) gate dielectrics in 70 nm CMOS technologies, from Monte-Carlo and mixed-mode simulations. Our results clearly show a decrease in the external fringing capacitance and an increase in the internal fringing capacitance, when the conventional SiO₂ is replaced by high-K gate dielectrics. It also indicates an optimum K value for a given technology generation in terms of circuit and device short-channel performance.     

Copper-dielectric cap interface with enhanced reliability for 45 nm technology and beyond

A production capable preparation of a Cu-dielectric cap interface with a significantly enhanced reliability robustness has been developed for the 45 nm dual damascene technology and beyond. The electromigration (EM) lifetime could be improved by a factor of 2 with an advanced in situ cleaning process (ACP) including a soft silicidation step of the Cu metallization prior to the Cu-cap deposition. The increase of the Cu metal line resistivity can be controlled and limited to <6%. Anneal experiments at high temperature underline a high thermal stability of the Cu-cap interface including the copper-silicide (CuSi) intralayer. The new ACP is applicable to Cu interconnects built with dense or porous ultra-low-k (ULK) dielectrics because the process minimizes the surface damage. This yields in a doubled dielectric breakdown strength of a Cu damascene structure with a ULK inter-level dielectric by implementation of the ACP.     

Air-Gaps for High-Performance On-Chip Interconnect Part II: Modeling, Fabrication, and Characterization

Air-gaps are the ultimate low-k material in microelectronics due to air having a low dielectric constant close to 1.0. The interconnect capacitance can further be reduced by extending the air-gaps into the interlayer dielectric region to reduce the fringing electric field. An electrostatic model (200 nm half-pitch interconnect with an aspect ratio of 2.0), was used to evaluate the dielectric properties of the air-gap structures. The incorporation of air-gaps into the intrametal dielectric region reduced the capacitance by 39% compared with SiO₂. Extending the air-gap 100 nm into the top and bottom interlayer SiO₂ region lowered the capacitance by 49%. The ability to fabricate air-gaps and ‹extended air-gaps’ was demonstrated, and the capacitance decrease was experimentally verified. Cu/air-gap and extended Cu/air-gap interconnect structures were fabricated using high-modulus tetracyclododecene (TD)-based sacrificial polymer. The aspect ratio of the air-gap was 1.8 and the air-gap was extended 80 nm and 100 nm into the top and bottom interlevel SiO₂ region, respectively. The measured effective dielectric constant (k _eff) of the Cu/air-gap and the extended Cu/air-gap structures with SiO₂ interlevel dielectric was 2.42 and 2.17, respectively. The effect of moisture uptake within the extended Cu/air-gap structure was investigated. As the relative humidity increased from 4% to 92%, the k _eff increased by 7%. Hexamethyldisilazane was used to remove adsorbed moisture and create a hydrophobic termination within the air-cavities, which lowered the effect of humidity on the k _eff. A dual Damascene air-gap and extended air-gap fabrication processes were proposed and the challenges of using a sacrificial polymer placeholder approach to form air-cavities are compared to other integration approaches of dual Damascene air-gap.     

Process damage-free damascene metal gate technology for gentle integration of epitaxially grown high-k

This paper presents the first successful attempt to integrate crystalline high-k gate dielectrics into a virtually damage-free damascene metal gate process. Process details as well as initial electrical characterization results on fully functional gate Gd₂O₃ dielectric MOSFETs with equivalent oxide thickness (EOT) down to 1.9 nm are discussed and compared with devices with rare-earth gate dielectrics fabricated previously in a conventional CMOS process.     

Weight-scale, XRR and corona charge method on back-end dielectrics for 65 and 45 nm technology nodes

The monitoring of the back-end dielectrics for 65 and 45 nm technology nodes is of great interest to ensure the integration of those materials into damascene structure. Several metrology methods were compared for density and k value measurements. It was shown that the densities measured with XRR and weight-scale were identical and that density could be correlated to corona charge method k value thanks to a Clausius-Mosotti-like relation. According to these results, it appeared that, for uniformly deposited and stable materials, weight-scale measurements can give accurate and fast monitorings. On the contrary, non-homogeneous materials should preferably be monitored with XRR or corona charge method depending on the controlled parameter.     

Electrical characterization of high-k gate dielectrics fabricated using plasma oxidation and post-deposition annealing of a Hf/SiO2/Si structure

High permittivity (high-k) gate dielectrics were fabricated using the plasma oxidation of Hf metal/SiO₂/Si followed by the post-deposition annealing (PDA), which induced a solid-phase reaction between HfO_x and SiO₂. The oxidation time and PDA temperature affected the equivalent oxide thickness (EOT) and the leakage current density of the high-k dielectric films. The interfacial structure of the high-k dielectric film/Si was transformed from HfO_x/SiO₂/Si to HfSi_xO_y/Si after the PDA, which led to a reduction in EOT to 1.15 nm due to a decrease in the thickness of SiO₂. These high-k dielectric film structures were investigated by X-ray photoelectron spectroscopy. The leakage current density of high-k dielectric film was approximately four orders of magnitude lower than that of SiO₂.     

A study of post-etch wet clean on electrical and reliability performance of Cu/low k interconnections

Integration of Cu with low k dielectrics has gained wide acceptance for 130 nm and beyond technology nodes at back-end-of-line (BEOL) interconnection in order to reduce both the RC delay and parasitic capacitance. Wet clean is one of the critical steps to remove post plasma etch residues. In this paper, the impacts of wet clean process after etching of (a) via, (b) metal 2 trench and (c) Cu cap of dual damascene structure on electrical performance of 130 nm Cu/CVD low k SiOCH metallization were explored and discussed. Electrical yields and dielectric breakdown strength of interconnects from the use of batch spray and single wafer processing systems of wet clean were also compared. We observed that electrical yields of interconnects were considerably dependant on optimized processing conditions (temperature, time, and mega-sonic power) and appropriate wet clean chemistry. The use of fluoride-based mixture of wet clean chemical for all three post-etch clean is very effective in cleaning the via and trench line before Ta barrier/Cu seed deposition. As a result, we successfully integrated double level Cu/CVD low k BEOL interconnection with excellent electrical and reliability performance.     

Challenges for dielectric materials in future integrated circuit technologies

Dielectrics provide crucial functions in integrated circuits as gate dielectrics, transistor isolation structures, memory elements, interlevel dielectrics, and also provide charge storage in fast capacitors for power isolation. As the feature sizes of integrated circuits continues to decrease and speed increases, the performance requirements for these dielectrics increases significantly. Conventional materials such as thermal and CVD SiO₂ are being replaced with new materials such as high k gate dielectrics, and carbon doped SiO₂ for low k interlevel dielectrics. Even in package level power isolation capacitors, improvements in performance are becoming more difficult and new materials are needed. The challenges to dielectric materials will become even more severe as the industry approaches the l0 nm generation. In each of these applications, the requirements and integration issues are different, and this paper will highlight the long-term challenges for different applications of high k and low k materials. Nanotechnology has the potential to deliver new nano-structured materials to support these requirements, but significant challenges must be overcome before they can be useful.     

A new method for extracting the effective channel length of MOSFETs

A new and simple method to extract the effective channel length L_eff of metal-oxide superconductor field effect transistor (MOSFET)s is presented. The method, which is developed based on an auxiliary integral function, has the advantage of determining the value of L_eff not influenced by the series resistances of the MOSFET. The method is tested in the environments of device simulation and measurements. In addition, comparison is made between the results obtained from the present method and a widely used L_eff extraction method.     

Tuning the dielectric properties of hafnium silicate films

The influence of Si concentration in hafnium silicate dielectrics on thermal stability and dielectric permittivity was analyzed. A phase diagram was developed using GIXRD and FTIR measurement. The stabilization of the “higher-k” cubic/tetragonal phase for annealing temperatures up to 1000 °C with a steady increase in capacitance was demonstrated for Hf_0.94Si_0.06O₂ films. It was also shown that the stabilization of nano-crystalline Hf_0.80Si_0.20O₂ films can be realized for annealing temperatures up to 900 °C. The influence of TiN electrodes on the dielectric constant and the leakage current characteristic was also investigated. A permittivity increase for annealing temperatures up to 1000 °C without degradation of leakage current was shown.     

Study and improvement of electrical performance of 130 nm Cu/CVD low k SiOCH interconnect related to via etch process

130 nm technology uses Cu/low k dielectrics integration for the back-end-of-line (BEOL) process. The motivation of this work was to assess and improve the electrical yields of dense via chains through the study of effects of via etch process splits. We also demonstrate successful wafer fabrication of two Cu-level interconnects with chemical vapor deposited (CVD) low k SiOCH material using dual damascene architecture processed on 200 mm wafers. As a result, we achieved excellent wafer level electrical yields for both dense via chains and metal bridging-continuity structures of the BEOL interconnections.     

Challenges of Ta2O5 as high-k dielectric for nanoscale DRAMs

The present status, successes, challenges and future of Ta₂O₅, and mixed Ta₂O₅-based high-k layers as active component in storage capacitors of nanoscale DRAMs are discussed. The engineering of new Ta₂O₅-based dielectrics (doped Ta₂O₅ and multicomponent Ta₂O₅-based high-k dielectrics) as well as of metal/high-k interface in MIM capacitor configuration are identified as critical factors for further reduction of EOT value below 1 nm.     

Accurate determination of flat band voltage in advanced MOS structure

This study concerns the accurate and automatic extraction of the flat band voltage (V_fb) from CV measurements in MOS structures. By comparison to Quantum CV simulator, it focalizes on the experimental conditions needed for an accurate determination of V_fb with various analytical methods. First, we demonstrate that an accurate determination of substrate doping level is crucial. Second, the so called Maserjian’s method appears to be more reliable when the maximum measurable capacitance is reduced; it is also less sensitive to variations of the depletion bias used for extraction of substrate doping level. Third, with non-constant substrate doping profile, significant source of error can be induced by uncertainty on the effective doping level at flat band conditions. A simple rule between doping gradient and surface doping level is proposed to ensure reliable extraction.     

Efficiency of reducing and oxidizing ash plasmas in preventing metallic barrier diffusion into porous SiOCH

This work focuses on the efficiency of reducing and oxidizing plasma chemistries in preventing metallic barrier diffusion into porous dielectric materials (SiOCH with a k value close to 2.2, porosity content around 40%). The ash processes have been performed on SiOCH coated blanket and patterned wafers in either reactive ion etching (RIE) or downstream (DS) reactors. The Rutherford backscattering spectroscopy technique (RBS) has shown that titanium based compounds diffuse into the blanket porous SiOCH without treatment during a typical TiN barrier deposition process by chemical vapor deposition (CVD). The metallic barrier diffusion is strongly limited on blanket wafers when the porous SiOCH has been previously modified (partially or fully) by ash plasmas (RIE-O₂, RIE-NH₃, DS-H₂/N₂ and DS-O₂/N₂) while the metallic barrier diffusion occurs with no modifying ash plasmas (DS-H₂/He). We have shown that ellipsometric porosimetry (EP) measurements clearly point out that no complete pore sealing is achieved with all the investigated ash plasmas. Energy-filtering transmission electron microscopy experiments (EFTEM) performed on single damascene structures have revealed significant titanium diffusion into the porous dielectric lines for DS-H₂/He and RIE-O₂ and sidewalls modification of the porous SiOCH lines (lower C/O ratio) for all the ash plasmas. The RC product (resistance × capacitance) have been extracted from the single damascene structures and the evolution of RC product will be discussed in terms of lines modification (titanium diffusion and porous SiOCH modification).     

Electrical characterization of crystalline Gd2O3 gate dielectric MOSFETs fabricated by damascene metal gate technology

This paper presents the first successful attempt to integrate crystalline high-K gate dielectrics into a virtually damage-free damascene metal gate process. Process details as well as initial electrical characterization results on fully functional gate Gd₂O₃ dielectric MOSFETs with equivalent oxide thickness down to 1.9 nm are discussed.     

Scaling the MOSFET gate dielectric: From high-k to higher-k? (Invited Paper)

We discuss options for metal–oxide-semiconductor field-effect transistor (MOSFET) gate stack scaling with thin titanium nitride metal gate electrodes and high-permittivity (‘high-k’) gate dielectrics, aimed at gate-first integration schemes. Both options are based on further increasing permittivity of the dielectric stack. First, we show that hafnium-based stacks such as TiN/HfO₂ can be scaled to capacitance equivalent thickness in inversion (T_inv) of 10 Å and equivalent oxide thickness (EOT) of 6 Å by using silicon nitride instead of silicon oxide as a high-k/channel interfacial layer. This is based on the higher dielectric constant of Si₃N₄ and on its resistance to oxidation. Although the nitrogen introduces positive fixed charges, carrier mobility is not degraded. Secondly, we investigate whether Ti-based ‘higher-k’ dielectrics have the potential to ultimately replace Hf. We discuss oxygen loss from TiO₂ as a main challenge, and identify two migration pathways for such oxygen atoms: In addition to well-known down-diffusion and channel Si oxidation, we have newly observed oxygen up-diffusion through the TiN metal gate, forming SiO₂ at the poly-Si contact. We further address the performance of Si₃N₄ and HfO₂ as oxygen barrier layers.     

Gate leakage properties of MOS devices with tri-layer high-k gate dielectric

Gate leakage of deep-submicron MOSFET with stack high-k dielectrics as gate insulator is studied by building a model of tunneling current. Validity of the model is checked when it is used for MOSFET with SiO₂ and high-k dielectric material as gate dielectrics, respectively, and simulated results exhibit good agreement with experimental data. The model is successfully used for a tri-layer gate-dielectric structure of HfON/HfO₂/HfSiON with a U-shape nitrogen profile and a like-Si/SiO₂ interface, which is proposed to solve the problems of boron diffusion into channel region and high interface-state density between Si and high-k dielectric. By using the model, the optimum structural parameters of the tri-layer dielectric can be determined. For example, for an equivalent oxide thickness of 2.0 nm, the tri-layer gate-dielectric MOS capacitor with 0.3-nm HfON, 0.5-nm HfO₂ and 1.2-nm HfSiON exhibits the lowest gate leakage.     

The effect of oxygen in Ru gate electrode on effective work function of Ru/HfO2 stack structure

Effective work function (φ_m,eff) values of Ru gate electrode on SiO₂ and HfO₂ MOS capacitors were carefully examined and discussed from the viewpoint of an effect of oxygen incorporation in Ru gate electrode on φ_m,eff. Annealing at 400 °C in the reduction (3%H₂) and the oxidation (1%O₂) ambient resulted in similar changes in the φ_m,eff of Ru/HfO₂/SiO₂ and Ru/SiO₂ MOS capacitors. Furthermore, the Ru gate MOS capacitor after annealing in the oxidation condition have shown almost the same φ_m,eff value to that of RuO₂ gate MOS capacitors. The oxygen concentration in the Ru/HfO₂ interface after annealing in oxidizing atmosphere is approximately one order of magnitude higher than that after annealing in reducing atmosphere as confirmed by secondary ion mass spectroscopy analysis. Furthermore, the higher oxygen concentration at the Ru/dielectric interface leads to the higher φ_m,eff value, regardless of SiO₂ or HfO₂ dielectrics. This indicates that φ_m,eff of Ru gate MOS capacitor is dominantly determined by the oxygen concentration at the Ru/dielectric layer interface rather than the dipoles originated from the oxygen vacancy in HfO₂.     

Conduction mechanisms of silicon oxide/titanium oxide MOS stack structures

During the last years, high-k dielectrics have been studied intensively looking for an alternative material to replace the SiO₂ films as gate dielectric in MOS transistors. Different materials and structures have been proposed. An important concern not yet solved, is the interfacial quality between high-k materials and silicon substrate. For this reason, stack structures with SiO₂ as an interfacial layer between silicon substrate and high-k film have been studied. In this contribution we analyze the main conduction mechanism observed in SiO₂/TiO₂ MOS stack structures obtained by room temperature plasma oxidation in different conditions and reactors. Films fabricated in a parallel-plate type reactor showed better quality with low current density where thermionic conduction mechanism is predominant. In lower quality films, for example those fabricated in a barrel type equipment, the current density is higher and the conduction mechanism observed is Poole–Frenkel. Finally we show that the presence of thermionic mechanism provides a weak thickness dependence and a strong current density reduction with respect to silicon oxide MOS structures with the same equivalent oxide thickness.     

Effective Permittivity Calculation of Composites with Interpenetrating Phases

The effective permittivity of composites with interpenetrating phases was determined through finite-element simulation. The spectra of effective permittivity for such composites were calculated, and relationships among the effective permittivity ε _eff, permittivity ratio x of the matrix to network phase, and volume fraction of the network f were developed using the numerical results. The simulation has been validated by comparing the results with previously published experiments, and excellent agreement has been achieved. The electric field distributions in the composites were also explored in this work.