具有侧面柱状结构的高压LED芯片制备

设计制作了一种具有侧面柱状结构的高压发光二极 管(HV-LED)芯片,与未作侧面柱状结构的HV-LED芯片相比, 在正向电流20mA下,其光功率提高了7.6%,而正向电压和波长基 本维持不变。对这两种HV-LED 芯片的电流和电压以及电流和光功率的关系进行研究。封装白光后的测试结果表明,在色温 4500K、 驱动 电流20mA下, 具有侧面柱状结构的HV-LED芯片光效达 125. 6lm/W。在标准测试温度为20℃、正向电流为20mA驱动下,具有侧面柱状结构的HV-LED芯片封装老化测试1000h后,光衰仅为2%。     

利复星药物与牛血清白蛋白作用的荧光光谱研究

以荧光光谱为手段,研究了药物利复星(Levofloxacin)与牛血清白蛋白(BSA)的作用和影响,研究了它的荧光淬灭现象.在向该溶液滴加利复星时,观察不到激发峰的明显移动,而发射峰出现了新颖的现象,原有的353.1 nm的发射峰强度明显的减弱;新出现了峰位位于450.4 nm的新的荧光发射峰.利复星-BSA体系的猝灭过程不是因为分子扩散和碰撞所引起的动态猝灭,而是分子之间结合形成了化合物所引起的静态猝灭.利复星的离解常数为Kd=3.39×10-5mol/L.利复星的能量转移效率为50%时给体和受体之间距离的R0=1.81×10-7cm,利复星和牛血清白蛋白的能量转移效率为E=0.351,根据这些计算结果可以知道利复星和牛血清白蛋白的色氨酸残基的结合位置为r=2.01×10-7cm.     

High performance electric-double-layer amorphous IGZO thin-film transistors gated with hydrated bovine serum albumin protein

Device performance of amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) has been improved greatly by using bovine serum albumin (BSA) as the top gate dielectric. BSA is a natural protein with acidic and basic amino acid residues, which is easily hydrated in air ambient. A typical a-IGZO TFT with hydrated BSA as the top gate dielectric exhibits a field-effect mobility (μ_FE) value of 113.5 cm² V⁻¹ s⁻¹ in saturation regime and a threshold voltage (V_TH) value of 0.25 V in air ambient. The excellent device performance can be well explained by the formation of electric double layers (EDLs) near the interfaces of a-IGZO/hydrated BSA and hydrated BSA/gate electrode. The reliability issue of a-IGZO TFTs gated with hydrated BSA has been also investigated by using the life time test without encapsulation. The V_TH value increases and μ_FE,sat value reduces slightly for the a-IGZO TFT and remain stabilized over 60 days.     

Hydrated bovine serum albumin as the gate dielectric material for organic field-effect transistors

Bovine serum albumin (BSA) is a natural protein with good hydration ability which contains acidic and basic amino acid residues of ca. 34% in total. In vacuum, pentacene organic field-effect transistors (OFETs) with BSA as the gate dielectric exhibits a field-effect mobility value (μ_FE,sat) of 0.3 cm² V⁻¹ s⁻¹ in the saturation regime and a threshold voltage (V_TH) of ca. −16 V. BSA is easy to be hydrated in air ambient. Electrical properties of BSA in vacuum and hydrated BSA in air ambient are characterized. Similar to polyelectrolyte, hydrated BSA may act the gate dielectric with the formation of electric double-layer capacitors (EDLCs) to improve the device performance. In a relative humidity of 47%, the μ_FE,sat value increases to 4.7 cm² V⁻¹ s⁻¹ and the V_TH reduces to −0.7 V. Generation of mobile ions in hydrated BSA and the formation of EDLCs are discussed.     

牛血清蛋白在亲水硅片表面吸附的原子力显微成像

本文用原子力显微术（AFM）研究了牛血清白蛋白（BSA）在亲水硅片表面的吸附，硅片表面经亲水处理后，将牛血清蛋白（BSA）吸附在表面，采用轻敲模式，可获得清晰的AFM图像，牛血清蛋白（BSA）的AFM图像表明：BSA在亲水硅片表面是单分子，水平吸附在硅片表面，且吸颗粒状；1mg/ml的BSA在吸附30min后为饱和吸附。BSA到达硅表面后，蛋白中可移动的带正电荷的基团可以趋向亲水表面，使BSA与硅表面的静电相互作用由斥力变为吸引力，BSA可以稳定地吸附在亲水硅片表面。     

Fabrication and characterization of NEMS

We proposed a called“nano-fabrication based on MEMS technology”approach to realize the typical nano-electro- mechanical structures,such as integrated nano probe,ultrathin cantilever,silicon nano wire,and doubly clamped nano beam, to demonstrate the feasibility and advantages.We also introduced the characterization of nano structures based on laser vibrometer and piezoresistive effect,the latter method was first time applied to investigate a doubly daped nanobeam with a thickness of about 200 nm.     

Fabrication and characterization of the amorphous-silicon staticinduction transistor

Experimental results for the fabrication and electrical characterization of a hydrogenated amorphous silicon static induction transistor are reported. The I-V measurements demonstrate the triode-like enhancement mode operation of the device and show an on-off current ratio of 300 and a pinchoff voltage of -9.5 V for V_ds=6 V. Numerical simulation suggests that the differences between experimental and theoretically predicted results are due to the presence of a high-density-of-states layer at the a-Si:H/a-Si:H interface     

铁电微管的制备与表征

采用化学浸润法在多孔硅模板上制备了锆钛酸铅(PbZr0.52Ti0.48O3,PZT)铁电微管,X射线衍射分析表明铁电微管为钙钛矿结构.运用扫描电子显微镜和原子力显微镜对铁电微管的微现形貌进行了观察,其姑果显示两种方法所测得的铁电微管直径不同.利用压电响应力显微镜观察到了铁电微管的电畴图像,并测得了铁电微管的微区电滞回...     

A step forward in the transient thermal characterization of chips and packages

Generating compact dynamic thermal models is a key issue in the thermal characterization of packages. A further but related problem is the modeling of the thermal coupling between chip locations, for the use in electro-thermal circuit simulators. The paper presents a measurement based method which provides a way to solve both problems. A thermal benchmark chip has been designed and realized, to facilitate thermal transient measurements. The developed evaluation method provides the compact thermal multiport model of the IC chip including package effects, for the accurate electro-thermal simulation of the ICs. The evaluation method is also suitable to generate the compact thermal model of the package.     

Fabrication and characterization of neodymium-doped glasswaveguides

Waveguides prepared in neodymium-doped lithium-silicate glass by silver-ion exchange are discussed. Refractive index change and diffusion coefficient due to ion exchange are determined. It is observed that silver-ion exchange does not influence the emission wavelength of neodymium-doped glass     

Fabrication and characterization of a planar interleaved micro-transformer with magnetic core

This paper presents the design, the fabrication and the characterization of a planar interleaved micro-transformer with an Yttrium Iron Garnet (YIG) core. The design of this micro-transformer and the manufacturing steps are presented. HFSS software is used for the conception and the simulation of the interleaved magnetic micro-transformer. It is composed of two identical windings. A bottom magnetic core is used to improve the integrated transformer performances. To form the windings, we have used a surface micromachining process. We have also used a negative photoresist (SU-8) as an insulating layer and as support for the fabrication of a bridge to connect the central end of the coils to the ground shield. The micro-transformer have been characterized with impedance meter up to 100 MHz, and completed to 1 GHz using vector network analyzer.     

Fabrication and characterization of lateral field-emitter triodes

The author fabricated a field-emitter triode with tungsten electrodes arranged laterally on a quartz glass substrate by using the photolithography and dry etching techniques. The device consists of an array of 170 field-emitter tips with a 10-μm pitch, a columnar gate, and an anode. The emission characteristics followed the Fowler-Nordheim tunneling theory. The mutual conductance was about 0.02 μS at an anode voltage of 300 V. The authors improved the fabrication process to obtain an emitter with an operating voltage of about 100 V     

Fabrication and characterization of nanowire transistors with solid-phase crystallized poly-Si channels

The performance of thin-film transistors with a novel poly-Si nanowire channel prepared by solid-phase crystallization is investigated in this paper. As compared with conventional planar devices having self-aligned source/drain, the new devices show an improved on-current per unit width and better control over the short channel effects. The major conduction mechanism of the off-state leakage is identified as the gate-induced drain leakage, and it is closely related to the source/drain implant condition and the unique device structure.     

四脚针状ZnO纳米结构的制备及表征

采用以Zn粉、C粉为原料,采用热蒸发法,在没有任何载气和700℃下制备了四脚针状ZnO纳米结构。C粉起到了催化剂的作用但产物却不存在催化剂去除的问题,同时C粉氧化生成的CO/CO2还起到了载气的作用。扫描电镜(SEM)表明,四脚针状ZnO具有很细的尖端,直径为50 nm。X射线衍射(XRD)、微区拉曼图谱的特征峰表明,四脚针状ZnO是高纯的六角纤锌矿结构。光致发光(PL)谱在403 nm附近有微弱的紫光发射峰,而在510 nm附近出现了很强的绿光发射峰。     

Fabrication and characterization of microscale heat sinks

In the field of thermal management, engineers are well aware of the challenges posed by the increasing level of dissipation. Among the many possible solutions to counter the threat of overheating, one is dealing with the usage of microscale heat sinks, where the forced air or liquid cooling solution is integrated into the electronic package itself. As the System-on-Package integration is not a straightforward task, many fabrication steps have to be fully developed before a successful chip-level cooling system is ready to be used. In this paper, as one of these many steps, we present a refined manufacturing technology which offers the possibility to create the microscale heatsink integrated together with the electronic devices. With the refined manufacturing technology, several channel patterns can be created relatively easily. Nevertheless, only simple channel patterns with integrated diodes are presented now which are tested with an enhanced thermal characterization method developed for microchannel based cooling structures in the last years.     

Fabrication and electrical characterization of phase-change memory devices with nanoscale self-heating-channel structures

We proposed a material composition and an optimized patterning process for the phase-change memory devices with a nanoscale self-heating channel (NSC) structures. As a suitable composition, Ge₁₈Sb₃₉Te₄₃ was employed, which is the 22% Sb-excessive phase compared with the conventional Ge₂Sb₂Te₅. For fabricating the NSC memory devices, Ge₁₈Sb₃₉Te₄₃ layer was patterned into a thin channel having enlarged pad areas at both sides end by the developed two-step dry etching technique using a TiN hard mask. The NSC memory devices showed such good behaviors as lower power operations without any degradation of switching speed and better endurance for cyclic rewritings even in the scaling regime of tens-of-nanometer size. It can be concluded from the obtained results that the proposed NSC memory devices promise the feasibility for realizing both aggressive scaling with a simpler process and enhanced memory performances for the phase-change nonvolatile memory applications.     

Fabrication and characterization of a new EEPROM cell with spacer select transistor

In this letter, process technology and cell characteristics of a newly developed compact electrically erasable programmable read only memory cell are described. The cell has spacer select gates on both side walls of floating gate and this gives a very small cell size as well as relief of topology during contact formation. The cell size is 0.95 /spl mu/m/sup 2/ with 0.18 /spl mu/m logic process. The cells are programmed and erased by Fowler-Nordheim tunneling. It appears that programming requires 3 ms at 16 V while erasing requires 2 ms at 14 V. It is shown that the cells have very uniform distribution of both programmed and erased threshold voltage. It is also shown that the cell endures up to half million cycling tests.     

Fabrication and characterization of CdZnTe radiation detectors with a new P-I-N design

We report on the design, fabrication, and performance of CdZnTe gamma-ray detectors with a new P-I-N structure for spectroscopic applications. Highpressure and conventional vertical-Bridgman CdZnTe crystals were used for detector fabrication. P and n layers were deposited by thermal evaporation, and by optimizing the deposition conditions we achieved low leakage current (approximately 15 nA at 1000 V) and good performance. Spectral response data at high bias voltages showed improved energy resolution and peak-to-valley ratios for ²⁴¹Am and ⁵⁷Co compared to metal-semiconductor-metal detectors.     

Fabrication and characterization of fin SONOS flash memory with separated double-gate structure

In this work, we have fabricated and characterized the 3-dimensional fin SONOS flash memory. This device has two independent gates on both sides of Si-fin and each of them governs two side-channels. Fabrication flow and array structure are described as well as operation schemes. The 4-bit/cell operation is demonstrated with the multi-bit concept in fabricated devices. Some fabrication issues related with device characteristics and reliabilities are delivered.     

Fabrication and characterization of field-plated buried-gate SiC MESFETs

Silicon carbide (SiC) MESFETs were fabricated using a standard SiC MESFET structure with the application of the "buried-channel" and field-plate (FP) techniques in the process. FPs combined with a buried-gate are shown to be favorable concerning output power density and power-added efficiency (PAE), due to higher breakdown voltage and decreased output conductance. A very high power density of 7.8 W/mm was measured on-wafer at 3 GHz for a two-finger 400-/spl mu/m gate periphery SiC MESFET. The PAE for this device was 70% at class AB bias. Two-tone measurements at 3 GHz /spl plusmn/ 100 kHz indicate an optimum FP length for high linearity operation.