A programmable FIR digital filter using CSD coefficients

An area-efficient programmable FIR digital filter using canonic signed-digit (CSD) coefficients was implemented that uses a switchable unit-delay to allocate the desired number of nonzero CSD coefficient digits to each filter tap. The prototype chip can allocate up to 16 pairs of nonzero CSD coefficient digits for a linear-phase filter, thus realizing filters with 32 linear-phase taps operating at 180 MHz with two nonzero CSD digits per filter tap. Additional nonzero CSD digits can be allocated to filter taps at the penalty of a reduced filter length and a reduced data-rate. The chip was implemented with 16-bit I/O in a die size of 5.9 mm by 3.4 mm using 1.0-μm CMOS technology     

A quadrature charge-domain sampler with embedded FIR and IIR filtering functions

A circuit technique for integrating built-in complex finite-impulse-response (FIR) and infinite-impulse-response (IIR) filtering functions into operation of a subsampler is presented. Based on integrative multiple sampling in the charge domain, the complex FIR filtering function of the sampler provides internal anti-aliasing and image band suppression prior to quadrature downconversion by subsampling. The complex IIR filtering function, taking place at the output sampling rate of the sampler, performs further first-order channel selection filtering on the downconverted signal. An example 50-MHz IF-sampler implementation in 0.8-/spl mu/m BiCMOS demonstrating the feasibility of the technique is presented in the paper.     

A high-speed programmable CMOS interface system combining D/Aconversion and FIR filtering

This paper describes the design, integrated circuit realization, and experimental characterization of a high-speed programmable interface system combining the functions of digital-to-analog (D/A) conversion and FIR filtering. The system comprises four high-speed digital delay lines, with programmable delay length, together with four high-speed steering-current D/A converters with independent digitally-programmable gains. A demonstration prototype chip has been fabricated in a 1.2-μm digital CMOS technology. At 54 MHz conversion rate and digital delay lines clocked at 18 MHz, it consumes 115 mW for a full-scale output current of 13.3 mA at 5 V supply     

An FIR processor with programmable dynamic data ranges

This work developed a modified direct form based on the radix-4 Booth algorithm to realize a finite impulse response (FIR) architecture with programmable dynamic ranges of input data and filter coefficients. This architecture comprises a preprocessing unit, data latches, configurable connection units, double Booth decoders, coefficient registers, a path control unit, and a postprocessing unit. Programmable dynamic ranges of input data and filter coefficients can be any positive even numbers or multiple of a word length of coefficient registers, using configurable connection units or a path control unit, respectively. In particular, the proposed architecture employs only data-path controls to accomplish programmable operations, without changing word lengths and components of data latches and filter taps. A practical 8-bit and 16-bit FIR processor has also been implemented by using the TSMC 5 V 0.6 μm CMOS technology. It is suitable for operations of asymmetric, symmetric, and anti-symmetric filters at 64, 63, 32, 31, and 16 taps, and is well explored to optimize its functional units. The proposed processor has throughput rates of 50 M and 25 M samples/s for 8-bit and 16-bit input data of various filter applications, respectively     

A configurable convolution chip with programmable coefficients

Describes the architecture and implementation of a bit-level configurable convolver array. The systolic field supports a configuration during operation in terms of number of taps and coefficient word length. A chip has been designed in 1.5- mu m CMOS using a full-custom design style which contains 112586 transistors on an active area of 46 mm/sup 2/. The configurability consumes only 9% of that area. The prototypes are shown to be fully functional up to 20 MHz. An extension of the architecture for optimized calculation of transformations is also presented.<>     

Digitally programmable switched-current FIR filter for low-voltageapplications

In this paper, we describe a switched-current (SI) finite-impulse response (FIR) filter, suitable for equalizer architectures. The basic cell of the FIR filter is a SI sample-hold (S/H) circuit, appropriate for low-voltage operation. The programmability of the FIR filter structure is achieved via MOSFET-only current dividers. The FIR filter has been designed and implemented using a 0.8 μm CMOS process and operates at a power-supply voltage of 2 V     

Low-power realization of FIR filters on programmable DSPs

This paper addresses the problem of reducing power dissipation of finite impulse response (FIR) filters implemented on programmable digital signal processors (DSPs). We describe a generic DSP architecture and identify the main sources of power dissipation during FIR filtering. We present seven transformations to reduce power dissipated in one or more of these sources. These transformations complement each other and together operate at algorithmic, architectural, logic and layout levels of design abstraction. Each of the transformations is discussed in detail and the results are presented to highlight its effectiveness. We show that the power dissipation can be reduced by more than 40% using these transforms. The transformations have been encapsulated in a framework that provides a comprehensive solution to low-power realization of FIR filters on programmable DSP's     

Narrow-band FIR filtering with FPGAs using sigma-delta modulation encoding

This paper addresses the problem of implementing narrow-band FIR filters using FPGAs. Rather than employing a conventional multiply-accumulate unit to compute the inner-product, an alternative method based on re-quantization of the input data stream using a sigma-delta modulator is presented. The re-quantization process preserves the dynamic range of the signal components contained in the bandwidth of the filter, while shifting the re-quantization noise to the spectral region to be rejected by the filter. The reduced bit length representation of the re-quantized input data samples removes the requirment for a full multiplier in the filter hardware. This makes the method very attractive for realization using FPGA technology. The filtering technique is described and implementation results using a Xilinx XC4010 FPGA are presented. A 200-tap filter implemented in a single FPGA achieves a computation rate of 415 MOPS and has a memory bandwidth of 1.66 Gbytes/s. An extension of the method using a quadrature re-quantizer and filter is also presented.     

Strictly passive FIR filtering for state-space models with external disturbance

This paper proposes a new strictly passive filter with a finite impulse response (FIR) structure for linear state-space signal models with external disturbance. This filter is called a strictly passive FIR filter (SPFF). We apply the strict passivity concept to derive a new linear filter with FIR structure and quasi-deadbeat property. The gain matrix of the proposed SPFF in this paper can be determined by resorting to the solution to a linear matrix inequality (LMI) feasibility problem. An illustrative example is presented to show the validity of the SPFF.     

Transposed FIR filter structure with time-varying coefficients fordigital data resampling

A new time-domain derivation is presented for interpolation and decimation by a fractional factor U/D. Though it is well known that such a filter can be implemented using a direct-form I, FIR filter with time-varying coefficients, a novel time-varying alternative, using a transposed filter structure, is described. Time-varying filters are especially important for implementation on a digital signal processor. The new time-varying structure has the advantage of reduced buffer memory for downscaling, or increased parallelism for high-speed upscaling, compared to the conventional time-varying structure     

Computation sharing programmable FIR filter for low-power and high-performance applications

This paper presents a programmable digital finite-impulse response (FIR) filter for high-performance and low-power applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically targets computation re-use in vector-scalar products and can be effectively used in the low-complexity programmable FIR filter design. Efficient circuit-level techniques, namely a new carry-select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. A 10-tap programmable FIR filter was implemented and fabricated in CMOS 0.25-/spl mu/m technology based on the proposed architectural and circuit-level techniques. The chip's core contains approximately 130 K transistors and occupies 9.93 mm/sup 2/ area.     

Use of a programmable filter for inverse filtering

A real-time deconvolution or inverse filter, operating at signal frequencies up to 5 MHz, is reported. The programmable digital filter is controlled by a computer which calculates the Wiener-filter solution using f.f.t. techniques. Deconvolved signals can be clearly discriminated after passing through a distorting medium.     

A Fast FIR filtering technique for multirate filters

This paper presents a technique for applying Fast FIR Algorithms (FFAs) to interpolation and decimation filters. In the event that the prototype filter has a symmetric impulse response, it is shown that the subfilters which result from the application of the FFA will be jointly symmetric. This fact may be exploited in order to further reduce the computational complexity of the system. The effect of transposition upon the proposed structure is discussed, and it is shown that transposition yields a more economical structure in the case of a decimation filter. The computational complexity of the proposed schemes is shown to compare favorably with that of the standard parallel filtering approach.     

A fast algorithm for FIR digital filtering with a sum-of-triangles weighting function

A doubly recursive algorithm for time domain convolution with a piecewise linear weighting function is presented that combines the speed of a recursive (IIR) digital filter with the flexibility and ease of design of a nonrecursive (FIR) digital filter. The approach approximates the desired FIR weighting function by a sum-of-triangles weighting function. ForL triangles (or triangle pairs for a linear phase filter) the algorithm is of orderLN. The approximation improves with the number of triangles. A significant advantage of the algorithm compared to FFT filtering or direct convolution is that there is no necessity of a tradeoff between frequency response accuracy and computation time per output point as the data spacing decreases in the filtered signal. The computational complexity is dependent on the number of triangles chosen, not the width of the weighting function, so the algorithm is especially effective for filters with an inherently wide FIR weighting function.     

Design of FIR linear phase filters with discrete coefficients usingHopfield neural networks

A novel method is presented for designing FIR linear phase filters with discrete coefficients using Hopfield neural networks. The proposed procedure is based on the minimisation of the energy function of the Hopfield neural network, and can produce a good solution to the design of FIR linear phase filters with discrete coefficients     

Fast algorithm for FIR filtering in the transform domain

A more efficient algorithm than the overlap-and-add (or overlap-and-save) method is developed for quickly computing the convolution involving very long impulse response. By dividing the input and the impulse response into segments of proper length, the algorithm requires fewer multiplications than the existing methods and therefore reduces the complexity of the filtering process     

Block Z transform and its application to FIR filtering

The block Z transform (BZT) is presented. It is shown that the BZT, used with the modified Fermat number transform (MFNT), is very efficient for FIR filtering of a long impulse response. The BZT takes advantage of the number theoretic transforms (NTTs), namely, the computational efficiency, and overcomes use of the restrictions on the NTTs, namely, the restriction on the length of the impulse response     

A fully programmable sampled-data analog CMOS filter with transfer-function coefficients determined by timing

A CMOS analog signal processor which is as programmable as a digital one is discussed. This processor does not use known switched-capacitor techniques, nor does it contain any selectable capacitor (or resistor) arrays. Instead, it operates on a pulsewidth control principle in which the value of each branch gain is determined by the duty cycle of a single digitally controlled analog transmission gate. A 4-/spl mu/m single-poly CMOS test IC containing all the critical analog functions was designed to demonstrate this principle at sampling frequencies up to 100 kHz. All of the processors described allow individual programming of each transfer function coefficient; one also features programmable topology, and another is capable of simultaneous multiple-signal multiple-transfer-function processing. A typical integrated fully programmable biquad shows 80-dB dynamic range.     

常系数FIR中的CSD串并乘法器设计

介绍了二进制数的Canonic Signed Digit(CSD)表示的特点,0位值比其他表示方法都要多.应用这一点在常系数的乘法器中,可以化简电路.阐述了CSD串并乘法器的具体化简过程,并应用这一技术于IS95-WCDMA中的脉冲整形23阶常系数FIR的设计中,面积缩小达42%.结果表明:CSD的化简效果是明显的.