Gate-bias assisted charge injection in organic field-effect transistors

The charge injection barriers in organic field-effect transistors (OFETs) seem to be far less critical as compared to organic light-emitting diodes (OLEDs). Counter intuitively, we show that the origin is image-force lowering of the barrier due to the gate bias at the source contact, although the corresponding gate field is perpendicular to the channel current. In coplanar OFETs, injection barriers up to 1 eV can be surmounted by increasing the gate bias, enabling extraction of bulk transport parameters in this regime. For staggered transistors, however, the injection is gate-assisted only until the gate bias is screened by the accumulation channel opposite to the source contact. The gate-assisted injection is supported by two-dimensional numerical charge transport simulations that reproduce the gate-bias dependence of the contact resistance and the typical S-shaped output curves as observed for OFETs with high injection barriers.     

Multi-gate non-volatile memories with nanowires as charge storage material

Multi-gate non-volatile memory (NVM) cell is a promising approach in the next generation. In this work, the performance of NVMs using nanocrystals (NCs) and nanowires (NWs) as charge trapping materials were evaluated by three-dimensional simulation. It is found that the NWs located at different positions have different charge injection speeds. And the NW density will strongly affect the charge injection efficiency. The NW at channel center can result in large memory window and acceptable channel controllability. Although the total charges injected into NWs is lower than that injected into NCs under the same programming condition, using NWs as charge trapping material exhibits larger memory window and better channel controllability. It is suggested that the NW is a better choice than NC to be charge storage material from the perspective of memory performance.     

低误差开关电流存储单元

详细分析了限制开关电流(SI)精度的主要误差,在共源-共栅组态存储单元的基础上,根据在开关晶体管关断前消除反型层可以改善电荷注入误差的原理,提出一种新型低误差开关电流存储单元.其主要思想是通过消除开关晶体管沟道内的可动电荷、降低存储单元的输出电导,以改善电荷注入误差和电导比误差.采用TSMC 0.25μtm CMOS模型参数进行HSPICE仿真,结果表明,该结构能够很好地降低电路误差,提高开关电流电路的精度.     

Weak inversion charge injection in analog MOS switches

The on-chip test circuit for examining the charge injection in analog MOS switches has been described in detail, and has been fabricated and characterized. Mixed-mode circuit and device simulations have been performed, creating excellent agreements not only with the experimental waveforms but also with the measured switch-induced error voltage. Further investigation of the experimental and simulated results has separated the charge injection into three distinct components: i) the channel charges in strong inversion; ii) the channel charges in weak inversion; and iii) the charges coupled through the gate-to-diffusion overlap capacitance. Important observations concerning the weak inversion charge injection have been drawn from the waveform of the current through the switched capacitor. In this work the channel charges in weak inversion have exhibited a 20% contribution to the switch-induced error voltage on a switched capacitor     

Extracting Contact Effects in Organic FETs

Contact resistances between organic semiconductors and metal electrodes have been shown to play a dominant role in electronic charge injection properties of organic FETs (OFETs). These effects are more prevalent in short channel length devices and therefore should not be ignored when examining intrinsic properties such as the mobility and its dependence on temperature or gate voltage. Here we outline a general procedure to extract contact current-voltage characteristics and the true channel mobility from the transport characteristics in bottom-contact poly (3-hexylthiophene) FETs, for both ohmic and nonlinear charge injection, over a broad range of temperatures and gate voltages. Distinguishing between the contact and channel contributions in bottom-contact OFETs is an important step toward improved understanding and modeling of these devices.     

Determination of spatial surface state density distribution in MOS and SIMOS transistors after channel hot electron injection

The charge pumping technique has been adapted for the determination of the spatial distribution of the interface state density in the channel region of short channel MOS or SIMOS transistors. This spatial distribution is shown to be modified by channel hot electron injection and provides information on the location and width of the injection region.     

Hot hole induced interface state generation and annihilation in SOIMOSFETs

The effects of pure hot hole injection in SOI MOSFET's are investigated. Pure hot hole injection is achieved by exploiting the opposite channel based carrier injection phenomenon. It is found that significant amounts of interface states are generated, some of which are annihilated by a subsequent hot electron injection pulse. A power law of the form D_it(t)=Ktⁿ with n close to 0.25 was obtained, indicating a more complex, diffusion limited, electrochemical reaction at the interface than previously reported     

埋沟CCD器件电荷处理容量的二维数值模拟

借助于二维器件模拟软件PISCES-IIB,通过在某相CCD电极下的耗尽区注入数量可控的电子电荷,对埋沟CCD器件电荷容量进行了定量分析。采用此方法对一种沟道宽度为7μm的CCD信道电荷容量进行了瞬态模拟,对不同结深、不同沟道掺杂浓度对CCD电荷容量的影响进行了讨论。得到了此结构工艺参数的初步优化结果,即CCD沟道表面掺杂浓度为结深为1 μm时,埋沟CCD的电荷容量可达文章提出的方法适用于其他CCD单元结构电荷容量的模拟。     

The leakage currents of amorphous silicon thin-film transistors: channel charge emission

The effects of channel charge emission on the transient leakage currents of amorphous silicon thin-film transistors are described. Up to one hundred devices connected in parallel are used to allow measurement of currents below 1 fA. We develop a procedure to separate the charge-emmission current from the injection and generation currents, based on the dependence on the drain-to-source voltage. The channel emission current is isolated and measured from 10/sup -3/ to 100 s after the TFT is switched off. The current decays approximately as 1/t, and provides information about the density of states in a-Si:H. The channel charge emission also influences the read-out properties of active matrix arrays.     

Effects of silicon layer properties on device reliability for0.1-μm SOI n-MOSFET design strategies

We employ an advanced simulation method to investigate the effects of silicon layer properties on hot-electron-induced reliability for two 0.1-μm SOI n-MOSFET design strategies. The simulation approach features a Monte Carlo device simulator in conjunction with commercially available process and device simulators. The two channel designs are: 1) a lightly-doped (10¹⁶ cm^-3) channel and 2) a heavily-doped (10¹⁸ cm^-3) channel. For each design, the silicon layer thicknesses (T_Si) of 30, 60, and 90 nm are considered. The devices are biased under low-voltage conditions where the drain voltage is considerably less than the Si/SiO₂ barrier height for electron injection. A comparative analysis of the Monte Carlo simulation results shows that an increase in T_Si results in decreasing hot electron injection into the back oxide in both device designs. However, electron injection into the front oxide exhibits opposite trends of increasing injection for the heavily-doped channel design and decreasing injection for the lightly-doped channel design. These important trends are attributed to highly two-dimensional electric field and current density distributions. Simulations also show that the lightly-doped channel design is about three times more reliable for thick silicon layers. However, as the silicon layer is thinned to 30 nm, the heavily-doped channel design becomes about 10% more reliable instead     

A physically based small-signal circuit model for heterostructureacoustic charge transport devices

A physically based small-signal circuit model for GaAs-AlGaAs Schottky gate heterostructure acoustic charge transport (HACT) devices is presented. Analytical expressions for the instantaneous and average channel current as a function of gate voltage are obtained from physical device parameters. The charge injection model is based on subthreshold current models for GaAs MESFETs. It is shown that the shape of the sampling aperture of the charge injection operation is approximately Gaussian. Good agreement is obtained between the measured DC channel current versus gate voltage and that predicted by the model. Equivalent circuits for the transfer and output sensing operations and expressions for noise sources due to the physical processes that occur within the device are developed. Thermal, shot, and transfer noise are treated. The form of the analytic expressions for frequency response and noise figure allows easy implementation on commercially available CAE software. Simulations of both gain and noise figure performed on Libra show good agreement with measured data     

Impact ionization and real-space transfer of minority carriers incharge injection transistors

High electric fields in the channel of InGaAs-InAlAs heterostructure complementary charge injection transistor give rise to impact ionization and real-space transfer of minority holes from the channel. These phenomena are investigated by measuring light emission in the 1.1-3.1 eV energy range for different points on the electrical characteristics. The effective carrier temperature, determined from the exponential tails of electroluminescence spectra, is 2100 K in the channel and 450 K in the barrier     

Charge trapping in organic transistor memories: On the role of electrons and holes

In this work, we study charge trapping in organic transistor memories with a polymeric insulator as gate dielectric. We found that the mechanism of charge trapping is tunneling from the semiconductor channel into the gate dielectric. Depending on the semiconductor and its processing, charge trapping can result in large bi-directional threshold voltage shifts, in case the semiconductor is ambipolar, or in shifts in only one direction (unipolar semiconductor). These results indicate that optimal memory performance requires charge carriers of both polarities, because the most efficient method to lower the programming field is by overwriting a trapped charge by an injected charge of opposite polarity.     

Measurement and analysis of charge injection in MOS analog switches

The analysis has been extended to the general case including signal-source resistance and capacitance. Universal plots of percentage channel charge injected are presented. Normalized variables are used to facilitate usage of the plots. The effects of gate voltage falling rate, signal-source level, substrate doping, substrate bias, switch dimensions, as well as the source and holding capacitances are included in the plots. A small-geometry switch, slow switching rate, and small source resistance can reduce the charge injection effect. On-chip test circuitry with a unity-gain operational amplifier, which reduces the disturbance imposed by measurement equipment to a minimum, is found to be an excellent monitor of the switch charge injection. The theoretical results agree with the experimental data.     

Successive charging/discharging of gate oxides in SOI MOSFET's bysequential hot-electron stressing of front/back channel

Hot-hole injection into the opposite channel of silicon-on-insulator (SOI) MOSFETs under hot-electron stress is reported. Sequential front/back-channel hot-electron stressing results in successive hot-electron/-hole injection, causing the threshold voltage to increase and decrease accordingly. This ability to inject hot holes into the opposite gate oxide can be used as an additional tool for studying the degradation mechanisms. Furthermore, it can be explored for possible use in designing SOI flash memory cells with back-channel-based erasing schemes     

Enhanced electron trapping near channel edges in NMOS transistors

Charge trapping in the gate oxide of NMOS transistors due to constant-voltage Fowler-Nordheim injection was investigated. Results from several different measurement methods consistently indicated strongly enhanced electron trapping in the gate oxide near the channel edges and in the gate oxide overlaps above drain and source, although net positive charge was observed in the bulk of the channel. The edge trapping effect could increase the electrical channel length by as much as 0.5 μm and is independent of the channel length. Possible reasons for the observed phenomena are discussed     

Planarization of Polymeric Field‐Effect Transistors: Improvement of Nanomorphology and Enhancement of Electrical Performance

The planarization of bottom‐contact organic field‐effect transistors (OFETs) resulting in dramatic improvement in the nanomorphology and an associated enhancement in charge injection and transport is reported. Planar OFETs based on regioregular poly(3‐hexylthiophene) (rr‐P3HT) are fabricated wherein the Au bottom‐contacts are recessed completely in the gate‐dielectric. Normal OFETs having a conventional bottom‐contact configuration with 50‐nm‐high contacts are used for comparison purpose. A modified solvent‐assisted drop‐casting process is utilized to form extremely thin rr‐P3HT films. This process is critical for direct visualization of the effect of planarization on the polymer morphology. Atomic force micrographs (AFM) show that in a normal OFET the step between the surface of the contacts and the gate dielectric disrupts the self‐assembly of the rr‐P3HT film, resulting in poor morphology at the contact edges. The planarization of contacts results in notable improvement of the nanomorphology of rr‐P3HT, resulting in lower resistance to charge injection. However, an improvement in field‐effect mobility is observed only at short channel lengths. AFM shows the presence of well‐ordered nanofibrils extending over short channel lengths. At longer channel lengths the presence of grain boundaries significantly minimizes the effect of improvement in contact geometry as the charge transport becomes channel‐limited.     

Measurement of crossphase modulation in coherent wavelength-division multiplexing using injection lasers

Light from two InGaAsP injection lasers of different wavelengths was multiplexed into a 15 km-long single-mode fibre. Owing to the nonlinear refractive index, the phase of light in one channel was changed by power changes in the other channel. A 1 mW power charge in one channel produced a 1.4° phase shift in the other channel.     

Hot carrier effects in n-MOSFETs with SiO2/HfO2/HfSiO gate stack and TaN metal gate

Charge trapping and trap generation in field-effect transistors with SiO₂/HfO₂/HfSiO gate stack and TaN metal gate electrode are investigated under uniform and non-uniform charge injection along the channel. Compared to constant voltage stress (CVS), hot carrier stress (HCS) exhibits more severe degradation in transconductance and subthreshold swing. By applying a detrapping bias, it is demonstrated that charge trapping induced degradation is reversible during CVS, while the damage is permanent for hot carrier injection case.     

Characterization of programmed charge lateral distribution in a two-bit storage nitride flash memory cell by using a charge-pumping technique

In this paper, we use a modified charge pumping technique to characterize the programmed charge lateral distribution in a hot electron program/hot hole erase, two-bit storage nitride Flash memory cell. The stored charge distribution of each bit over the source/drain junctions can be profiled separately. Our result shows that the second programmed bit has a broader stored charge distribution than the first programmed bit. The reason is that a large channel field exists under the first programmed bit during the second bit programming. Such a large field accelerates channel electrons and causes earlier electron injection into the nitride. In addition, we find that programmed charges spread further into the channel as program/erase cycle number increases.