A majority-logic nanodevice using a balanced pair of single-electron boxes

This paper describes a majority-logic gate device that will be useful in developing single-electron integrated circuits. The gate device consists of two identical single-electron boxes combined to form a balanced pair. It accepts three inputs and produces a majority-logic output by using imbalances caused by the input signals; it produces a 1 output if two or three inputs are 1, and a 0 output if two or three inputs are 0. We combine these gate devices into two subsystems, a shift register and an adder, and demonstrate their operation by computer simulation. We also propose a method of fabricating the unit element of the gate device, a minute dot with four coupling arms. We demonstrate by experiments that it is possible to arrange these unit elements on a GaAs substrate, in a self-organizing manner, by means of a process technology that is based on selective-area metalorganic vapor-phase epitaxy.     

Construction of a Fuzzy and Boolean Logic Gates Based on DNA

Logic gates are devices that can perform logical operations by transforming a set of inputs into a predictable single detectable output. The hybridization properties, structure, and function of nucleic acids can be used to make DNA‐based logic gates. These devices are important modules in molecular computing and biosensing. The ideal logic gate system should provide a wide selection of logical operations, and be integrable in multiple copies into more complex structures. Here we show the successful construction of a small DNA‐based logic gate complex that produces fluorescent outputs corresponding to the operation of the six Boolean logic gates AND, NAND, OR, NOR, XOR, and XNOR. The logic gate complex is shown to work also when implemented in a three‐dimensional DNA origami box structure, where it controlled the position of the lid in a closed or open position. Implementation of multiple microRNA sensitive DNA locks on one DNA origami box structure enabled fuzzy logical operation that allows biosensing of complex molecular signals. Integrating logic gates with DNA origami systems opens a vast avenue to applications in the fields of nanomedicine for diagnostics and therapeutics.     

Novel single-electron logic circuits using charge-induced signal transmission (CIST) structures

In this paper, on the basis of the Monte Carlo simulation, we demonstrate a method to realize logical operations by the use of the single-electron charge-induced signal transmission (CIST) circuit which we have proposed previously. First, we propose three new-type signal transmission circuits. Then, we demonstrate through construction of a NAND circuit and a full-adder circuit on the basis of the Monte Carlo simulation that we can construct any logic circuit by the use of these circuits. Since the CIST circuit can perform any logical operation and can transmit the state of the presence or absence of an electron and a hole as a binary signal over long distance during one clock cycle bidirectionally, these CIST circuits are expected to be applied to integrated circuit devices as a new circuit construction method.     

Analytical Models for the Performance of von Neumann Multiplexing

As conventional silicon CMOS technology continues to shrink, logic circuits are increasingly subject to errors induced by electrical noise. In addition, device reliability will become a problem, and circuits will be subject to permanent faults. Rather than requiring the circuit to be defect-free, fault-tolerance techniques can be incorporated to allow the continued operation of these devices in the presence of defects. We present an improved model for the reliability of nand multiplexing, a fault-tolerance technique typically requiring large levels of redundancy. It extends previous models to account for dependence between the inputs and derives the distribution of the outputs of each stage when subject to errors. The Markov chain approach used in earlier models is shown to be correct in modeling the effect of multiple stages. Our new model produces more accurate results for moderate levels of redundancy. An example shows the required hardware redundancy is reduced by 50% versus the previous binomial model. In addition, three new types of errors are modeled: the output stuck-at-one, output stuck-at-zero, and input stuck-at-zero faults     

Liquid marble interaction gate for collision-based computing

Liquid marbles are microliter droplets of liquid, encapsulated by self-organized hydrophobic particles at the liquid/air interface. They offer an efficient approach for manipulating liquid droplets and compartmentalizing reactions in droplets. Digital fluidic devices employing liquid marbles might benefit from having embedded computing circuits without electronics and moving mechanical parts (apart from the marbles). We present an experimental implementation of a collision gate with liquid marbles. Mechanics of the gate follows principles of Margolus’ soft-sphere collision gate. Boolean values of the inputs are given by the absence (FALSE) or presence (TRUE) of a liquid marble. There are three outputs: two outputs are trajectories of undisturbed marbles (they only report TRUE when just one marble is present at one of the inputs), one output is represented by trajectories of colliding marbles (when two marbles collide they lose their horizontal momentum and fall), this output reports TRUE only when two marbles are present at inputs. Thus the gate implements AND and AND-NOT logical functions. We speculate that by merging trajectories representing AND-NOT output into a single channel one can produce a one-bit half-adder. Potential design of a one-bit full-adder is discussed, and the synthesis of both a pure nickel metal and a hybrid nickel/polymer liquid marble is reported.     

Fabrication and Room-Temperature Single-Charging Behavior of Self-Aligned Single-Dot Memory Devices

Self-aligned single-dot memory devices and arrays were fabricated based on arsenic-assisted etching and oxidation effects. The resulting device has a floating gate of about 5-10 nm, presenting single-electron memory operation at room temperature. In order to realize the final single-electron memory circuit, this paper investigates process repeatability, device uniformity in single-dot memory arrays, device scalability, and process transferability to an industrial application     

Josephson Junction based Quantum Computing

Among the physical realizations of the elements required for quantum computation nano-scale electronic devices [2, 10, 12, 16] are very promising. They can be easily integrated into electronic circuits and scaled up to large numbers of qubits. Here we describe qubits based on low-capacitance Josephson junctions. In these systems Coulomb blockade effects allow the control of the charge on a superconducting island. They constitute quantum bits, with logical states differing by the charge on one island. Single- and two-bit operations can be performed by manipulating applied gate voltages. The phase coherence time is sufficiently long to allow a series of these steps. In addition to the manipulation of qubits, the resulting quantum state can be read out by coupling a single-electron transistor capacitively to the qubit. Received: October 23, 1998; revised version: September 21, 1999     

Reliability-Driven Gate Replication for Nanometer-Scale Digital Logic

To make digital circuits with unreliable devices more reliable has been a design challenge, especially for today's nanometer-scale technologies. In this paper, we discuss gate replication architecture towards increasing the reliability of individual logic gates. While this architecture is similar to, and a special case of, conventional N-modular redundancy scheme, we provide more interpretation and extend it to the situation where N is an even integer by using threshold logic gate instead of majority voter. We also study the reliability models for generic gates with single-electron tunneling (SET) technology. Both analysis and numerical evaluation suggest that while more redundancy leads to higher reliability in general, the improvement rate depends on individual gate failure rates     

Renewable Time‐Responsive DNA Circuits

DNA devices have been shown to be capable of evaluating Boolean logic. Several robust designs for DNA circuits have been demonstrated. Some prior DNA‐based circuits are use‐once circuits since the gate motifs of the DNA circuits get permanently destroyed as a side effect of the computation, and hence cannot respond correctly to subsequent changes in inputs. Other DNA‐based circuits use a large reservoir of buffered gates to replace the working gates of the circuit and can be used to drive a finite number of computation cycles. In many applications of DNA circuits, the inputs are inherently asynchronous, and this necessitates that the DNA circuits be asynchronous: the output must always be correct regardless of differences in the arrival time of inputs. This paper demonstrates: 1) renewable DNA circuits, which can be manually reverted to their original state by addition of DNA strands, and 2) time‐responsive DNA circuits, where if the inputs change over time, the DNA circuit can recompute the output correctly based on the new inputs, that are manually added after the system has been reset. The properties of renewable, asynchronous, and time‐responsiveness appear to be central to molecular‐scale systems; for example, self‐regulation in cellular organisms.     

High-speed Josephson integrated circuit technology

The author describes recent progress in high-speed integrated circuits using niobium junctions. He briefly describes the circuit fabrication process and then introduces the modified variable threshold logic (MVTL) gate family. The lowest experimentally obtained MVTL OR-gate delay was only 2.5 ps with a power consumption of 17 μW/gate. This gate family is used in various high-speed logic circuits, such as 8-bit shift registers, 16-bit ALUs (arithmetic logic units), and 4-bit microprocessors. The author confirmed the high-speed operation of less than 10 ps per gate on average for these circuits. A novel high-sensitivity magnetic sensor using a SQUID (superconducting quantum interference device) was also developed. It is called a single-chip SQUID magnetometer because the feedback circuit, which is operated at room temperature is a conventional SQUID system, has been integrated on the same chip as the SQUID sensor itself     

Single-Electron Device With Si Nanodot Array and Multiple Input Gates

We have developed a flexible-logic-gate single-electron device (SED) with an array of nanodots. Although the small size of SEDs is highly advantageous, the size of the nanodots inevitably fluctuates, which causes variations in device characteristics. This variability can be eliminated and high device functionality can be obtained by exploiting the oscillatory characteristics and multigate capability of SEDs. We fabricated, on a silicon-on-insulator wafer, a Si nanodot array device with two input gates and a control gate and investigated its basic operation characteristics experimentally. The device was demonstrated to operate as a logic gate providing six important logic functions ( and, or, nand, nor, xor, and xnor), which are obtained by adjusting the control-gate voltage.     

Bifurcations and fundamental error bounds for fault-tolerant computations

In the emerging nanotechnologies, faulty components may be an integral part of a system. For the system to be reliable, the error of the building blocks has to be smaller than a threshold. Therefore, finding exact error thresholds for noisy gates is one of the most challenging problems in fault-tolerant computations. Under the von Neumann's probabilistic computing framework, we show that computation by circuits built out of noisy NAND gates with an arbitrary number of K inputs under worst case operation can be readily described by nonlinear discrete maps. Bifurcation analysis of such maps naturally gives the exact error thresholds above which no reliable computation is possible. It is further shown that the maximum threshold value for a K-input NAND gate is obtained when K=5. This implies that if one chooses NAND gate as basic building blocks, then the optimal number of inputs for the NAND gate may be very different from the conventional value of 2. The analysis technique generalizes to other types of gates and circuits that use voting to improve reliability, as well as a network built out of the so-called para-restituted NAND gates recently proposed by Sadek et al. Nonlinear dynamics theory offers an interesting perspective to study rich nonlinear interactions among faulty components and design nanoscale fault-tolerant architectures.     

Progress Report on “From Printed Electrolyte‐Gated Metal‐Oxide Devices to Circuits”

Printed electrolyte‐gated oxide electronics is an emerging electronic technology in the low voltage regime (≤1 V). Whereas in the past mainly dielectrics have been used for gating the transistors, many recent approaches employ the advantages of solution processable, solid polymer electrolytes, or ion gels that provide high gate capacitances produced by a Helmholtz double layer, allowing for low‐voltage operation. Herein, with special focus on work performed at KIT recent advances in building electronic circuits based on indium oxide, n‐type electrolyte‐gated field‐effect transistors (EGFETs) are reviewed. When integrated into ring oscillator circuits a digital performance ranging from 250 Hz at 1 V up to 1 kHz is achieved. Sequential circuits such as memory cells are also demonstrated. More complex circuits are feasible but remain challenging also because of the high variability of the printed devices. However, the device inherent variability can be even exploited in security circuits such as physically unclonable functions (PUFs), which output a reliable and unique, device specific, digital response signal. As an overall advantage of the technology all the presented circuits can operate at very low supply voltages (0.6 V), which is crucial for low‐power printed electronics applications.     

Electrical properties of high-κ gate dielectrics: Challenges, current issues, and possible solutions

High-κ gate dielectrics like HfO₂ and HfSiO(N) are considered for the replacement of SiO₂ and SiON layers in advanced complementary metal–oxide–semiconductor (MOS) devices. Using these gate oxides allows indeed to drastically reduce the leakage current flowing through the device, as required by the specifications of the International Technology Roadmap for Semiconductors. However, major problems remain to be solved before the possible use of high-κ gate dielectrics in integrated circuits. The purpose of this paper is to give an overview of the challenges and issues pertaining to high-κ-based devices. Several issues are discussed in detail, like flat-band and threshold voltage control, carrier mobility degradation, charge trapping, gate dielectric wear-out and breakdown, and bias temperature instabilities. Our current understanding of these issues is presented, with an emphasis on the relationship between the material properties of the gate stack, and the electrical properties of the devices. The combination of metal gates with high-κ gate dielectric appears to be a promising solution for the further scaling down of CMOS devices.     

The use of multiaperture cores for the realization of threshold functions of many variables

It is shown that threshold functions of many variables can be realized by writing these variables into a multiaperture core and then reading them out synchronously. The multiaperture core is a closed series magnetic circuit of elementary, e.g., toroidal, cores each of which serves to store one binary variable. During the read operation identical EMF pulses are induced in all one-turn figure-eight output windings. Their polarity depends on the value of the input variable. The threshold function is realized by summing the EMF induced in all the output windings whose number of turns are proportional to the weights of the corresponding variables. On one core it is possible to obtain simultaneously various threshold functions of the input variables. It is possible to expand the logical possibilities of the threshold element by executing some elementary logical functions of two or three variables at the input.     

SOI single-electron transistor with low RC delay for logic cells and SET/FET hybrid ICs

We report on a successful fabrication of silicon-based single-electron transistors (SETs) with low RC time constant and their applications to complementary logic cells and SET/field-effect transistor (FET) hybrid integrated circuit. The SETs were fabricated on a silicon-on-insulator (SOI) structure by a pattern-dependent oxidation (PADOX) technique, combined with e-beam lithography. Drain conductances measured at 4.2 K approach large values of the order of microsiemens, exhibiting Coulomb oscillations with peak-to-valley current ratios /spl Gt/1000. Data analysis with a probable mechanism of PADOX yields their intrinsic speeds of /spl sim/ 2 THz, which is within an order of magnitude of the theoretical quantum limit. Incorporating these SETs as basic elements, in-plane side gate-controlled complementary logic cells and SET/FET hybrid integrated circuits were fabricated on an SOI chip. Such an in-plane structure is very efficient in the Si fabrication process, and the side gates adjacent to the electron island could easily control the phase of Coulomb oscillations. The input-output voltage transfer, characteristic of the logic cell, shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2 K. The SET/FET hybrid integrated circuit consisting of one SET and three FETs yields a high-voltage gain and power amplification with a wide-range output window for driving the next circuit. The small SET input gate voltage of 30 mV is finally converted to 400 mV, corresponding to an amplification ratio of 13.     

Ultracompact photonic coupling splitters twisted by PTT nanowires

We report a series of ultracompact photonic coupling splitters with multi-input/output ports assembled by twisting flexible polymer nanowires, which were fabricated by one-step drawing method from poly(trimethylene terephthalate) (PTT). Experimental demonstration shows that the properties of the splitters are dependent on the operation wavelength and the input branch of the optical signal launched. For a fixed operation wavelength and the input branch, desirable splitting ratio can be tuned by controlling the input/output branching angle. The excess loss of these splitters is less than 1 dB, and the intrinsic loss is less than 0.4 dB. They are desirable for high density photonic integrated circuits (PICs) and nanonetworks, while the twisting technology will be useful in constructing other wire-based photonic devices.     

Simple and universal platform for logic gate operations based on molecular beacon probes

A new platform technology is herein described with which to construct molecular logic gates by employing the hairpin-structured molecular beacon probe as a basic work unit. In this logic gate operation system, single-stranded DNA is used as the input to induce a conformational change in a molecular beacon probe through a sequence-specific interaction. The fluorescent signal resulting from the opening of the molecular beacon probe is then used as the output readout. Importantly, because the logic gates are based on DNA, thus permitting input/output homogeneity to be preserved, their wiring into multi-level circuits can be achieved by combining separately operated logic gates or by designing the DNA output of one gate as the input to the other. With this novel strategy, a complete set of two-input logic gates is successfully constructed at the molecular level, including OR, AND, XOR, INHIBIT, NOR, NAND, XNOR, and IMPLICATION. The logic gates developed herein can be reversibly operated to perform the set-reset function by applying an additional input or a removal strand. Together, these results introduce a new platform technology for logic gate operation that enables the higher-order circuits required for complex communication between various computational elements.     

Reversible Logic-Based Concurrently Testable Latches for Molecular QCA

Nanotechnologies, including molecular quantum dot cellular automata (QCA), are susceptible to high error rates. In this paper, we present the design of concurrently testable latches ($D$ latch, $T$ latch, JK latch, and SR latch), which are based on reversible conservative logic for molecular QCA. Conservative reversible circuits are a specific type of reversible circuits, in which there would be an equal number of 1's in the outputs as there would be on the inputs, in addition to one-to-one mapping. Thus, conservative logic is parity-preserving, i.e., the parity of the input vectors is equal to that of the output vectors. We analyzed the fault patterns in the conservative reversible Fredkin gate due to a single missing/additional cell defect in molecular QCA. We found that if there is a fault in the molecular QCA implementation of Fredkin gate, there is a parity mismatch between the inputs and the outputs, otherwise the inputs parity is the same as outputs parity. Any permanent or transient fault in molecular QCA can be concurrently detected if implemented with the conservative Fredkin gate. The design of QCA layouts and the verification of the latch designs using the QCADesigner and the HDLQ tool are presented.