A Monolithically Integrated 12V/5V Switch-Capacitor DC-DC Converter

Motivated by the battery-operated applications that demand compact,lightweight andefficient DC-DC converters,many kinds of converter circuits have been published.Amongthem,resonantconverters and the soft-switching convertershave greatl...     

A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC

This paper discusses fully digital error correction and self-calibration which correct errors due to capacitor mismatch, charge injection, and comparator offsets in algorithmic A/D converters. The calibration is performed without any additional analog circuitry, and the conversion does not need extra clock cycles. This technique can be applied to algorithmic converter configurations including pipelined, cyclic, or pipelined cyclic configurations. To demonstrate the concept, an experimental 2-stage pipelined cyclic A/D converter is implemented in a standard 1.6-μm CMOS process. The ADC operates at 600 ks/s using 45 mW of power at ±2.5 V supplies. The active die area excluding the external logic circuit is 1 mm². Maximum DNL of ±0.6 LSB and INL of ±1 LSB at a 12-b resolution have been achieved     

A 15-b 1-Msample/s digitally self-calibrated pipeline ADC

A 15-b 1-Msample/s digitally self-calibrated pipeline analog-to-digital converter (ADC) is presented. A radix 1.93, 1 b per stage design is employed. The digital self-calibration accounts for capacitor mismatch, comparator offset, charge injection, finite op-amp gain, and capacitor nonlinearity contributing to DNL. A THD of -90 dB was measured with a 9.8756-kHz sine-wave input. The DNL was measured to be within ±0.25 LSB at 15 b, and the INL was measured to be within ±1.25 LSB at 15 b. The die area is 9.3 mm×8.3 mm and operates on ±4-V power supply with 1.8-W power dissipation. The ADC is fabricated in an 11-V, 4-GHz, 2.4-μm BiCMOS process     

A Monolithically Integrated 12V/5V Switch-Capacitor DC-DC Converter

A monolithically integrated 12V/SV switch capacitor DC-DC converter with structure-simplified main circuit and control circuit is presented. Its topological circuit and basic operating principle are discussed in detail. It is shown that elevated operating frequency, increased capacitance and reduced turn-on voltage of the diodes can make the converter's output characteristics improved. Reducing resistance of the equivalent resistors and other parasitic parameters can make the operation frequency higher. As a feasible efficient method to fabricate monolithically integrated converter with high frequency and high output power, several basic circuits are parallelly combined where the serial-parallel capacitance is optimized for the maximum output power. The device selection and its fabrication method are presented. A feasible integration process and its corresponding layout are designed. All active devices including switching transistors and diodes are integrated together with all passive cells including capacitors and resistor on a single chip based on BiMOS process,as has been verified to be correct and practical by simulation and chip test.     

A 14-b 2.5 MSPS pipelined ADC with on-chip EPROM

A 14-b 2.5 MSPS, multistage pipeline, subranging analog-to-digital converter is presented. In addition to conventional laser-wafer-trim, on chip, “write once” EPROM is used to calibrate inter-stage gain errors at package sort. Integral nonlinearity errors as small as ±1.5 LSB and differential nonlinearity errors of ±0.5 LSB have been achieved. The 5.4 mm by 4.4 mm device includes a 2.5 V reference and is built on a 2 μm 10 V BiCMOS process and consumes 500 mW of power     

Micropower CMOS temperature sensor with digital output

A CMOS smart temperature sensor with digital output is presented. It consumes only 7 μW. To achieve this extremely low-power consumption, the system is equipped with a facility that switches off the supply power after each sample. The circuit uses substrate bipolars as a temperature sensor. Conversion to the digital domain is done by a sigma-delta converter which makes the circuit highly insensitive to digital interference. The complete system is realized in a standard CMOS process and measures only 1.5 mm². In the temperature range from -40 to +120°C, the inaccuracy is ±1°C after calibration at two temperatures. The circuit operates at supply voltages down to 2.2 V     

An 8-MHz CMOS subranging 8-bit A/D converter

A 8-bit subranging converter (ADC) has been realized in a 3-/spl mu/m silicon gate, double-polysilicon capacitor CMOS process. The ADC uses 31 comparators and is capable of conversion rates to 8 MHz at V/SUB DD/=5 V. Die size is 3.2/spl times/2.2 mm/SUP 2/.     

A low glitch 14-b 100-MHz D/A converter

A low glitch 14-b 100-MHz current output digital-to-analog converter (DAC) is described. In addition to segmentation of the four most significant bits (MSB's) into 15 equally weighted current sources, a proportional-to-absolute-temperature (PTAT) switching voltage is applied to the current steering devices to minimize glitch over temperature. A bidirectional thin-film trim network and high β n-p-n devices reduce the amount of laser trimming required to achieve 14-b accuracy, resulting in less post-trim degradation of DAC linearity over temperature and the life of the chip. The converter has been fabricated in a 4-GHz/1.4-μm BiCMOS technology and exhibits a measured glitch energy of 0.5 pV·s (singlet). Settling time to within ±0.012% of the final value is ⩽20 ns for both rising and falling edges of a full scale step. Spurious free dynamic range (SFDR) for the described converter is 87 dBc at an update rate (f_CLK) of 10 MHz and an output frequency (f_OUT) of 2.03 MHz. The converter operates from +5 V and -5.2 V supplies and consumes 650 mW independent of conversion rate. The chip size is 4.09×4.09 mm including bond pads and electrostatic discharge (ESD) protection devices     

A 15-b resolution 2-MHz Nyquist rate ΔΣ ADC in a1-μm CMOS technology

A high-resolution high-speed fourth-order cascaded ΔΣ analog-to-digital converter, based on a 2-1-1 topology, is presented. The converter is implemented with fully differential switched capacitor circuits in a standard 1-μm CMOS technology. The converter uses two symmetrical reference voltages of 1 V, and is driven by a single 48-MHz clock signal. With an oversampling ratio of only 24, the converter achieves a resolution of 91 dB, a peak SNR of 90 dB, and a peak SNDR of 85 dB at a Nyquist rate of 2 MHz after comb filtering. The power consumption of the converter is 230 mW, from a single 5-V supply voltage     

A CMOS continuous-time Gm-C filter for PRML read channelapplications at 150 Mb/s and beyond

Design techniques for equiripple phase CMOS continuous-time filters are presented, and their integration within a partial-response maximum likelihood (PRML) disk drive read channel is discussed. A programmable seven-pole two asymmetric zero filter implementation is described based on a new transconductance (G_m) cell. The impact of integrator finite output impedance, excess phase, and other implementation related nonidealities is discussed. A filter tuning circuit that requires an accurate time base but no external components is presented. The filter has a cutoff frequency (f_c) range of 6-43 MHz, where f_c is the -3 dB point of the magnitude transfer function with the two zeros set to infinity. Also, with finite zeros it is able to provide up to 12 dB of boost which is defined as the maximum value of the magnitude transfer function referred to dc. The group delay ripple stays within ±2% for frequencies below 1.75 f _c. The cutoff frequency exhibits a 650 ppm/°C temperature dependency and a variation of ±1%/V with the power supply. Total harmonic distortion (THD) values are below -40 dB at twice the nominal operating input voltage (V_nominal=320 mV peak-to-peak differential), and the dynamic range exceeds 60 dB (for a maximum input signal of 640 mV peak-to-peak differential, maximum bandwidth setting, and no boost). Both the filter and a tuning circuit were implemented in a 0.6-μm single-poly triple-metal n-well CMOS process. They consume 90 mW from a single 5 V power supply and occupy an area of 0.8 mm²      

A low-power reconfigurable analog-to-digital converter

A low-power CMOS reconfigurable analog-to-digital converter that can digitize signals over a wide range of bandwidth and resolution with adaptive power consumption is described. The converter achieves the wide operating range by (1) reconfiguring its architecture between pipeline and delta-sigma modes; (2) varying its circuit parameters, such as size of capacitors, length of pipeline, and oversampling ratio, among others; and (3) varying the bias currents of the opamps in proportion to the converter sampling frequency, accomplished through the use of a phase-locked loop (PLL). This converter also incorporates several power-reducing features such as thermal noise limited design, global converter chopping in the pipeline mode, opamp scaling, opamp sharing between consecutive stages in the pipeline mode, an opamp chopping technique in the delta-sigma mode, and other design techniques. The opamp chopping technique achieves faster closed-loop settling time and lower thermal noise than conventional design. At a converter power supply of 3.3 V, the converter achieves a bandwidth range of 0-10 MHz over a resolution range of 6-16 bits, and parameter reconfiguration time of twelve clock cycles. Its PLL lock range is measured at 20 kHz to 40 MHz. In the delta-sigma mode, it achieves a maximum signal-to-noise ratio of 94 dB and second and third harmonic distortions of 102 and 95 dB, respectively, at 10 MHz clock frequency, 9.4 kHz bandwidth, and 17.6 mW power. In the pipeline mode, it achieves a maximum DNL and INL of ±0.55 LSBs and ±0.82 LSBs, respectively, at 11 bits, at a clock frequency of 2.6 MHz and 1 MHz tone with 24.6 mW of power     

A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC

A low-power 10-bit converter that can sample input frequencies above 100 MHz is presented. The converter consumes 55 mW when sampling at f_s=40 MHz from a 3-V supply, which also includes a bandgap and a reference circuit (70 mW if including digital drivers with a 10-pF load). It exhibits higher than 9.5 effective number of bits for an input frequency at Nyquist (f_in=f_s/2=20 MHz). The differential and integral nonlinearity of the converter are within ±0.3 and ±0.75 LSB, respectively, when sampling at 40 MHz, and improve to a 12-bit accuracy level for lower sampling rates. The overall performance is achieved using a pipelined architecture without a dedicated sample/hold amplifier circuit at the input. The converter is implemented in double-poly, triple-metal 0.35-μm CMOS technology and occupies an area of 2.6 mm²     

A high-frequency and high-resolution fourth-order /spl Sigma//spl Delta/ A/D converter in BiCMOS technology

A high-performance cascaded sigma-delta modulator is presented. It has a new three-stage fourth-order topology and provides functionally a maximum signal to quantization noise ratio of 16 bits and 16.5-bit dynamic range with an oversampling ratio of only 32. This modulator is implemented with fully differential switch-capacitor circuits and is manufactured in a 2-/spl mu/m BiCMOS process. The converter, operated from +/-2.5 V power supply, +/-1.25 V reference voltage and oversampling clock of 48 MHz, achieves 97 dB resolution at a Nyquist conversion rate of 1.5 MHz after comb-filtering decimation. The power consumption of the converter is 180 mW.<>     

A 10-bit 200-MS/s CMOS parallel pipeline A/D converter

This paper describes a 10-bit 200-MS/s CMOS parallel pipeline analog-to-digital (A/D) converter that can sample input frequencies above 200 MHz. The converter utilizes a front-end sample-and-hold (S/H) circuit and four parallel interleaved pipeline component A/D converters followed by a digital offset compensation. By optimizing for power in the architectural level, incorporating extensively parallelism and double-sampling both in the S/H circuit and the component ADCs, a power dissipation of only 280 mW from a 3.0-V supply is achieved. Implemented in a 0.5-μm CMOS process, the circuit occupies an area of 7.4 mm². The converter achieves a differential nonlinearity and integral nonlinearity of ±0.8 LSB and ±0.9 LSB, respectively, while the peak spurious-free-dynamic-range is 55 dB and the total harmonic distortion better than 46 dB at a sampling rate of 200 MS/s     

一种用于数模转换器的电流-电压转换电路

介绍了一种用于数模转换器的电流 电压转换电路。在数模转换器的负载电阻片内集成的情况下 ,利用文中提出的电流 电压转换电路 ,数模转换器实现了要求的宽摆幅电平输出 (全“0”输入时 ,输出低电平 - 3V ;全“1”输入时 ,输出高电平 3 5V)。整个数模转换器电路用 1 2 μm双层金属双层多晶硅n阱CMOS工艺实现。其积分非线性误差为 0 4 5个最低有效位 (LSB) ,微分非线性误差为 0 2LSB ,满摆幅输出的建立时间小于 1μs。该数模转换器使用± 5V电源 ,功耗约为 30mW ,电路芯片面积为 0 4 2mm2 。     

Design techniques for a low-power low-cost CMOS A/D converter

A 10 bit 200 kHz algorithmic analog-to-digital converter (ADC) was designed to demonstrate design techniques for low-power low-cost CMOS integrated systems. A switched-bias power-reduction technique reduces the total system power by 10%. A layout technique employing extra thin poly-layer lines instead of conventional dummy devices reduces plasma-induced comparator offsets. Based on a standard digital CMOS process with a single poly layer, the ADC adopts metal-to-metal capacitors for internal charge storage. The experimental ADC was fabricated in a 0.6 μm single-poly double-metal n-well CMOS technology, and showed a power consumption of 7 mW and a signal-to-noise-and-distortion ratio (SNDR) of 53 dB at the Nyquist sampling rate with a 3.3 V single supply voltage. The measured differential and integral nonlinearities of the prototype are less than ±0.8 and ±1.8 LSB, respectively     

A fully differential comparator using a switched-capacitordifferencing circuit with common-mode rejection

A fully differential comparator is described. It uses a switched-capacitor differencing circuit that provides common-mode rejection. The comparator has been tested by building a 3-b flash analog-to-digital converter (ADC) in a 2-μm CMOS process. With a supply voltage of 3.3 V, a sampling rate of 25 MHz, and full-scale sinusoidal inputs up to 7 MHz, the signal-to-distortion ratio of the ADC when the input is single ended is about 1-2 dB less than when the input is differential. In a 2-μm CMOS process, the comparator occupies 0.25 mm² and dissipates 1.05 mW     

A 400-Msample/s, 6-b CMOS folding and interpolating ADC

A 400-Msample/s, 6-bit CMOS folding and interpolating analog-to-digital converter (ADC) is described. A low-impedance current-mode approach is adopted. Current-division interpolation incorporated within the folders allows fast operation and is compatible with low supply voltages. This interpolation scheme, together with a short aperture comparator, gives good performance for input frequencies up to one-quarter of the sampling rate without using a sample and hold. For simplicity, the ADC uses only a single clock and its complement. The device is implemented in a 0.5 μm BiCMOS technology using only CMOS devices. The converter occupies 0.6 mm² and dissipates 200 mW from a 3.2 V supply     

A low-power CMOS time-to-digital converter

A time-to-digital converter, TDC, with 780 ps lsb and 10-μs input range has been integrated in a 1.2-μm CMOS technology. The circuit is based on the interpolation time interval measurement principle and contains an amplitude regulated crystal oscillator, a counter, two pulse-shrinking delay lines, and a delay-locked loop for stabilization of the delay. The TDC is designed for a portable, low-power laser range-finding device. The supply voltage is 5±0.5 V, and the operating temperature range is -40 to +60°C. Single-shot accuracy is 3 ns and accuracy after averaging is ±120 ps with input time intervals 5-500 ns. In the total input range of 10 μs, the final accuracy after averaging is ±200 ps. Current consumption is 3 mA, and the chip size is 2.9 mm×2.5 mm     

A versatile bipolar monolithic 6-bit A/D converter for 100 MHz sample frequency

An A/D converter was developed which uses a parallel conversion technique and is designed for manufacture with an ASBC process. The converter SDA 5010 is suitable for a wide range of applications because of its high-conversion rate, its low-power dissipation of 450 mW, large analog input range of up to /spl plusmn/2.5 V, and an overflow output for systems where a higher accuracy than 6 bits is required.