凸点材料的选择对器件疲劳特性的影响

为了研究凸点材料对器件疲劳特性的影响,采用非线性有限元分析方法、统一型黏塑性本构方程和Coffin-Manson修正方程,对Sn3.0Ag0.5Cu,Sn63Pb37和Pb90Sn10三种凸点材料倒装焊器件的热疲劳特性进行了系统研究,对三种凸点的疲劳寿命进行了预测,并对Sn3.0Ag0.5Cu和Pb90Sn10两种凸点材料倒装焊器件进行了温度循环试验.结果表明,仿真结果与试验结果基本吻合.在热循环过程中,凸点阵列中距离器件中心最远的焊点,应力和应变变化最剧烈,需重点关注这些危险焊点的可靠性;含铅凸点的热疲劳特性较无铅凸点更好,更适合应用于高可靠的场合;而且随着铅含量的增加,凸点的热疲劳特性越好,疲劳寿命越长.     

Influence of solder bump arrangements on molded IC encapsulation

This paper presents a fluid–structure interaction (FSI) analysis of ball grid array (BGA) package encapsulation. Real-time and simultaneous FSI analysis is conducted by using finite volume code (FLUENT) and finite element code (ABAQUS), which are coupled with MpCCI. A BGA integrated circuit (IC) package with different solder bump arrangements is considered in this study. In the FSI analysis, effects of solder bump arrangements on pressure distribution, void, deformation, and stress imposed on the IC structures are investigated. The maximum deformation and maximum stress on the silicon chip and solder bumps are evaluated. The findings indicate that the full-array solder bump package encounters lower stress and deformation during encapsulation. The void formation of each solder bump arrangement is examined. Scaled-up encapsulation is performed and the predicted flow front advancements are substantiated by experimental results. Results demonstrate the excellent capability of the proposed modeling tools for predictive trends of IC encapsulation. Thus, better understanding of IC encapsulation is provided to engineers and package designers in the microelectronics industry.     

Fracture Mechanics of Solder Bumps During Ball Shear Testing: Effect of Bump Size

This paper examines the mechanics of ball shear testing with the objective of understanding the mechanism by which the maximum shear force and the rate of crack growth is dependent on the solder bump size. For this, Pb-Sn solder bumps with diameters between 460 μm and 760 μm are soldered to 400 μm-diameter Cu pads and subjected to ball shear testing. In spite of the constant interface area, the bump size significantly impacts the measured shear fracture force and the crack growth rate. Both the fracture force and the crack growth rate increase with bump size, and in the case of the fracture force, the increase is almost linear. Our analysis finds that the linear increase in the fracture force is a result of the bump deformation force, which increases with bump size. A simple model that accounts for the deformation force component is developed and used to extract the true interface fracture force. The estimated true interface fracture force is found to vary little with bump size, tightly converging to the 40 MPa to 48 MPa range. On the other hand, the dependence of crack growth rate on bump size is found to result from the higher degree of rotational moment associated with larger bumps.     

Solder bump reliability-issues on bump layout

The reliability of solder bumps in a typical under-filled flip chip package is calculated three-dimensionally (3-D) using the finite element method and a viscoplastic material model for the solder. Simulations are performed with varying bump placement, underfill coverage and board size. The average plastic work in a bump is used to compare the loading and bump reliability of different geometries. The results show possible improvements over the traditional bump placement by changing the geometry of the interconnects on the flip chip package. Three changes that improve reliability are discussed in detail: the redistribution of bump rows, the reduction of board size and the inclusion of heat transfer bumps.     

Design of Solder Joint Structure for Flip Chip Package with an Optimized Shear Test Method

The structure of flip chip solder bumps was optimized in terms of shear height and shear speed using a shear test method with both experimental investigation and nonlinear, three-dimensional, finite element analysis being conducted. A representative, Pb-free solder composition, Sn-3.0Ag-0.5Cu, was used to optimize the shear test of the flip chip solder joints. Increasing the shear height, at a fixed shear speed, decreased the shear force, as did decreasing the shear speed, at a fixed shear height. These experimental and computational results supported the recommendation of low shear height and low shear speed condition for the shear testing of flip chip solder bumps. This optimized shear test method was applied to investigate the effect of various heights of mini bumps on the shear force of the solder joints. The shear force increased with increasing Ni-P mini bump height.     

CSP封装Sn-3.5Ag焊点的热疲劳寿命预测

对芯片尺寸封装(CSP)中Sn-3.5Ag无铅焊点在热循环加速载荷下的热疲劳寿命进行了预测.首先利用ANSYS软件建立CSP封装的三维有限元对称模型,运用Anand本构模型描述Sn-3.5Ag无铅焊点的粘塑性材料特性;通过有限元模拟的方法分析了封装结构在热循环载荷下的变形及焊点的应力应变行为,并结合Darveaux疲劳寿命模型预测了无铅焊点的热疲劳寿命.     

Isothermal aging effects on the microstructure and solder bump shear strength of eutectic Sn37Pb and Sn3.5Ag solders

The reliability of the eutectic Sn37Pb (63%Sn37%Pb) and Sn3.5Ag (96.5%Sn3.5%Ag) solder bumps with an under bump metallization (UBM) consisting of an electroless Ni(P) plus a thin layer of Au was evaluated following isothermal aging at 150 °C. All the solder bumps remained intact after 1500 h aging at 150 °C. Solder bump microstructure evolution and interface structure change during isothermal aging were observed and correlated with the solder bump shear strength and failure modes. Cohesive solder failure was the only failure mode for the eutectic Sn37Pb solder bump, while partial cohesive solder failure and partial Ni(P) UBM/Al metallization interfacial delamination was the main failure mode for eutectic Sn3.5Ag solder bump.     

Thermomechanical Reliability Study of Flip Chip Solder Bumps: Using Laser Ultrasound Technique and Finite Element Method

Current techniques for nondestructive quality evaluation of solder bumps in electronic packages are either incapable of detecting solder bump cracks, or unsuitable for in-line inspection due to high cost and low throughput. As an alternative, a solder bump inspection system is being developed at Georgia Institute of Technology using laser ultrasound and interferometric techniques . This system uses a pulsed Nd:YAG laser to induce ultrasound in electronic packages in the thermoelastic regime; it then measures the transient out-of-plane displacement responses on the package surfaces using laser interferometric technique. The quality of solder bumps in electronic packages is evaluated by analyzing the transient responses. This paper presents a systematic study on thermomechanical reliability of flip chip solder bumps using laser ultrasound–interferometric inspection technique and finite element (FE) method. The correlation between the failure parameter extracted from FE simulation for evaluating solder bump reliability and quality degradation characterization of solder bumps through noncontact, nondestructive laser ultrasound testing has also been investigated.      

Effect of bump size on current density and temperature distributions in flip-chip solder joints

Three dimensional thermo-electrical analysis was employed to simulate the current density and temperature distributions for eutectic SnAg solder bumps with shrinkage bump sizes. It was found that the current crowding effects in the solder were reduced significantly for smaller solder joints. Hot-spot temperatures and thermal gradient were increased upon reducing the solder. The maximum temperature for solder joint with 144.7 μm bump height is 103.15 °C which is only 3.15 °C higher than the substrate temperature due to Joule heating effect. However, upon reducing the bump height to 28.9 μm, the maximum temperature in the solder increased to 181.26 °C. Serious Joule heating effect was found when the solder joints shrink. The higher Joule heating effect in smaller solder joints may be attributed to two reasons, first the increase in resistance of the Al trace, which is the main heating source. Second, the average and local current densities increased in smaller bumps, causing higher temperature increase in the smaller solder bumps.     

Electrothermal coupling analysis of current crowding and Joule heating in flip-chip packages

Solder bumps serve as electrical paths as well as structural support in a flip-chip package assembly. Owing to the differences of feature sizes and electric resistivities between a solder bump and its adjacent traces, current densities around the regions where traces connect the solder bump increase in a significant amount. This current crowding effect along with the induced Joule heating would accelerate fatigue failure due to electromigration. In this paper we apply the three-dimensional electrothermal coupling analysis to investigate current crowding and Joule heating in a flip-chip package assembly carrying different constant electric currents under different ambient temperatures. Experiments are conducted to calibrate temperature-dependent electric resistivities of solder alloy, Al trace, and Cu trace, and to verify the numerical model by comparing calculated and measured maximum temperatures on the die surface. Through the electrothermal coupling analysis, effects of current crowding and Joule heating induced by different solder bump structures are examined and compared.     

Interfacial delamination investigation between copper bumps in 3D chip stacking package by using the modified virtual crack closure technique

In this study, the modified virtual crack closure technique (MVCCT) incorporated with the finite element method (FEM) is applied to investigate the delamination behavior between stacked copper bumps in 3D chip stacking packaging at package-level and board-level, and the energy release rate at the delamination front is evaluated as the criterion of the crack expansion. The package-level structure is firstly simulated to validate the dependability of MVCCT, and the results reveal that the delamination between copper bumps within specific size will not induce delamination expansion during thermal cycling condition, which show good agreement with experiment results. The mesh density and the delamination geometry effect analyses are also studied at package-level to ensure the reliable result of finite element analysis. The results show that the former has an insignificant effect on the energy release rate, while the later has a significant influence. Moreover, based on the simulation results at package-level structure, the further delamination behavior at board-level is investigated to predict potential failure mode different from the package-level structure. The results show higher energy release rate is induced and mixed fracture mode occurs.     

A study in flip-chip UBM/bump reliability with effects of SnPb solder composition

This paper aims to investigate the electromigration phenomenon of under-bump-metallization (UBM) and solder bumps of a flip-chip package under high temperature operation life test (HTOL). UBM is a thin film Al/Ni(V)/Cu metal stack of 1.5 μm; while bump material consists of Sn/37Pb, Sn/90Pb, and Sn/95Pb solder. Current densities of 2500 and 5000 A/cm² and ambient temperatures of 150–160 °C are applied to study their impact on electromigration. It is observed that bump temperature has more significant influence than current density does to bump failures. Owing to its higher melting point characteristics and less content of Sn phase, Sn/95Pb solder bumps are observed to have 13-fold improvement in Mean-Time-To-Failure (MTTF) than that of eutectic Sn/37Pb. Individual bump resistance history is calculated to evaluate UBM/bump degradation. The measured resistance increase is from bumps with electrical current flowing upward into UBM/bump interface (cathode), while bumps having opposite current polarity cause only minor resistance change. The identified failure sites and modes from aforementioned high resistance bumps reveal structural damages at the region of UBM and UBM/bump interface in forms of solder cracking or delamination. Effects of current polarity and crowding are key factors to observed electromigration behavior of flip-chip packages.     

Layer Structure and Thickness Effects on Electroplated AuSn Solder Bump Composition

The eutectic gold–tin (AuSn) solder composition is receiving increased attention for packaging applications. In addition to the environmental benefits of removing lead compounds from electronic manufacturing, gold–tin eutectic also exhibits desirable mechanical properties such as high strength and low thermal fatigue. However, some methods of deposition for this solder require complicated processes or limit the minimum bump size. This paper explores the formation of AuSn eutectic solder bumps using sequential electrodeposition of Au and Sn to determine the effect of layer thickness and sequence on the composition and structure of the resulting solder bump.     

Three-Dimensional Thermomechanical Simulation of Fine-Pitch High-Count Ball Grid Array Flip-Chip Assemblies

Flip-chip technology is increasingly prevalent in electronics assembly [three-dimensional (3D) system-in-package] and is mainly used at fine pitch for manufacture of megapixel large focal-plane detector arrays. To estimate the reliability of these assemblies, numerical simulations based on finite-element methods appear to be the cheapest approach. However, very large assemblies contain more than one million solder bumps, and the optimization process of such structures through numerical simulations turns out to be a very time-consuming task. In many applications, the interconnection layer of such flip-chip assemblies consists of solder bumps embedded in epoxy filler. For such configurations, we propose an alternative approach, which consists in replacing this heterogeneous interconnection layer by a homogeneous equivalent material (HEM). A micromechanical model for the estimation of its equivalent thermoelastic properties has been developed. The obtained constitutive law of the HEM was then implemented in finite-element software (Abaqus^®). Thermomechanical responses of tested assemblies submitted to loads corresponding to manufacturing conditions have been analyzed. The homogenization–localization process allowed estimation of the mean values of stresses and strains in each phase of the interconnection layer. To access more precisely the stress and strain fields in these phases, two models of structural zoom, taking into account the real solder bump geometry, have been tested. The obtained local stress and strain fields corroborate the experimentally observed damage initiation of the solder bumps.     

The effect of solder bump pitch on the underfill flow

An underfill encapsulant was used to fill the gap between the chip and substrate around solder joints to improve the long-term reliability of flip chip interconnect systems. The underfill encapsulant was filled by the capillary effect. In this study, the filling time and pattern of the underfill flow in the process with different bumping pitch, bump diameter, and gap size were investigated. A modified Hele-Shaw flow model, that considered the flow resistance in both the thickness direction and the restrictions between solder bumps, was used. This model estimated the flow resistance induced by the chip and substrate as well as the solder bumps, and provided a reasonable flow front prediction. A modified model that considered the effect of fine pitch solder bumps was also proposed to estimate the capillary force in fine pitch arrangements. It was found that, on a full array solder bump pattern, the filling flow was actually faster for fine pitch bumps in some arrangements. The filling time of the underfill process depends on the parameters of bumping pitch, bump diameter, and gap size. A proposed capillary force parameter can provide information on bump pattern design for facilitating the underfilling process.     

Characteristics of current crowding in flip-chip solder bumps

For a flip-chip package assembly, current crowding occurs in the vicinity of the locations where traces connect the solder bumps. This feature contributes significantly to the electromigration failure of the solder bumps. In this study the finite element analysis is performed to investigate characteristics of current crowding in a flip-chip solder bump subjected to a constant applied current. It is found that under such a condition, current crowding is induced solely by the structural geometry of the system. It is independent of the magnitude of the applied current. A volumetric averaging technique is also applied to cope with the current crowding singularity.     

Constitutive model and numerical analysis for high lead solders

High lead solder interconnects are extensively used in the electronic industry. This paper uses a unified creep plasticity (UCP) constitutive model to numerically simulate the mechanical performance of such interconnects under thermomechanical cyclic loading. The UCP model is capable of incorporating thermal and cyclic hardening effects. To make the model more objective, cyclic loading induced damage was also incorporated. The model is programmed into the commercially available finite element modeling software ABAQUS. A uniaxial tension case was analyzed to verify the model and reasonable agreement with experimental results was achieved. A typical three-dimensioned solder bump under shear deformation loading was analyzed and the strain/stress distribution within the solder bump was obtained.     

Characterization of 63Sn37Pb and 80Au2OSn solder sealed opticalfiber feedthroughs subjected to repetitive thermal cycling

A highly accurate prediction of hermeticity lifetime is made for eutectic 63Sn37Pb and 80Au20Sn alloy solder sealed optical fiber-Kovar ^TM nosetube feedthroughs subjected to repetitive thermal cycling. Thermal fatigue fracture of the Sn-Pb solder/Kovar^TM interface develops when cracks, initially generated from creep deformation of the solder, propagate gradually through the junction in the axial direction. A nonlinear axisymmetric finite element analysis of the 63Sn37Pb fiber feedthrough seal is performed using a thermo-elastic creep constitutive equation, and solder joint fatigue based on accumulated strain energy associated with solder creep imposed by temperature cycling is analyzed. Additionally, thermal effective stress and plastic strain is studied for alternative 80Au20Sn solder by the finite element method with results indicating significant increase in useful life as compared to 63Sn37Pb. SEM/EDX metallurgical analysis of the solder/Ni-Au plated Kovar^TM nosetube interface indicates that AuSn₄ intermetallic formed during soldering with 63Sn37Pb also contributes to joint weakening, whereas no brittle intermetallic is observed for 80Au20Sn. Hermetic carbon coated optical fibers metallized with Ni,P-Ni underplate and electrolytic Au overplating exhibit correspondingly similar metallurgy at the solder/fiber interface. Combined hermeticity testing and metallurgical analysis carried out on 63Sn37Pb and 80Au20Sn alloy solder sealed optical fiber feedthroughs after repetitive temperature cycling between -65 and +150°C, and -40 and +125°C validated the analytical approach     

The effects of underfill and its material models onthermomechanical behaviors of a flip chip package

In this paper, the effects of underfill on thermomechanical behavior of two types of flip chip packages with different bumping size and stand-off height were investigated under thermal cycling both experimentally and two-dimensional (2-D) finite element simulation. The materials inelasticity, i.e., viscoelasticity of underfill U8437-3 and viscoplasticity of 60 Sn40 Pb solder, were considered in the simulations. The results show that the use of underfill encapsulant increases tremendously (~20 times) the thermal fatigue lifetime of SnPb solder joint, weakens the effects of stand-off height on the reliability, and changes the deformation mode of the package. It was found that the thermal fatigue crack occurs in the region with maximum plastic strain range, and the Coffin-Manson type equation could then be used for both packages with and without underfill. Solder joint crack initiation occurred before delamination when using underfill with good adhesion (75 MPa) and the underfill delamination may not be a dominant failure mode in the present study. The interfacial stresses at the underfill/chip interface were calculated to analyze delamination sites, which agree with the results from acoustic image. Moreover, the effects of material models of underfill, i.e., constant elasticity (EC) and temperature dependent elasticity (ET) as well as the viscoelasticity (VE), on the thermomechanical behaviors of flip chip package were also studied in the simulation. The VE model gives comparatively large plastic strain range and large displacements in the shear direction, as well as decreased solders joint lifetime. The ET model gives similar results as the VE model and could be used instead of VE in simulations for the purpose of simplicity     

WLCSP中微焊球结构尺寸对其热应力的影响

晶圆级芯片尺寸封装(WLCSP)微焊球结构尺寸对其热机械可靠性有重要的影响。通过二维有限元模拟筛选出对WLCSP微焊球及其凸点下金属层(UBM)中热应力影响显著的参数,采用完全因子实验和多因子方差统计分析定量评估各种因子影响的显著性,最后建立三维模型,用子模型技术研究关键尺寸因子对热应力变化的影响。研究发现,焊球半径是影响焊球热应力的最关键尺寸因子,电镀铜开口和铜焊盘厚度对焊球热应力的影响也较显著;钝化层开口和焊球半径是影响UBM热应力的最关键尺寸因子。随着焊球半径增大,焊球热应力减小。