Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-/spl kappa/ dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-/spl kappa/ dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/A(2-5/spl times/10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8/spl times/10/sup 17/ cm/sup -3/eV/sup -1/ to 1.3/spl times/10/sup 19/ cm/sup -3/eV/sup -1/, somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-/spl kappa//gate stacks, relative comparison among them and to the Si--SiO/sub 2/ system.     

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-K dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-K dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/ A(2-5 /spl times/ 10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8 /spl times/ 10/sup 17/ cm/sup -3/ eV/sup -1/ to 1, 3 /spl times/ 10/sup 19/ cm/sup -3/ eV/sup -1/ somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-K/gate stacks, relative comparison among them and to the Si-SiO/sub 2/ system.     

A simple approach to fabrication of high-quality HfSiON gate dielectrics with improved nMOSFET performances

A simple technique to form high-quality hafnium silicon oxynitride (HfSiON) by rapid thermal processing oxidation of physical vapor deposition hafnium nitride (HfN) thin films on ultrathin silicon oxide (SiO/sub 2/) or silicon oxynitride (SiON) layer is presented. Metal TaN gate electrode is also introduced into such HfSiON stacks. Excellent performances including large electron mobility (85%SiO/sub 2/at0.2 MV/cm), low leakage current (10/sup -4/ of SiO/sub 2/), and superior time-dependant dielectric breakdown reliability are achieved in HfSiON/SiO/sub 2/ stacks, and these results suggest such stacks are very promising for the low-power SOC applications in the near future. In addition, the improvement of the electron mobility in this HfSiON/SiO/sub 2/ stack by a reduction of the border traps in the HfSiON dielectric is demonstrated.     

1.5-V single work-function W/WN/n/sup +/-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

This letter reports on 1.5-V single work-function W/WN/n/sup +/-poly gate CMOS transistors for high-performance stand-alone dynamic random access memory (DRAM) and low-cost low-leakage embedded DRAM applications. At V/sub dd/ Of 1.5-V and 25/spl deg/C, drive currents of 634 /spl mu/A//spl mu/m for 90-nm L/sub gate/ NMOS and 208 /spl mu/A-/spl mu/m for 110-nm L/sub gate/ buried-channel PMOS are achieved at 25 pA//spl mu/m off-state leakage. Device performance of this single work function technology is comparable to published low leakage 1.5-V dual work-function technologies and 25% better than previously reported 1.8-V single work-function technology. Data illustrating hot-carrier immunity of these devices under high electric fields is also presented. Scalability of single work-function CMOS device design for the 90-nm DRAM generation is demonstrated.     

Film Properties of MoSi/sub 2/ and Their Application to Self-Aligned MoSi/sub 2/ Gate MOSFET

Molybdenum silicide (MoSi/sub 2/) gate technology has been extensively investigated in conjunction with MOS device performance and reliability. Features of the MoSi/sub 2/) gate technology are to realize a low resistivity of 1 X 10/sup -4/ Omega · cm for both gate and interconnection, and to give rise to higher reliability under both positive and negative bias stress of 2 MV/cm at 250/spl deg/C. Problems on the ohmic contact between MoSi/sub 2/ and single-crystal substrates are not completely solved yet, particularly when the device is processed at high temperature after MoSi/sub 2/ deposition.     

n/sup +/-InAs-InAlAs recess gate technology for InAs-channel millimeter-wave HFETs

We report a submicrometer, self-aligned recess gate technology for millimeter-wave InAs-channel heterostructure field effect transistors. The recess gate structure is obtained in an n/sup +/-InAs-InAlAs double cap layer structure with a citric-acid-based etchant. From molecular-beam epitaxy-grown material functional devices with 1000-, 500-, and 200-nm gate length were fabricated. From all three device geometries we obtain drive currents of at least 500 mA/mm, gate leakage currents below 2 mA/mm, and RF-transconductance of 1 S/mm. For the 200-nm gate length device f/sub /spl tau// and f/sub max/ are 162 and 137 GHz, respectively. For the 500-nm gate length device f/sub /spl tau// and f/sub max/ are 89 and 140 GHz, respectively. We observe scaling limitations at 200-nm gate length, in particular a negative threshold voltage shift from -550 to -810 mV, increased kink-effect, and a high gate-to-drain capacitance of 0.5 pF/mm. The present limitations to device scaling are discussed.     

Fully silicided NiSi gate on La/sub 2/O/sub 3/ MOSFETs

We have fabricated the fully silicided NiSi on La/sub 2/O/sub 3/ for n- and p-MOSFETs. For 900/spl deg/C fully silicided CoSi/sub 2/ on La/sub 2/O/sub 3/ gate dielectric with 1.5 nm EOT, the gate dielectric has large leakage current by possible excess Co diffusion at high silicidation temperature. In sharp contrast, very low gate leakage current density of 2/spl times/10/sup -4/ A/cm/sup 2/ at 1 V is measured for 400/spl deg/C formed fully silicided NiSi and comparable with Al gate. The extracted work function of NiSi was 4.42 eV, and the corresponding threshold voltages are 0.12 and -0.70 V for respective n- and p-MOSFETs. Electron and hole mobilities of 156 and 44 cm/sup 2//V-s are obtained for respective n- and p-MOSFETs, which are comparable with the HfO/sub 2/ MOSFETs without using H/sub 2/ annealing.     

Characterization and reliability of dual high-k gate dielectric stack (poly-Si-HfO/sub 2/-SiO/sub 2/) prepared by in situ RTCVD process for system-on-chip applications

We investigate for the first time the possibility of integrating chemical vapor deposition (CVD) HfO/sub 2/ into the multiple gate dielectric system-on-a-chip (SoC) process in the range of 6-7 nm, which supports higher voltage (2.5-5 V operation/tolerance). Results show that CVD HfO/sub 2/-SiO/sub 2/ stacked gate dielectric (EOT =6.2 nm) exhibits lower leakage current than that of SiO/sub 2/ (EOT =5.7 nm) by a factor of /spl sim/10/sup 2/, with comparable interface quality (D/sub it//spl sim/1/spl times/10/sup 10/ cm/sup -2/eV/sup -1/). The presence of negative fixed charge is observed in the HfO/sub 2/-SiO/sub 2/ gate stack. In addition, the addition of HfO/sub 2/ on SiO/sub 2/ does not alter the dominant conduction mechanism of Fowler-Nordheim tunneling in the HfO/sub 2/-SiO/sub 2/ gate stack. Furthermore, the HfO/sub 2/-SiO/sub 2/ gate stack shows longer time to breakdown T/sub BD/ than SiO/sub 2/ under constant voltage stress. These results suggest that it may be feasible to use such a gate stack for higher voltage operation in SoC, provided other key requirements such as V/sub t/ stability (charge trapping under stress) can be met and the negative fixed charge eliminated.     

Electrical characteristics of 8-/spl Aring/ EOT HfO/sub 2//TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown junctions

The authors demonstrate high-performing n-channel transistors with a HfO/sub 2//TaN gate stack and a low thermal-budget process using solid-phase epitaxial regrowth of the source and drain junctions. The thinnest devices have an equivalent oxide thickness (EOT) of 8 /spl Aring/, a leakage current of 1.5 A/cm/sup 2/ at V/sub G/=1 V, a peak mobility of 190 cm/sup 2//V/spl middot/s, and a drive-current of 815 /spl mu/A//spl mu/m at an off-state current of 0.1 /spl mu/A//spl mu/m for V/sub DD/=1.2 V. Identical gate stacks processed with a 1000-/spl deg/C spike anneal have a higher peak mobility at 275 cm/sup 2//V/spl middot/s, but a 5-/spl Aring/ higher EOT and a reduced drive current at 610 /spl mu/A//spl mu/m. The observed performance improvement for the low thermal-budget devices is shown to be mostly related to the lower EOT. The time-to-breakdown measurements indicate a maximum operating voltage of 1.6 V (1.2 V at 125 /spl deg/C) for a ten-year lifetime, whereas positive-bias temperature-instability measurements indicate a sufficient lifetime for operating voltages below 0.75 V.     

GaAs MOSFET with oxide gate dielectric grown by atomic layer deposition

For the first time, a III-V compound semiconductor MOSFET with the gate dielectric grown by atomic layer deposition (ALD) is demonstrated. The novel application of the ALD process on III-V compound semiconductors affords tremendous functionality and opportunity by enabling the formation of high-quality gate oxides and passivation layers on III-V compound semiconductor devices. A 0.65-/spl mu/m gate-length depletion-mode n-channel GaAs MOSFET with an Al/sub 2/O/sub 3/ gate oxide thickness of 160 /spl Aring/ shows a gate leakage current density less than 10/sup -4/ A/cm/sup 2/ and a maximum transconductance of 130 mS/mm, with negligible drain current drift and hysteresis. A short-circuit current-gain cut-off frequency f/sub T/ of 14.0 GHz and a maximum oscillation frequency f/sub max/ of 25.2 GHz have been achieved from a 0.65-/spl mu/m gate-length device.     

A novel InGaP/InGaAs/GaAs double /spl delta/-doped pHEMT with camel-like gate structure

The author reports a novel InGaP/InGaAs/GaAs double delta-doped pseudomorphic high-electron mobility transistor (pHEMT) with n/sup +/-GaAs/p/sup +/-InGaP/n-InGaP camel-like gate structure grown by MOCVD. Due to the p-n depletion from the p/sup +/-InGaP gate to the channel region and the presence of /spl Delta/Ec at the InGaP/InGaAs heterostructure, the turn-on voltage of gate is larger than 1.7 V. For a 1/spl times/100-/spl mu/m/sup 2/ device, the experimental results show an extrinsic transconductance of 107 mS/mm and a saturation current density of 850 mA/mm. Significantly, an extremely broad gate voltage swing larger than 6 V with above 80% maximum g/sub m/ is obtained. Furthermore, the unit current cut-off frequency f/sub T/ and maximum oscillation frequency are up to 20 and 32 GHz, respectively. The excellent device performance provides a promise for linear and large signal amplifiers and high-frequency circuit applications.     

Copper gate AlGaN/GaN HEMT with low gate leakage current

Copper (Cu) gate AlGaN/GaN high electron mobility transistors (HEMTs) with low gate leakage current were demonstrated. For comparison, nickel/gold (Ni/Au) gate devices were also fabricated with the same process conditions except the gate metals. Comparable extrinsic transconductance was obtained for the two kinds of devices. At gate voltage of -15 V, typical gate leakage currents are found to be as low as 3.5/spl times/10/sup -8/ A for a Cu-gate device with gate length of 2 /spl mu/m and width of 50 /spl mu/m, which is much lower than that of Ni/Au-gate device. No adhesion problem occurred during these experiments. Gate resistance of Cu-gate is found to be about 60% as that of NiAu. The Schottky barrier height of Cu on n-GaN is 0.18 eV higher than that of Ni/Au obtained from Schottky diode experiments. No Cu diffusion was found at the Cu and AlGaN interface by secondary ion mass spectrometry determination. These results indicate that copper is a promising candidate as gate metallization for high-performance power AlGaN/GaN HEMT.     

TDDB and polarity-dependent reliability of high-quality, ultrathin CVD HfO/sub 2/ gate stack with TaN gate electrode

In this letter, we present a comprehensive study on longterm reliability of ultrathin TaN-gated chemical vapor deposition gate stack with EOT=8.5-10.5. It is found that, due to the asymmetric band structure of HfO/sub 2/ gate stack with an interfacial layer, the HfO/sub 2/ gate stack shows polarity-dependent leakage current, critical defect density, and defect generation rate, under gate and substrate injection. However, no such polarity dependence of time-to-breakdown (T/sub BD/) is observed when T/sub BD/ is plotted as a function of gate voltage. The 10-year lifetime of an HfO/sub 2/ gate stack is projected to be Vg=-1.63 V for the equivalent oxide thickness (EOT) =8.6 and Vg=-1.88 V for EOT=10.6 at 25/spl deg/C. These excellent reliability characteristics are attributed to reduced leakage current of HfO/sub 2/ gate stack with physically thicker films that result in larger critical defect density and Weibull slope to that of SiO/sub 2/ for the same EOT. However, at 150/spl deg/C, and with area scaling to 0.1 cm/sup 2/ and low percentile of 0.01%, the maximum allowed voltages are projected to Vg=-0.6 V and -0.75 V for EOT of 8.6, and 10.6, respectively.     

Investigations of high-performance GaAs solar cells grown on Ge-Si/sub 1-x/Ge/sub x/-Si substrates

High-performance p/sup +//n GaAs solar cells were grown and processed on compositionally graded Ge-Si/sub 1-x/Ge/sub x/-Si (SiGe) substrates. Total area efficiencies of 18.1% under the AM1.5-G spectrum were measured for 0.0444 cm/sup 2/ solar cells. This high efficiency is attributed to the very high open-circuit voltages (980 mV (AM0) and 973 mV (AM1.5-G)) that were achieved by the reduction in threading dislocation density enabled by the SiGe buffers, and thus reduced carrier recombination losses. This is the highest independently confirmed efficiency and open-circuit voltage for a GaAs solar cell grown on a Si-based substrate to date. Larger area solar cells were also studied in order to examine the impact of device area on GaAs-on-SiGe solar cell performance; we found that an increase in device area from 0.36 to 4.0 cm/sup 2/ did not degrade the measured performance characteristics for cells processed on identical substrates. Moreover, the device performance uniformity for large area heteroepitaxial cells is consistent with that of homoepitaxial cells; thus, device growth and processing on SiGe substrates did not introduce added performance variations. These results demonstrate that using SiGe interlayers to produce "virtual" Ge substrates may provide a robust method for scaleable integration of high performance III-V photovoltaics devices with large area Si wafers.     

Improved reliability of HfO/sub 2//SiON gate stack by fluorine incorporation

Effects of fluorine (F) incorporation on the reliabilities of pMOSFETs with HfO/sub 2//SiON gate stacks have been studied. In this letter, fluorine was incorporated during the source/drain implant step and was diffused into the gate stacks during subsequent dopant activation. The authors found that F introduction only negligibly affects the fundamental electrical properties of the transistors, such as threshold voltage V/sub th/, subthreshold swing, gate leakage current, and equivalent oxide thickness. In contrast, reduced generation rates in interface states and charge trapping under constant voltage stress and bias temperature stress were observed for the fluorine-incorporated split. Moreover, the authors demonstrated for the first time that F incorporation could strengthen the immunity against plasma charging damage.     

Schottky-barrier S/D MOSFETs with high-k gate dielectrics and metal-gate electrode

This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-/spl kappa/ gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D) , excellent electrical performance of I/sub on//I/sub off//spl sim/10/sup 7/-10/sup 8/ and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi/sub 2-x/ S/D , I/sub on//I/sub off/ can reach /spl sim/10/sup 5/ at V/sub ds/ of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-/spl kappa/ dielectric and metal-gate materials to be used in the future generation CMOS technology.     

High-efficiency enhancement-mode power heterojunction FET with buried p/sup +/-GaAs gate structure for low-voltage-operated mobile applications

This letter describes a successfully developed enhancement-mode double-doped AlGaAs/InGaAs/AlGaAs heterojunction FET with a buried p/sup +/-n junction gate structure for low-voltage-operated mobile applications. The buried p/sup +/-GaAs gate structure effectively reduced on-resistance (R/sub on/) and suppressed drain-current frequency dispersion for the device with high positive threshold voltage, resulting in high-efficiency characteristics under low-voltage operation. The fabricated p/sup +/-gate HJFET exhibited a low R/sub on/ of 1.4 /spl Omega//spl middot/mm with a threshold voltage of +0.4 V. Negligible frequency dispersion characteristics were obtained through pulsed current-voltage measurements for the device. Under a single 2.7-V operation, a 19.8-mm gate width device exhibited a power added efficiency of 51.9% with 26.8-dBm output power and a -40.1-dBc adjacent channel power ratio using a 1.95-GHz wideband code-division multiple-access signal.     

Effects of annealing on charge in HfO/sub 2/ gate stacks

This letter presents a systematic investigation of charge in HfO/sub 2/ gate stacks. Assuming that the majority of charge is associated with the stack interfaces, it is found that the charge at the HfO/sub 2//interfacial layer (IL) interface is negative while the charge at the Si/IL interface is positive. In general, the calculated charge densities at both interfaces are of order 10/sup 12/ cm/sup -2/. A forming gas anneal (FGA) reduces the interface charge greatly at both interfaces. However, the FGA temperature does not have much effect on the charge density. The effects of post deposition anneal at various temperatures and under various atmospheres are also studied. Its found that a high temperature dilute oxidizing atmosphere anneal reduces the charge at both interfaces.     

A study on charge reduction in HfO/sub 2/ gate stacks

Charge in metal-organic chemical vapor deposition-grown HfO/sub 2/ gate stacks has been systematically studied using nMOS capacitors. It is found that, for these films, the charge in the stack is mainly concentrated at the interfaces between the layers and is negative at the HfO/sub 2//interfacial layer (IL) interface and positive at the Si/IL interface. In general, the calculated charge densities at both interfaces are of order 10/sup 12/ cm/sup -2/. A forming gas anneal (FGA) reduces both interface charge greatly. The FGA can also significantly reduce the hysteresis and interface state density. The effects of post deposition anneal at various temperatures and under various ambients have also been studied. It is found that a high-temperature dilute oxidizing ambient anneal followed by an FGA reduces the charge at both interfaces.     

Submicrometer thin gate oxide P-channel transistors with P+polysilicon gates for VLSI applications

Submicrometer p-channel transistors have been fabricated using thin (150 Å) gate oxide and p+ polysilicon gates. Favorable device characteristics have been achieved for L(eff) as low as 0.4 µm. P+ gate was formed under different processing conditions. Data showed negligible boron penetration through the thin oxide. Two-dimensional simulations demonstrated the advantages of p+ poly in reducing short channel effects. Experimental results from three device lots with different processing conditions showed good subthreshold slope and low leakage current, even for low threshold voltages. VTversus L(eff) showed much less threshold drop than was seen using n+ poly. Device characteristics were robust with respect to processing variations.