SiO_2介质材料辐射损伤测试结构设计

为研究CMOS器件与电路的辐射效应,文中提出了SiO2介质材料辐射损伤测试结构的设计思想。针对栅氧化层和场氧化层在器件中位置、作用和结构上的差异,分别设计了用于场氧化层测试的多栅结构和用于栅氧化层测试的封闭栅结构以及Dog-Bone栅结构。为CMOS器件辐射损伤机理及辐射加固提供了新的样品和研究方法。     

用于测试CMOS输出驱动器电流变化率的新电路

提出了一种新的用于测试 CMOS输出驱动器电流变化率的电路结构 .它把片上电感引入到测试系统中作为对实际封装寄生电感的等效 ,从而排除了测试时复杂的芯片 -封装界面的影响 .这种电路结构不仅可以用于实际测算输出驱动器的性能指标 ,还可以用于研究 VL SI电路中的同步开关噪声问题 .该设计方法在新加坡特许半导体公司的 0 .6μm CMOS工艺线上进行了流片验证 .测试结果表明 ,这一测试结构能有效地表征 CMOS输出驱动器的电流变化率的性能指标和 VL SI电路中的同步开关噪声特性     

用于测试CMOS输出驱动器电流变化率的新电路

提出了一种新的用于测试CMOS输出驱动器电流变化率的电路结构．它把片上电感引入到测试系统中作为对实际封装寄生电感的等效,从而排除了测试时复杂的芯片-封装界面的影响．这种电路结构不仅可以用于实际测算输出驱动器的性能指标,还可以用于研究VLSI电路中的同步开关噪声问题．该设计方法在新加坡特许半导体公司的0.6μm CMOS工艺线上进行了流片验证．测试结果表明,这一测试结构能有效地表征CMOS输出驱动器的电流变化率的性能指标和VLSI电路中的同步开关噪声特性．     

低噪声、低功耗微电容读出ASIC设计

针对差分电容式微电子机械系统(MEMS)加速度计,设计了一种低噪声、低功耗微电容读出专用集成电路(ASIC)。电路采用开关电容结构,使用相关双采样(CDS)技术降低电容-电压(C-V)转化电路的低频噪声和偏移电压。通过优化MEMS表头噪声匹配、互补金属氧化物半导体(CMOS)开关和低噪声运算放大器来降低频带内的混叠热噪声。采用电源开关模块和门控时钟技术来降低电路功耗,同时集成自检测电路和温度传感器。采用混合CMOS工艺进行流片加工,测试结果表明,优化后ASIC的电容分辨率为槡1.203 aF/Hz,系统分辨率为0.168 mg(量程2 g),芯片功耗约为2 mW。同时,该ASIC还具有很好的上电特性和稳定性。     

电子工艺

IELDVD068:9849 0603383 2005年微电子测试结构会议录=2005 International Conference on Microelectronic Test Structures[会,英]／ IEEE Electron Devices Society．-P．270(E) 本会议录收集了会上发表的100篇论文,内容涉及90nm CMOS工艺,深亚微米CMOS铜互连工艺失效分析测试,硅片微波测量增强信号端隔离容量,集成     

MEMS湿度传感器信号采集与数字化处理研究

MEMS（微电子机械系统）湿度传感器是利用标准的CMOS技术加上MEMS的后处理技术制造,以其体积小、响应快等优点受到越来越多的重视,介绍了本实验室研制的MEMS压阻式湿度传感器的测试原理、硬件电路的设计和传输函数模型的建立,以及软件设计和封装设计,最后给出了样机的测试结果。     

真空微电子平板摄像管10×10像素驱动电路的设计与制作

真空微电子平板摄像是一种全新的摄像理论,它采用碳纳米场发射阴极、栅极和阳极(收集极)三极管结构。介绍了真空微电子平板摄像管驱动电路的设计要求、设计思路和电路测试结果,实验中采用的栅极驱动对驱动电路(扫描电路)起到了关键作用。     

短波320×256抗辐射加固读出电路设计

设计了一款采用CMOS工艺的短波320×256抗辐射加固读出电路,分析了CMOS工艺抗辐射的特点,重点介绍了模拟通路、偏压产生电路和数字电路的加固设计方法,采用了双环保护结构、对NMOS管使用环形栅和冗余设计等措施。该设计电路经过流片,测试结果表明该抗辐射加固设计方法有效可行。     

实现分离神经间信号再生和功能重建用的微电子神经桥

根据神经信号的特性设计了微电子神经桥。微电子神经桥包括神经信号探测电极、功能电激励电极和神经信号放大、处理及功能电激励驱动电路,其核心电路采用集成电路0.5μm CMOS工艺实现,已经通过电学测试并应用于动物实验。文中设计了一个特别的实验方案以验证微电子神经桥的可行性。在微电子神经桥辅助下,脊蟾蜍的缩腿反射可以在另外一只脊蟾蜍对应腿上重建。经过相关性分析,受控脊蟾蜍的坐骨神经信号相对于信源脊蟾蜍的坐骨神经信号延迟0.72ms,而且互相干函数值达到0.73,所以受控坐骨神经信号与信源坐骨神经信号显著相关,与反射相关的神经功能得到再生。实验证明微电子神经桥可以在异体神经间实现功能重建。     

一种12bit CMOS全差分SAR ADC

本文设计一种12bit CMOS全差分SAR ADC,分析了其电路原理和结构,阐述各部分电路对ADC性能的影响,提出新型DAC_SUB电阻串和时间自调节比较器结构,并推算VCM抖动对电路的影响。基于TSMC 0.18μm 1.8V/3.3V CMOS工艺,采用全差分阻容混合式结构,实现ADC设计。本设计ADC的核心版图尺寸为390um×780um,测试结果显示,在1MS/s采样率下,当输入信号频率为31.37kHz时,该ADC的ENOB达到10.76Bit,功耗约为2mW。     

监测CMOS IC关键失效的微电子测试结构

介绍了ＣＭＯＳ ＩＣ的静电放电微电子测试结构，叙述了双极－ＭＯＳ兼容的闭锁效应和闭锁滞后现象的微电子测试结构，并对测试结果进行了讨论。     

Prospects for using submicron CMOS VLSI in fault-tolerant equipment operating under exposure to atmospheric neutrons

Single-event upsets and latchups, whose removal is the subject of designing fault- tolerant VLSI and VLSI-based equipment, are the main effects of VLSI exposure to atmospheric neutrons. For a comparative analysis of the fault tolerance of CMOS structures with various design standards, we have investigated domestic and foreign CMOS VLSI with design standards from 0.5 to 0.13 μm and additionally produced test structures of submicron SRAMs with design standards of 0.5, 0.35, and 0.18 μm. The SOI CMOS technology provides the highest efficiency among the design-technological methods. There are no latchups in the specimens of test structures with design standards of 0.5 and 0.35 μm exposed to 250-MeV and 1-GeV protons. We recommend developing the basic components of submicron VLSI with an enhanced resistance to atmospheric neutrons based on techniques that include the typical SEU cross sections and the thyristor- effect cross sections obtained here for CMOS VLSI with various design standards.     

Test chip based approach to automated diagnosis of CMOS yieldproblems

The authors describe a design approach for, and experimental results obtained from, a test chip developed for the purpose of automated diagnosis of random-defect-dominated yield problems of CMOS ICs. Unlike test chips comprised of ad hoc collections of test structures, the test chip described here is based on the notion of systematic structural decomposition, employed to ensure complete sets of structures required for unambiguous identification of all structural features associated with electrical faults. Test structure selection, sizing, layout, testing, and data analysis are discussed, and examples of rejected wafers are presented to illustrate the direct and straightforward way in which unambiguous diagnosis are obtained. Conclusions related to implementation of an expert system for automated CMOS process problem diagnosis employing the data obtained from this test chip are summarized     

IC test structures for multilayer interconnect stress determination

A new method for measuring strain in multilayer integrated circuit (IC) interconnects is presented. This method utilizes process compatible MEMS-based test structures and is applied to the determination of longitudinal interconnect stress in a standard dual-metal-layer CMOS process. Strain measurements are shown to be consistent for an array of similar test structures. Stress values, calculated from constitutive relations, are in good agreement with published results     

Evaluation on board-level noise filter networks to suppress transient-induced latchup in CMOS ICs under system-level ESD test

Different types of board-level noise filter networks are evaluated to find their effectiveness for improving the immunity of CMOS ICs against the transient-induced latchup (TLU) under the system-level electrostatic discharge (ESD) test. By choosing proper components in each noise filter network, the TLU immunity of CMOS ICs can be greatly improved. All the experimental evaluations have been verified with the silicon-controlled rectifier (SCR) test structures and the ring oscillator circuit fabricated in a 0.25-/spl mu/m CMOS technology. Some board-level solutions can be further integrated into the chip design to effectively improve the TLU immunity of CMOS IC products.     

Characterization of parasitic transistors to evaluate CMOS processuniformity

The design and fabrication of several families of parasitic transistors available in a standard CMOS process are discussed and their application to process control examined. These transistors are characterized and their extracted parameters correlated with those obtained from CMOS devices. From these correlations it is concluded that parasitic transistors are very sensitive to changes in the process that influence the performance of MOS transistors. As a result parasitic transistors can be used in conjunction with standard MOS devices and test structures to provide a more complete picture of CMOS process variation     

Test structures to measure the heat capacity of CMOS layersandwiches

We report novel thermal characterization microstructures to measure the heat capacity of CMOS thin film sandwiches. This parameter is relevant, e.g., for the dynamic response of thermal CMOS microtransducers and for the thermal management of integrated circuits. The test structures were fabricated using a commercial 2-μm CMOS process, followed by maskless micromachining. The propagation of heat waves in the structures is monitored, which provides the thermal conductivity and heat capacity of CMOS thin film sandwiches. At 300 K, volumetric heat capacities of (1.71±0.12)×10⁶ Jm ^-3K^-1 and (2.41±1.88)×10⁶ Jm^-3K^-1 were obtained for the sandwich of CMOS dielectrics and for the lower CMOS metal, respectively. These values do not deviate significantly from available bulk data of such materials     

Design of a comprehensive process evaluation vehicle for development of small geometry CMOS process

The design of a comprehensive process evaluation vehicle for thorough evaluation of a small geometry CMOS process has been discussed in this paper. The process evaluation vehicle includes both parametric and functional test structures and is considered to be particularly useful for the development of a small geometry CMOS process.     

A new technique to accurately determine latch-up holding conditions using light excitation

A simple and accurate method to determine the true CMOS latch-up holding current and voltage by avoiding the "quasi-stable" negative resistance region is reported. A combination of microscope light excitation and a low-output impedance programmable power supply permits millivolt resolution, eliminates the need for a series current limiting resistor, and allows automatic testing. Results from test structures fabricated with n-well CMOS process are used to illustrate the method. With the terminal voltage during the excitation only 20-100 mV above the holding voltage, the method is practically nondestructive and therefore especially suitable for characterization of structures with high latch-up currents.