Analysis and design of a fully integrated CMOS low‐noise amplifier for concurrent dual‐band receivers

This article thoroughly analyzes a concurrent dual‐band low‐noise amplifier (LNA) and carefully examines the effects of both active and passive elements on the performance of the dual‐band LNA. As an example of the analysis, a fully integrated dual‐band LNA is designed in a standard 0.18‐μm 6M1P CMOS technology from the system viewpoint for the first time to provide a higher gain at the high band in order to compensate the high‐band signal's extra loss over the air transmission. The LNA drains 6.21 mA of current from a 1.5‐V supply voltage and achieves voltage gains of 14 and 22 dB, input S₁₁ of 15 and 18 dB, and noise figures of 2.45 and 2.51 dB at 2.4 and 5.2 GHz, respectively. © 2006 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2006.     

A W‐band RF‐MEMS switched LNA in a 70 nm mHEMT process

This work presents a monolithic integrated reconfigurable active circuit consisting of a W‐band RF micro‐electro‐mechanical‐systems (MEMS) Dicke switch network and a wideband low‐noise amplifier (LNA) realized in a 70 nm gallium arsenide (GaAs) metamorphic high electron mobility transistor process technology. The RF‐MEMS LNA has a measured gain of 10.2–15.6 dB and 1.3–8.2 dB at 79–96 GHz when the Dicke switch is switched ON and OFF, respectively. Compared with the three‐stage LNA used in this design the measured in‐band noise figure (NF) of MEMS switched LNA is minimum 1.6 dB higher. To the authors’ knowledge, the experimental results represent a first time demonstration of a W‐band MEMS switched LNA monolithic microwave integrated circuit (MMIC) in a GaAs foundry process with a minimum NF of 5 dB. The proposed novel integration of such MEMS switched MMICs can enable more cost‐effective ways to realize high‐performance single‐chip mm‐wave reconfigurable radiometer front‐ends for space and security applications, for example. © 2015 Wiley Periodicals, Inc. Int J RF and Microwave CAE 25:639–646, 2015.     

A miniature low‐power ultra‐wideband low noise amplifier in 0.18 μm CMOS

A 0.18‐μm CMOS low‐noise amplifier (LNA) operating over the entire ultra‐wideband (UWB) frequency range of 3.1–10.6 GHz, has been designed, fabricated, and tested. The UWB LNA achieves the measured power gain of 7.5 ± 2.5 dB, minimum input matching of ?8 dB, noise figure from 3.9 to 6.3 dB, and IIP3 from ?8 to ?1.9 dBm, while consuming only 9 mW over 3–10 GHz. It occupies only 0.55 × 0.4 mm² without RF and DC pads. The design uses only two on‐chip inductors, one of which is such small that could be replaced by a bonding wire. The gain, noise figure, and matching of the amplifier are also analyzed. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE , 2011.     

A straightforward design technique for narrowband multi‐stage low‐noise amplifiers with I/O conjugate match

Low‐noise amplifier (LNA) designers often struggle to simultaneously satisfy gain, noise, stability, and I/O matching requirements. In this article, a novel design technique, tailored for two‐stage low‐noise amplifiers, is presented. The proposed design method is completely deterministic and exploits inductive source degeneration to obtain a two‐stage LNA featuring perfect input and output match together with low noise figure (NF) and a pre‐determined gain, including stability analysis. A novel flowchart is provided together with the corresponding design chart that contains gain, matching, and stability information, therefore addressing all key figures‐of‐merit of a linear amplifier. The design chart is easily implementable in commercial Electronic Design Automation software, to aid designers in the difficult task of selecting the appropriate source degeneration inductor value. The noise performance, on the other hand, is the best possible since the matching networks are designed to provide the input of the two Field Effect Transistors with the optimum termination for noise. The design method is validated with two separate test vehicles operating respectively at Ka‐band (26.5‐31.5 GHz) and K‐band (20.0‐24.0 GHz). The realized Monolithic Microwave Integrated Circuits exhibit 18 dB gain for both versions, NF of 1.5 and 1.2 dB, respectively for the Ka‐band and K‐band version. Input and output matching are typically better than 12 and 15 dB.     

Design and layout techniques for a mm‐wave body‐biased variable‐gain amplifier

A two‐stage mm‐wave variable‐gain amplifier is designed and implemented in a 65‐nm CMOS technology. A fully symmetric layout has been utilized to suppress the odd‐mode of propagation and increase the quality factor in co‐planar waveguide transmission lines. Moreover, a new design technique is proposed for implementing decoupling capacitors for mm‐wave frequencies. Body‐biasing technique is utilized to change the amplifier gain without significant change in the overall power consumption of the circuit. The measurement results show that the amplifier achieves a peak gain of 10 dB with a gain variation range of 25 dB while consuming 12 mW from a 1.2‐V supply. © 2013 Wiley Periodicals, Inc. Int J RF and Microwave CAE 24:470–477, 2014.     

A 3.4 dB NF k‐band LNA with a tapped capacitor matching network in 65 nm CMOS technology

This article proposes a tapped capacitor network for low‐noise amplifier (LNA) input matching which can provide much broader bandwidth than traditional ones. According to the design, the implemented LNA can realize noise match and power match simultaneously, which will broaden LNA's bandwidth without introducing larger noise than traditional ones. In addition, input pad parasitic capacitance can be absorbed by the network. Then a k‐band LNA with the matching network designed in 65 nm CMOS technology is shown to demonstrate the performance of the matching network. The tested results show that frequency band of S₁₁ less than ?10 dB is about 17 GHz and minimum NF is about 3.4 dB. © 2014 Wiley Periodicals, Inc. Int J RF and Microwave CAE 25:146–153, 2015.     

Analysis and design of packaged and ESD protected BiCMOS RF front‐end for a UHF receiver

The design of packaged and ESD protected RF front‐end circuits for UHF receiver working at ISM band is presented. By extensively evaluating the effects of the package and ESD parasitics on the LNA input impedance, transconductance, and noise figure, some useful guidelines on the design of inductively degenerated common emitter LNA with package and ESD protection are provided. In addition, by taking advantage of both the bipolar and MOSFET devices, a BiFET mixer with low noise and high linearity is also described in this article. With the careful consideration of the tradeoffs among noise figure, linearity, power gain, and power consumption, the front‐end is implemented in a generic low‐cost 0.8‐μm BiCMOS technology. The on‐board measurement of the packaged RF front‐end circuits demonstrates a 20.3‐dB power gain, 2.6‐dB DSB noise figure, and ?9.5‐dBm input referred third intercept point while consuming about 3.9‐mA current. © 2007 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2007.     

18‐31 GHz GaN wideband low noise amplifier (LNA) using a 0.1 μm T‐gate high electron mobility transistor (HEMT) process

GaN technology has attracted main attention towards its application to high‐power amplifier. Most recently, noise performance of GaN device has also won acceptance. Compared with GaAs low noise amplifier (LNA), GaN LNA has a unique superiority on power handling. In this work, we report a wideband Silicon‐substrate GaN MMIC LNA operating in 18‐31 GHz frequency range using a commercial 0.1 μm T‐Gate high electron mobility transistor process (OMMIC D01GH). The GaN MMIC LNA has an average noise figure of 1.43 dB over the band and a minimum value of 1.27 dB at 23.2 GHz, which can compete with GaAs and InP MMIC LNA. The small‐signal gain is between 22 and 25 dB across the band, the input and output return losses of the MMIC are less than ?10 dB. The P_1dB and OIP3 are at 17 dBm and 28 dBm level. The four‐stage MMIC is 2.3 × 1.0 mm² in area and consumes 280 mW DC power. Compared with GaAs and InP LNA, the GaN MMIC LNA in this work exhibits a comparative noise figure with higher linearity and power handling ability.     

2–6 GHz GaN distributed power amplifier MMIC with tapered gate‐series/drain‐shunt capacitors

In this article, using a 0.25 μm GaN HEMT process, we present a 2–6 GHz GaN two‐stage distributed power amplifier MMIC that utilizes tapered gate series capacitors and nonuniform drain transmission lines with tapered shunt capacitors to simultaneously obtain a linear gain enhancement and optimum load line for each transistor. By using well‐derived equations to provide each transistor with the optimum load impedance and to tune the phase delay between the input and output transmission lines, the nonuniform distributed power amplifier is designed for second‐stage amplification, and satisfactory performance is demonstrated. The phase balance and tapering of the gate series capacitors have a role in improving the linear gain of the two‐stage amplifier. The measured data show a linear gain of 22 ± 1 dB, an input/output return loss of more than 15 dB, saturated output power of 41.2–43.1 dBm under a continuous‐wave mode, and a power‐added efficiency of 18–22% from 2 to 6 GHz which are very competitive values compared with previous works. © 2016 Wiley Periodicals, Inc. Int J RF and Microwave CAE 26:456–465, 2016.     

Analysis and improvement of PSRR in an envelope‐tracking power amplifier using a common‐drain amplifier topology

A common‐drain power amplifier (PA) for envelope tracking systems is presented. In envelope tracking, the main PA operates mostly in compression and the power supply rejection ratio (PSRR) is not high. Furthermore, the output noise of the supply modulator can be mixed with the RF signal and generates out‐of‐band emissions. In this article, instead of using a common‐source topology, the PSRR of the envelope tracking PA is inherently improved by utilizing a common‐drain topology. A comprehensive analysis shows that the common‐drain topology is less sensitive to the supply noise, as compared to the conventional common‐source topology. The proposed common‐drain PA is implemented using a discrete LDMOS PD20010‐E RF transistor. Measurement results show that the PSRR of the proposed common‐drain PA is improved by up to 7 dB as compared to that of the common‐source PA. For a two‐tone input with 10 MHz bandwidth at the center frequency of 700 MHz, the power added efficiency (PAE) and IM3 of the envelope tracking common‐drain PA are 20% and ? 28 dBc, respectively, at an average output power of 33.4 dBm. The amplifier also shows a 12.4 dB power gain. Moreover, by utilizing the envelope tracking, the PAE is improved by more than 5%.     

3GHz～5GHz CMOS超宽带低噪声放大器设计

提出了一个低噪声、高线性的超宽带低噪声放大器(UWB LNA).电路由窄带PCSNIM LNA拓扑结构和并联低Q负载结构组成,采用TSMC 0.18 μm RFCMOS工艺,并在其输入输出端引入了高阶带通滤波器.仿真结果表明,在1.8V直流电压下LNA的功耗约为10.6 mW.在3 GHz～5 GHz 的超宽带频段内,...     

Closed‐form approach to design distributed matching networks for high‐frequency amplifiers

Based on the use of distributed lossless elements, a closed‐form synthesis for double‐frequency‐matching networks is introduced with an emphasis on the design of high‐frequency amplifiers. Three different circuit conditions are considered and design relationships are provided and discussed. Finally, the proposed approach, which uses the circle method, is successfully employed to design a Ka‐band (26–32 GHz) linear amplifier with gain equal to 8 dB and return loss greater than 10 dB for the considered band. © 2006 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2006.     

Design and implementation of a dual‐band concurrent fully‐integrated LNA for WLAN IEEE 802.11a/b/g applications

This article presents a dual‐band concurrent fully‐integrated low‐noise amplifier (LNA) targeted to WLAN IEEE 802.11a/b/g standards. The use of a concurrent topology enables saving die area and power consumption compared with the parallel solution that employs two separated LNAs. An original design methodology that helps in the selection of input/output matching network element values is also presented. The LNA die area is 1.0 × 0.9 mm² and it consumes 9 mW (5 mA at 1.8 V). © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.     

A broadband hybrid GaN cascode low noise amplifier for WiMax applications

This article reports a Microstrip design for low noise amplifier (LNA) using a packaged commercial GaN‐on‐SiC high electron mobility transistor (HEMT). A cascode configuration with an inter‐stage matching and an independent biasing technique was used. A lumped elements design was first developed, analyzed, and simulated in ADS. Then the design was implemented using microstrip technology and simulated using the momentum EM simulation in ADS. The LNA is easy to fabricate, has a low cost, and can be easily modified for other applications. The proposed GaN LNA showed a gain of 13.5 dB with a noise figure (NF) of 3 dB from 2.8 to 3.8 GHz.     

Alternative approach to low‐noise amplifier design for ultra‐wideband applications

Conventional ultra‐wideband low‐noise amplifiers require a flat gain over the entire 3.1–10.6 GHz bandwidth, which severely restraints the trade‐off spaces in low noise amplifier design. This article proposes a relaxed gain‐flatness requirement based on system level investigations. Considering the wireless transceiver front‐end with antenna and propagation channel, the unflat‐gain low‐noise amplifier with an incremental gain characteristic does not degrade the performance of overall system. As an alternative to its flat‐gain counterpart, the proposed unflat gain requirement tolerates gain ripple as large as 10 dB, which greatly eases the design challenges to low‐noise amplifier for ultra‐wideband wireless receivers. Two low‐noise amplifier examples are given to demonstrate the feasibility and design flexibility under the proposed gain‐flatness requirement. © 2007 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2007.     

A comparison of three‐dimensional electromagnetic and RC parasitic extraction analysis of mm‐wave on‐chip passives in SiGe BiCMOS low‐noise amplifiers

Layout parasitics significantly impact the performance of mm‐wave microelectronic circuits. These effects may be estimated by including foundry‐qualified pcell interconnect models in schematic with or without additional RC parasitics extraction (RCPE), or by generating an EM simulation (FEM and MoM) of the layout and cosimulating with active device models. In this paper, these methods are compared at by simulating the compression (P1db), gain (S₂₁), and noise figure (NF) of a V‐band LNA in 130 nm SiGe BiCMOS and comparing the results of different simulation approaches to measurements. It is found that the FEM cosimulated results agree better with the measurements than the other methods, providing a maximum error of 0.8 dB in gain, 0.18 dB in NF, and 0.6 dB in P1dB. This is a significant improvement over the errors obtained with pcell‐based schematic (2.6 dB in gain, 0.1 dB in NF, and 2.2 dB in P1db), schematic simulation with RCPE (1.55 dB in gain, 1.15 dB in NF, and 0.8 dB in P1db), and MoM cosimulation (0.67 dB in gain, 0.72 in NF, and 0.67 in P1db). This experiment validates the preference to FEM cosimulation in mm‐wave microelectronic circuits yet would indicate that reasonably accurate first‐iteration results may be obtained through a combined pcell‐RCPE approach with significantly shorter simulation time.     

低功耗低噪声CMOS放大器设计与优化

分析了两种传统的基于共源共栅结构的低噪声放大器LNA技术:实现噪声优化和输入匹配SNIM技术并在功耗约束下同时实现噪声优化和输入匹配PCSNIM技术。针对其固有不足,提出了一种新的低功耗、低噪声放大器设计方法。     

PVT‐compensated low‐voltage and low‐power CMOS LNA for IoT applications

In this paper, a low‐noise amplifier (LNA) with process, voltage, and temperature (PVT) compensation for low power dissipation applications is designed. When supply voltage and LNA bias are close to the subthreshold, voltage has significant impact on power reduction. At this voltage level, the gain is reduced and various circuit parameters become highly sensitive to PVT variations. In the proposed LNA circuit, in order to enhance efficiency at low supply voltage, the cascade technique with g_m boosting is used. To improve circuit performance when in the subthreshold area, the forward body bias technique is used. Also, a new PVT compensator is suggested to reduce sensitivity of different circuit's parameters to PVT changes. The suggested PVT compensator employs a current reference circuit with constant output regarding temperature and voltage variations. This circuit produces a constant current by subtracting two proportional to absolute temperature currents. At a supply voltage of 0.35 V, the total power consumption is 585 μW. In different process corners, in the proposed LNA with PVT compensator, gain and noise figure (NF) variations are reduced 10.3 and 4.6 times, respectively, compared to a conventional LNA with constant bias. With a 20% deviation in the supply voltage, the gain and noise NF variations decrease 6.5 and 34 times, respectively.     

一种新型负反馈超宽带低噪声放大器的设计与实现

随着超宽带技术的发展,系统设计对低噪声放大器的性能提出了越来越高的要求。针对宽带放大器增益平坦度低。匹配性差等问题,本文从负反馈理论着手,改进了负反馈网络。通过ADS软件的辅助设计,实现了30MH—1．35GHz频段下的低噪声放大器的设计。通过对各项电路参数的优化,实现了增益为17．7dB,增益平坦度小于dB,输入输出电压驻波比小于1．5,噪声系数小于2．6的技术指标。     

Three‐dimensional printed wideband,dual‐cavity Ku‐band antenna

A novel three‐dimensional (3D) printed, wideband, and low cost bull's eye antenna is proposed and designed for Ku‐band applications. The proposed antenna covers entire Ku‐band satellite communication bands starting from 10.5 GHz to 14.5 GHz. The antenna structure consists of dual‐cavity radiating aperture surrounded by a circular groove. With the addition of cavity and corrugation, the antenna gain is increased more than 6 dB. The antenna is fabricated using 3D printing technology and conductive painting. Measurement results indicate that the antenna has 72% fractional bandwidth from 8 GHz to 17 GHz. Measured antenna peak gain is 13.5 dBi at 13 GHz and no less than 11.5 dBi throughout the entire Ku band.