基于UPC1909的有源箝位软开关变换器

在常规的硬开关电路中,由于变压器漏感及寄生电容的影响,常常在开关转换瞬间会产生很高的电压尖峰。本文采用有源箝位反激式变换器电路,实现了零电压零电流(ZVZCS)软开关变换,使电压尖峰得到了抑制。该电路成功地应用了UPCI909控制芯片,简化了传统的驱动电路。实验结果表明,主开关管两端电压被箝位在一定数值,实现了零电压零电流开关,效率达到90％。     

An Analog Delay Circuit for On-Line Visual Confirmation of Discriminated Neuroelectric Signals

An analog delay circuit which utilizes an inexpensive commercially available analog shift register is described. The delay circuit when used in conjunction with a window discriminator will display "on-line" visual confirmation of single neural events from extracellular recordings containing more than one spike class. The delay can be changed to include the entire spike waveform by adjusting a potentiometer in the delay circuit.     

Widely tunable low-power high-linearity current-mode integrator built using DG-MOSFETs

A novel tunable current-mode integrator for low-voltage low-power applications is presented using mixed-mode TCAD simulations. The design is based on independently driven double-gate (IDDG) MOSFETs, a nano-scale four-terminal device, where one gate can be used to change the characteristics of the other. Using current-mirrors built with IDDG-MOSFETs, we show that the number of active devices in the tunable current-mode integrator, 16 in bulk CMOS design, may be halved, i.e. considerable savings in both total area and power dissipation. The integrator operates with single supply voltage of 1 V and a wide range of tunable bandwidth (~2 decades) and gain (~30 dB). This linear circuit has third-order harmonic distortion as low as ?70 dB in appropriate bias conditions, which can be set via the back-gates. The impact of tuning on the IDDG integrator and conventional design using symmetrically driven (SDDG) MOSFETs is comparatively studied. The proposed design is a good example for performance leverage through IDDG MOSFET architectures in analog circuits integral to future mixed-signal systems.     

Quantized Spiking Neuron With A/D Conversion Functions

This brief presents a simple artificial spiking neuron and proposes its application to an A/D converter. Depending on the initial state, which is an analog input, the neuron can generate spike trains having various spike position patterns. Based on spike position modulation, the spike train can be symbolized by a digital output. As a result, the analog input can be encoded into the digital output. Adjusting a reconfigurable parameter, the neuron can realize various encodings such as binary and Gray encodings. This brief also proposes a simple reconfigurable implementation circuit and experimentally confirms typical A/D conversion functions     

采用电容延时和反馈的抑制毛刺复位接口电路

针对手机用TFT-LCD驱动控制芯片的应用环境具有高噪声、毛刺持续时间长的特点,提出一种采用电容充放电延时和反馈技术的抑制毛刺复位接口电路。该电路可以消除持续时间长达数微秒的单个毛刺。另外,通过自动选择不同的充放电路径,可实现不同的延迟时间,从而可以消除毛刺的累积效益。设计的复位接口电路已经成功应用于176RGB×220分辨率、26万色手机用TFT-LCD驱动控制芯片。采用0.18μmCMOS中压工艺的HSPICE仿真以及工程样片流片结果表明,所设计的复位接口电路的性能完全满足TFT-LCD驱动控制芯片的复杂应用环境要求,并且具有面积开销较小的特点。     

Bridge-arm current reduction in DC-AC inverter

When building single-phase inverter with power Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), switching action may cause poor reverse recovery characteristic due to body parasitic diode of MOSFET, which can produce peak current in the circuit loop and the high transient voltage and current (dv/dt, di/dt) during the turning-on period. In this article, a novel method to reduce the bridge arm current spike in DC-AC inverter is proposed. The presented method uses the improved and simplified coupled inductor which is connected between the upper and lower power devices. The parasitic capacitors of MOSFET are charged and discharged by the coupled inductor and the energy is released in the new loop; therefore, the bridge peak current is diminished. The time-domain model of transient-state analyses is given in detail. The current spike of the main switch is clamped efficiently. By increasing switching frequency, the volume of the magnetic core can be further reduced which is resulted from reduction in the reverse recovery current in parasitic diode. Because of the suppression of the spike current via the device, the switch-on loss of the power loss is reduced, and low on-state resistor of the power device can be adopted to suppress the conduction loss. The proposed approaches are validated with experimental results.     

IGBT关断瞬态电压尖峰影响及抑制

绝缘栅双极晶体管(IGBT)是一种性能优良的全控型电力电子器件,由于线路和器件内部分布电感的存在,关断时集电极电流的快速变化会感应产生一个较大的电压尖峰从而引起过电压击穿。分析了栅极结电容放电时间常数和拖尾电流对电压尖峰的影响,通过改变栅极驱动电阻和温度可以抑制电压尖峰。分析了电压尖峰引起过压击穿的失效机理以及失效模式,表明IGBT过压击穿引起失效的本质仍然是结温过高引起的热击穿失效。     

Extraction of Substrate Resistance in Bulk FinFETs Through RF Modeling

A new method to extract substrate resistance (R_sub) for small-sized nano-scale metal oxide semiconductor field effect transistors (MOSFETs) including bulk FinFETs is proposed and compared with conventional method. The R_sub's extracted from small-size MOSFETs by using the proposed method are shown to have frequency independent characteristics, unlike those from the conventional method. Proposed equivalent circuit explains well the R_sub behavior with body width. The proposed model showed very good agreement (error in Y₂₂~3%) with three-dimensional device simulation     

Memristive retinomorphic grid architecture removing noise and preserving edge

In this paper, special memristor circuit and memristive retina network structure for analogue image processing have been presented. The new developments on memristor element have opened various possibilities due to its being in nano-scale and having nonlinear behavior. The proposed memristor emulator consists of only one Operational Transconductance Amplifier (OTA) and two MOS transistors which are operated in sub-threshold region. The memristor fuse structure is obtained by connecting two proposed memristor emulators. In the second section of our paper, we proposed a circuit block which is composed of 16 × 16 pixels retinomorphic memristive grid to maintain a smoothed and edges preserved image. All simulation results for both proposed memristor circuits and retinomorphic grid are obtained as expected.     

一种新型低漏电ESD电源箝位电路

在到达纳米级工艺后,传统的静电放电防护(ESD)电源箝位电路的漏电对集成电路芯片的影响越来越严重。为降低漏电,设计了一种新型低漏电ESD电源箝位电路,该箝位电路通过2个最小尺寸的MOS管形成反馈来降低MOS电容两端的电压差。采用中芯国际40 nm CMOS工艺模型进行仿真,结果表明,在相同的条件下,该箝位电路的泄漏电流仅为32.59 nA,比传统箝位电路降低了2个数量级。在ESD脉冲下,该新型ESD箝位电路等效于传统电路,ESD器件有效开启。     

A wireless microsystem with digital data compression for neural spike recording

The paper describes a multi-channel neural spike recording system sensing and processing the action potentials (APs) detected by an electrode array implanted in the cortex of freely-behaving small laboratory animals. The core of the system is a custom integrated circuit (IC), with low-noise analog front-end interfaced to a 16 electrode array followed by a single 8-bit SAR ADC, a digital signal compression and a 400-MHz wireless transmission units. Data compression is implemented by detecting action potentials and storing up to 20 points per each spike waveform. The choice greatly improves data quality and allows single spike identification. The transmitter delivers a 1.25-Mbit/s data rate coded with a Manchester-coded frequency shift keying (MC-FSK) within a 3-MHz bandwidth. An overall power consumption of 17.2 mW makes possible to reach a transmission range larger than 20-m. The IC is mounted on a small and light printed circuit board. Two AAA batteries, set in a pack positioned on the back of the animal, power the system that can work continuously for more than 100 h.     

Resistorless dual-mode quadrature sinusoidal oscillator using a single active building block

This paper presents a new realization of resistorless mixed-mode (i.e. both voltage-mode and current-mode) quadrature sinusoidal oscillator using a new active building block (ABB) called the differential voltage current-controlled conveyor transconductance amplifier (DVCCCTA). The proposed oscillator circuit uses a single DVCCCTA, two grounded capacitors (GCs) and does not employ any external linear resistors. The tuning laws for the condition of oscillation (CO) and the frequency of oscillation (FO) are non-interactive; and controlled by separate bias currents. The circuit provides two explicit quadrature current outputs and two quadrature voltage outputs and thus can be classified as a mixed-mode quadrature oscillator. Another notable feature of the proposed circuit is that it can also be used as a biquadratic filter to realize low-pass and band-pass filtering functions simultaneously. Non-ideal analysis of the circuit is provided and PSpice simulation results have been included to verify the workability of the proposed circuit.     

Design of testable reversible latches by using a novel efficient implementation of Fredkin gate

ABSTRACT

Energy dissipation caused by information loss in irreversible computations will be an important limitation for the development of nano-scale circuits in the near future. Reductions in energy dissipation comprise one of the important goals of nanotechnology-based methods, including Quantum dot Cellular Automata (QCA), and so it is desirable to consider reversibility in the design of QCA circuits. In this research, a novel reversible Fredkin gate based on QCA is proposed, which is more efficient and less complex than the conventional Fredkin gate. Conservative reversible logic is parity preserving; hence, any permanent or transient fault can be caused a mismatch between the inputs and the outputs and can be concurrently detected if a reversible circuit is implemented with the conservative Fredkin gate. A single missing/additional cell defect is investigated in the proposed Fredkin gate and fault patterns are presented. To demonstrate the efficiency of the proposed design, some testable reversible sequential elements, such as D-latch, JK-latch, T-latch and SR-latch, are designed by using it. Our proposed concurrent testable designs greatly reduce the occupied area and maximise the circuit density in comparison with previously reported designs. The proposed designs are simulated and verified using QCA Designer ver.2.0.3 and HDLQ.     

石墨烯场效应管的Verilog-A建模

在传统硅基器件日益趋近物理极限的背景下,石墨烯场效应管作为一种新型纳米器件受到了广泛关注。以漂移-扩散传输理论为基础,得到了石墨烯场效应管的漏电流解析表达式,并以此建立了适合电路设计的石墨烯场效应管Verilog-A模型。利用该模型对栅长为10μm、沟道宽度为5μm的石墨烯场效应管进行HSPICE仿真,仿真结果与实验所测数据相符。在此基础上,给出了基于石墨烯场效应管的共源放大电路、共漏放大电路和共栅放大电路三种基本电路组态的仿真结果,表明石墨烯场效应管应用于模拟及RF电路具有广阔的前景。     

连续输出全集成开关电容带隙基准电路

本文提出了一种新型的开关电容带隙基准电路。电路采用双通道开关电容求和电路,能够连续输出基准电压,同时采用输出缓冲电路降低电压过冲,无需片外滤波电容。本设计采用NEC 0.35μm CMOS工艺,使用Hspice仿真软件对电路进行仿真。仿真结果表明:在典型参数情况下,该电路能够连续输出过冲为50μV的基准电压,在-20℃～80℃范围内,其输出电压的温度系数为15.4ppm/℃。     

基于细胞神经网络的从阴影恢复形状的新方法

细胞神经网络(CNN)是一种实时处理信号的大规模非线性模拟电路,它的连续时间特点以及局部互连特点使其可以进行并行计算,并且非常适用于超大规模集成电路(VLSI)的实现.本文针对从阴影恢复形状(SFS)问题,提出了一种基于硬件退火CNN的能量函数优化方法,并对该方法进行了详细分析,给出了实例的仿真结果,验证了该方法的有效性.该方法为并行处理算法,具有运算量小、易于大规模VLSI集成实现,且能够克服局部极小等优点,可以使SFS问题得到实时的处理.     

基于共振隧穿二极管的集成电路研究

RTD基集成电路所具有的超高速、低功耗和自锁存的特性,使其在数字电路、混合信号电路以及光电子系统中有着重要的应用。首先对RTD与化合物半导体HEMT,HBT以及硅CMOS器件的集成工艺进行了介绍。在MOBILE电路及其改进和延伸的基础上,对高速ADC／DAC电路和低功耗的存储器电路进行了具体的分析。最后对RTD基电路面临的主要问题和挑战进行了讨论,提出基于硅基RTD与线性阈值门（LTG）逻辑相结合是未来纳米级超大规模集成电路的最佳发展方向。     

An energy-efficient spike encoding circuit for speech edge detection

In speech processing applications, the instantaneous bandwidth of speech can be used to adaptively control the performance of an audio sensor’s analog front end. Extracting the instantaneous bandwidth of speech depends on the detection of speech edges in the time–frequency plane. In this paper, we propose a spike encoding circuit for real-time and low-power speech edge detection. The circuit can directly encode the signal’s envelope information—an important feature to identify the speech edge—by temporal spike density without additional envelope extraction. Furthermore, the spike encoding circuit automatically adapts its resolution to the amplitude of the input signal, which improves the encoding resolution for small signal without increasing the power consumption. We use the nonlinear dynamical approach to design this circuit and analyze its stability. We also develop a linearized model for this circuit to provide the design intuition and to explain its adaptive resolution. Fabricated in 0.5-μm CMOS process, the spike encoding circuit consumes 0.3-μW power and the experimental results are presented.     

A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET

Double-gate (DG) transistor has emerged as one of the most promising devices for nano-scale circuit design. In this paper, we propose a high-performance and robust sense-amplifier design using independent gate control in symmetric and asymmetric DG devices for sub-50-nm technologies. The proposed sense amplifier has better performance (30%-35% less sensing delay) and robustness (60%-80% less minimum input bit-differential for correct operation considering 10% worst case silicon thickness mismatch) compared to the connected gate design. Hence, the proposed design successfully demonstrates the benefit of using independent gate control in DG devices for efficient circuit design in sub-50-nm regime.     

Hardware-efficient common-feedback Markov-random-field probabilistic-based noise-tolerant VLSI circuits

As the size of CMOS devices is scaled down to lower the power consumption and space occupied on the chip to the nano-scale, unfortunately, noise is not reduced accordingly. As a result, interference due to noise can significantly affect circuit performance and operation. Since noises are random and dynamic in nature, probabilistic noise-tolerant approaches are more desirable to handle this problem. However, trade-offs between hardware complexity and noise-tolerance are severe design challenges in the probabilistic-based noise-tolerant approaches. In this paper, we proposed a cost-effective common-feedback probabilistic-based noise-tolerant VLSI circuit based on Markov random field (MRF) theory. We proposed a common latch feedback method to lower the hardware complexity. To further enhance the noise-tolerant ability, the common latch feedback technique is combined with Schmitt trigger. To demonstrate the proof-of-concept design, a 16-bit carry-lookahead adder was implemented in the TSMC 90 nm CMOS process technology. As compared with the state-of-art master-and-slave MRF design, the experimental results show that not only the transistor count can be saved by 20%, the noise-tolerant performance can also be enhanced from 18.1 dB to 24.2 dB in the proposed common feedback MRF design.