基于皮尔斯振荡器的8MHz晶振电路设计

分析了石英晶体的等效模型和性能参数,设计了一款基于皮尔斯振荡器的8 MHz晶振电路,主要包括皮尔斯电路、使能控制及隔离电路、偏置电路和整形及电平移位电路.针对数字电路时钟为方波且数字电压域与模拟电压域不同的问题,设计了一个整形及电平移位电路,将晶体振荡器输出的正弦波整形成方波,且电路实现了双电压域工作.基于华宏0.11...     

基于EWB的数字钟设计与实现

Electronics Workbench(EWB)EDA软件是目前各种电路仿真软件中最理想的一种软件,该软件具有完整的混合模拟与数字信号模拟的功能。介绍了一种基于EWB软件设计电子钟的方法,系统由石英晶体振荡器、分频器、计数器、译码电路、LED显示电路、校时电路、整点报时电路组成。     

用于晶体振荡器温度补偿的次方电压产生方法

为了获得更高精度的时钟源,需要对晶体振荡器进行温度补偿以便减小频率随温度的变化。对比晶体振荡器不同的温度补偿方式,模拟温度补偿具有较高的性能,而模拟温度补偿电路的主要模块就是获取与温度成次方关系的补偿电压。文中采用了一种模拟乘法器的方法来获得与温度成不同指数关系的电压,在全差分放大器的输入端接入4个MOS管,利用其工作于线性区时的电流电压关系并结合全差分放大器来实现两个模拟量之间的相乘,进而获得与温度成1次方、2次方、3次方、4次方和5次方关系的补偿电压。获得的这些电压通过加和电路叠加后即可用于晶体振荡器的高阶温度补偿。通过仿真,得到全差分放大器的差模增益为78.6 dB,乘法器可以实现两个信号的相乘,且应用该方法进行补偿的晶体振荡器的频率偏移为±2 ppm。     

用于实时时钟的32.768kHz晶振电路分析与设计

提出了一种采用晶振和比较器的结构实现实时时钟RTC的32.768kHz集成晶体振荡电路的方法.设计基于UMC 0.18um工艺参数,并使用Hspice对所设计的电路进行仿真,通过分析其各项性能指标,验证了电路具有起振时间短,波形稳定,功耗低,所占芯片面积小的特点.     

A system-oriented 5 V NMOS LSI circuit for data acquisition and front-end digital control

A 5 V n-channel enhancement/depletion circuit performs 8 bit data acquisition with a 5 V analog input range. It provides front-end digital control with adjustable set point and hysteresis. A simple constant-slope converter was developed, which is calibrated for a given application by tuning the built-in clock oscillator and adjusting the only reference, analog ground. For temperature compensation, the oscillator and the current source track with temperature. Digital subtraction was implemented with a three-decade synchronous BCD up/down counter, which produces positive or negative readings by a reversal of the counter. The circuit has a multiplexed three-digit TTL compatible BCD output. The chip size is 13 mm/SUP 2/ and it consumes 150 mW.     

IR2132驱动器及其在三相逆变器中的应用

提出了IR2132驱动器在三相逆变器中的应用。采用数字信号处理器对电源系统进行全数字控制,通过改变PWM波形的脉冲宽度和调制周期可以达到调压和变频的目的。采用功率MOSFET和IGBT专用驱动芯片IR2132驱动三相桥式逆变电路。介绍了IR2132驱动电路的特点、内部结构、工作原理和基于IR2132构成的三相逆变电路结构,并提出了一种新型实用的预制相位PWM数字控制方案,取代了传统的模拟驱动电路和模块化桥臂电路设计,降低了开发成本,并融合了多元化的保护功能使逆变电源系统的驱动电路变得简单可靠。     

基于51单片机的简易电子钟设计

本文以STC89C51单片机为核心控制器,在它的引脚上接上其他电子元器件以及外围电路,设计了一个电子时钟.这个电子钟显示时间是用数码管实现的,本设计选用的数码管是6位数码管,以分别实现对"时"、"分"、"秒"进行数字显示,它们之间的间隔用数码管上的小数点来分割,采用74HC573锁存器来驱动六位8段数码管,并利用石英晶振产生时钟脉冲,并利用单片机内部的定时器计数,通过程序和外围电路控制数码管进行动态显示.本文提供一种简单且廉价的设计方案,广大的电子科技爱好者可以参考并自行制作.     

基于FPGA的平板显示器件驱动电路的设计

介绍了一种基于FPGA的平板显示器件驱动电路的设计方法。在FPGA内部设计了数字GAMMA校正、时基校正、时钟发生器、锁相环、I2C控制等模块,替代了各个专用集成芯片的功能,用数字技术取代传统模拟技术实现电路各模块,简化了电路;能够完成平板显示器件显示时序及控制方面的要求且控制灵活;能驱动大部分的平板显示器件,通用性好;设计了丰富的扩展信号接口,FPGA外挂SDRAM可应用于更大规模的平板显示驱动,可移植性强。采用高分辨率液晶投影显示屏LCX029CPT来验证所设计的驱动电路,通过电路实现,显示出质量很好的图像。     

基于频差倍增法的频率标准装置建模与分析

在航天测控及广电电力领域,为了保证时间和频率统一,需要对时统的铷钟及髙稳晶振等设备进行高精度频率测量。采用了一种以铯原子频率标准为参考,基于频差倍增法构建的频率标准装置,根据频差倍增法测量原理,推导了测量铷钟及髙稳晶振过程中数据影响因素的数学模型,在此基础上,通过对测量影响因素的分析及实测数据计算,对装置的测量不确定度进行了分析和评定。评定结果表明,标准装置符合铷钟及髙稳晶振的检定规程要求,能够确保测量结果准确可靠。     

基于DS P的PTCR多功能参数测试仪

利用数字信号处理器控制外围接口电路，对多路热敏电阻测试电路执行依次通/断电操作，循环执行，以测试其老化性能，循环次数由用户设定。在每次测试第一次通电过程中，控制动作时间比较电路启动，同时数字信号处理芯片自动记录每一路的热敏电阻的动作时间数据，并进行处理。该系统可以同时测试30只热敏元件。     

An accurate digital phase measurement scheme

An accurate digital phase measurement scheme based on automatic accumulation principle is proposed. It uses a signal-dependent clock frequency and thus it measures the phase accurately at any frequency. Moreover, it is economical, since it eliminates the need for a highly stable crystal oscillator.     

A method of measuring the integrated arc duration using a digital counter

This letter describes a simple but accurate method of measuring the integrated or the average duration of a series of arcs by a proper voltage discriminating gate circuit which was used in conjunction with a clock oscillator and a digital counter.     

Ku波段直接频率综合器设计

为了实现Ku波段直接频率综合器,该文叙述了用数字和模拟直接合成的方法产生一、二本振、各种相参时钟及发射激励信号的设计方法和关键技术措施;并给出了达到的主要技术指标、测试结果和测量方法。实验结果与理论模拟基本一致,验证了方案的可行性。     

Clock and data recovery IC for 40-Gb/s fiber-optic receiver

The integrated clock and data recovery (CDR) circuit is a key element for broad-band optical communication systems at 40 Gb/s. We report a 40-Gb/s CDR fabricated in indium-phosphide heterojunction bipolar transistor (InP HBT) technology using a robust architecture of a phase-locked loop (PLL) with a digital early-late phase detector. The faster InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This, in turn, reduces the circuit complexity (transistor count) and the voltage-controlled oscillator (VCO) requirements. The IC includes an on-chip LC VCO, on-chip clock dividers to drive an external demultiplexer, and low-frequency PLL control loop and on-chip limiting amplifier buffers for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed-signal IC operating at the clock rate of 40 GHz. We also describe the chip architecture and measurement results.     

A 30-MHz hybrid analog/digital clock recovery circuit in 2-μmCMOS

A high-speed hybrid clock recovery circuit composed of an analog phase-locked loop (PLL) and a digital PLL (DPLL) for disk drive applications is described. The chip operates at a maximum data rate of 33 MHz from a single 5-V power supply and achieves fast acquisition, a decode window of 95% of full window width, effective sampling jitter of 100-ps rms, and an effective input sampling rate of 1 GHz. The ring oscillator in the analog PLL shows a 62 p.p.m./°C temperature coefficient (TC) and 4.5%/V supply sensitivity of free-running frequency. The total power dissipation is about 600 mW, and the active area is 30000 mil² in a 2-μm single-poly double-metal n-well CMOS process     

铷钟扩捕方法研究

铷钟的捕获带和其能否锁定密切相关,它通常比较小。对原子钟扩捕问题进行了研究,设计了主要由二次谐波幅度检测电路和由单片机同DA构成的扫描电路等组成的扩捕电路。工作时扫描电路输出三角波扫描信号,带动本振的频率扫动同时检测二次谐波的幅度,当幅值超过设定时,说明本振的频率已进入铷钟以前的捕获带,停止扫描,铷钟靠环路的作用便能锁定。以铷钟为对象进行了实验研究,实验结果是当把本振的频率调偏到捕获带以外时,不用扩捕电路环路没法锁定而使用扩捕电路后环路正常锁定,实验结果和理论分析一致。     

基于EWB的可编程调频微型电动机三相方波变流电源设计

随着现代电力电子装置,电气设备的快速发展,使得驱动电源得到进一步的发展,本文设计了一种转换效率、对称性以及稳定度等特性都比较好的数字式三相方波变流电源。所设计电源将石英晶体谐振器作为产生高频的方波信号的高频振荡器,然后用可编程的思想进行分频,再环形分配,处理成所需要的频率数值,最后通过运算放大器以满足输出电压,输出功率的要求,并且同模拟振荡式相比,它的频率稳定度要高很多。根据设计的三相方波变流电源的模型在电子工作平台EWB中进行搭建,对数字式三相方波变流电源的波形、输出电压、输出电流等进行仿真研究,通过对仿真结果分析可以验证其设计方案的准确性和可行性,这为以后搭建三相方波变流电源的硬件电路提供了一定的理论依据。     

基于数字PID增量控制的恒温晶体振荡器

针对晶体时钟振荡器输出频率易受外界温度变化影响的特点,设计了以MSP430F4618单片机为控制核心的恒温晶体振荡器.将高精度负温度系数热敏电阻作为传感器对晶体温度进行采样,并采用精密放大器IAN330芯片对晶体温度变化差值信号进行转换并输出至控制核心.输出的信号经12位A/D转换后进行数字PID增量控制运算得到控制量增量,再通过12位D/A转换输出至DRV593芯片驱动半导体制冷片(TEC)对晶体温度进行控制,并循环该过程使晶体振荡器的工作温度保持稳定.     

An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time

An all-digital phase-locked loop (PLL) circuit in which resolution in the phase detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time is presented. The pulse delay circuit is connected in a ring shape with 32 inverters (2/sup 5/ inverters). With the inverter gate-delay time as the time base, the pulse phase difference is detected simultaneously with the generation of the output clock. In this system, the phase detector and oscillator share a single ring-delay-line (RDL). This means the resolution is the same at all times, making a high-speed response possible. In a prototype integrated circuit (IC) using 0.65-/spl mu/m CMOS, the generation of a frequency multiplication clock was achieved with four reference clocks, and that of a phase-locked clock with seven reference clocks, for a high-speed response. The cell size was 1.08 /spl times/ 1.08 mm/sup 2/, and the output clock frequency had a wide range of 50 kHz/spl sim/60 MHz. The multiplication range of the clock frequency was also a very wide 4/spl sim/1022, and a high level of precision was achieved with a clock jitter standard deviation of 234 ps. This digital PLL can withstand a broad range of operating environments, from -30/spl deg/C/spl sim/140/spl deg/C, and is suitable for making a programmable clock generator on a chip.     

Digital multiphase clock/pattern generator

In telecommunications systems, the commonly used method to generate clocks is based on phase-locked loop or delay-locked loop related frequency synthesis. In this paper, we address a method of digital multiphase clock/pattern generation (MPCG) to generate a system clock or pulse pattern vector when a multiphase clock is available. The advantages of the multiphase clock method are: (a) the design method is digital; (b) the working frequency range is very wide; and (c) the sensitivity to noise is less than analog methods. Different approaches to implement the basic blocks in MPCG are described. A design example implemented in BiCMOS uses eight clock phases at 622 MHz obtained by dividing a 5-GHz clock to generate a clock at 622 MHz×32/53=376 MHz. By such a method, we can generate a pulse pattern vector as well. The maximum time resolution is equal to half of the phase difference. A low power solution is achieved without loss of circuit speed