应用于OFDM系统中的高速FFT处理器设计

针对无线城域网中工作在2GHz~11GHz频带的IEEE802.16a标准,在实现其OFDM系统时提出一种高速而且经济的FFT处理器设计方案。设计中采用了Radix-4的频率抽取算法和并行的蝶型计算单元结构,而且将旋转因子预先存储在ROM中以提高处理器运行的速度。设计方案采用了单个蝶型运算单元以达到控制FFT处理器规模的目的。数据的输入与输出都共用一个存储器,这进一步节约了硬件资源损耗。     

一种适用于DVB-T系统的新型FFT处理器设计

针对地面数字视频广播(DVB-T)系统中高速FFT处理器的设计要求,提出了一种新的基16/8混合基算法及其实现结构。采用单个基16/8复用的蝶形运算单元顺序处理,并通过减少乘法器数目,有效降低了硬件消耗;运算单元内部采用“基4+基4/2”级联流水线方式,大大加快了运算速度;此外,应用对称乒乓RAM结构提高了蝶算单元的连续运算能力;并且使用改进的块浮点防溢出机制,以保证运算精度。仿真和实现结果表明该设计具有良好的性能,完全满足实际应用要求。     

VLSI architecture for low latency radix-4 CORDIC

The CORDIC algorithm, originally proposed using nonredundant radix-2 arithmetic, has been refined in terms of throughput and latency with the introduction of redundant arithmetic and higher radix techniques. In this paper, we propose a pipelined architecture using signed digit arithmetic for the VLSI efficient implementation of rotational radix-4 CORDIC algorithm, eliminating z path completely. A detailed comparison of the proposed architecture with the available radix-2 architectures shows the latency and hardware improvement. The proposed architecture achieves latency improvement over the previously proposed radix-4 architecture with a relatively small hardware overhead. The proposed architecture for 16-bit precision was implemented using VHDL and extensive simulations have been performed to validate the results. The functionally simulated net list has been synthesized for 16-bit precision with 90 nm CMOS technology library and the area-time measures are provided. This architecture was also implemented using Xilinx ISE9.1 software and a Virtex device.     

基于FPGA的高速数字脉冲压缩

研究一种基于现场可编程门阵列实现的高速脉冲压缩处理的硬件结构。设计通用的蝶形处理单元,使其在脉冲压缩处理的3个阶段都能使用,实现了硬件的共享,提高了硬件资源的利用效率。通过可使用原位运算的并行存储器结构,使得每个时钟周期均可完成一次蝶形运算,极大地提高了处理速度。采用块浮点处理单元,兼顾定点的高速率和浮点的高精度。经过实践验证,时钟在100 MHz时完成4 096点的脉冲压缩的时间为140 μs。     

Dual-mode floating-point adder architectures

Most modern microprocessors provide multiple identical functional units to increase performance. This paper presents dual-mode floating-point adder architectures that support one higher precision addition and two parallel lower precision additions. A double precision floating-point adder implemented with the improved single-path algorithm is modified to design a dual-mode double precision floating-point adder that supports both one double precision addition and two parallel single precision additions. A similar technique is used to design a dual-mode quadruple precision floating-point adder that implements the two-path algorithm. The dual-mode quadruple precision floating-point adder supports one quadruple precision and two parallel double precision additions. To estimate area and worst-case delay, double, quadruple, dual-mode double, and dual-mode quadruple precision floating-point adders are implemented in VHDL using the improved single-path and the two-path floating-point addition algorithms. The correctness of all the designs is tested and verified through extensive simulation. Synthesis results show that dual-mode double and dual-mode quadruple precision adders designed with the improved single-path algorithm require roughly 26% more area and 10% more delay than double and quadruple precision adders designed with the same algorithm. Synthesis results obtained for adders designed with the two-path algorithm show that dual-mode double and dual-mode quadruple precision adders requires 33% and 35% more area and 13% and 18% more delay than double and quadruple precision adders, respectively.     

应用于时频分析的低功耗短时傅里叶变换处理器

提出了一个应用于时频分析的短时傅里叶变换处理器.为了克服已有的离散短时傅里叶变换算法和结构的缺点,给出了一种基于快速傅里叶变换阵列的新结构.根据实际需要提出了一种新的高频域分辨率的SDF(Single-path Delay Feedback)结构FFT单元,和传统的SDF结构FFT单元相比,反馈FIFO的深度和蝶形单元的数量都有所降低.再加上开发窗函数的对称性和适当合并硬件资源,与原始设计相比处理器的功耗降低了20%.使用中芯国际0.18微米工艺实现之后,系统工作时钟可以达到200MHz,即该处理器可以满足同样频率的采样信号的实时时频分析需求.     

2-D Systolic Array architecture of CBNS based Discrete Hilbert Transform Processor

This paper proposes an optimized design of Discrete Hilbert Transform (DHT) processor using Complex Binary Number System (CBNS). The conventional implementation of DHT based on the “divide and conquer” approach involves two separate computational units for the real and imaginary parts, which requires a large silicon area and increases the path delay. In contrast, incorporation of CBNS in transformation techniques facilitates complex-valued signal processing through a single computational unit.The CBNS-DHT processor has been designed using the standard computational method of Fast Fourier Transform (FFT). The 2-D Systolic Array architecture along with a novel processing element has been proposed for CBNS based Complex-valued FFT (CFFT) and Inverse FFT (CIFFT) computations. The architecture of CBNS-CFFT/CIFFT has been extended to develop the CBNS-DHT processor on the Zynq-7000 family, XC7Z020-CLG484 FPGA platform. A comparative performance analysis of CBNS-DHT and Normal Binary Number System (NBNS)-DHT highlights the efficiency of CBNS-DHT in terms of VLSI parameters — silicon area, path-delay and memory utilization. CBNS-CFFT shows significant improvement in path delay and area consumption as compared to NBNS-CFFT for both Twiddle Factors and FFT size, which proves that CBNS based CFFT and DHT processor design is more efficient in terms of speed and area requirements.     

Implementing fast Fourier transforms using the Am29500 family

The paper discusses the implementation of fast Fourier transform (FFT) algorithms using members of the Am29500 family of microprocessors and peripherals. First the suitability of the Am29500 family for signal processing applications is discussed. The architectural requirements of FFT processors are then outlined. A parallel processing architecture using pipelining is developed and the microprogramming of the system is described. Timing and implementation details, together with some practical test results, are given. The paper concentrates mainly on radix-2 decimation-in-time (DIT) FFT computations, but the architecture described can be applied to variable-radix processors running DIT or DIF (decimation-in-frequency) algorithms.     

Gather/scatter hardware support for accelerating Fast Fourier Transform

As we enter the multi-core era, seeking methods to boost the performance of single-threaded applications remains critical. Achieving gains in processor performance by increasing the operating frequency has begun to meet more obstacles. However, significant performance improvements can be achieved by extending the capability of the processor with the addition of hardware support, which makes much more effective use of the available transistors. This paper presents a novel hardware support called, DistTree, to speed up processor performance. The DistTree hardware automates gather and scatter operations for applications with complex but predictable memory access patterns like the Fast Fourier Transform (FFT). With this hardware support integrated with a modern microprocessor (the Alpha architecture in our experiments), the FFT performance can reap a more than twofold increase when compared against the FFTW library, a state-of-the-art implementation. The DistTree hardware support enables the processor to spend the majority of processor cycles on executing the computations of an algorithm by reducing both the arithmetic and address computation overhead. Therefore, the performance of many single-threaded applications can be significantly increased.     

FFT处理器无冲突地址生成方法

本文提出了一种新的无冲突地址生成方法，使蝶式运算单元在一个周期内能够同时读取两个操作数。由于取消了地址奇偶判别电路，简化了存储体控制逻辑，同 时也加快了输入／输出地址生成，该方法还同样适用于基－４ＦＦＴ处理器。     

Radix-8 full adder in QCA with single clock-zone carry propagation delay

We design a 3-bit adder or a radix-8 full adder (FA) in quantum-dot cellular automata (QCA), where the 3-bit carry propagation path can be accommodated in one clock-zone. To achieve this, we introduce group majority signals similar to group propagate and generate signals in parallel prefix computations, use them to reformulate the carry expressions of a previous radix-4 FA, and as such we could extend it to higher radix FAs. Applying the aforementioned new interpretation of carry expressions (via group majority signals) on 3-bit adders, results in that only a single clock cycle is required for 12-bit (vs. the previous 8-bit) carry propagation, across four radix-8 FAs. Based on the proposed radix-8 QCA-FA, we realized 8-, 16-, 32-, 64, and 128-bit QCA adders via QCADesigner. Comparison of these adders with the previous radix-4 experiment, showed 9–41% speed up, and 57–76% area saving, for 16–128-bit adders, respectively. On the other hand, compared to the best previous radix-2 design, for the same bit widths, we experienced 57–172% speed up, but at the cost of 138–4% area increase, except for the 64 and 128-bit cases, where we also experienced 19% and 41% area saving, respectively.     

An area efficient multi-mode quadruple precision floating point adder

Most of the scientific and engineering applications require accurate computations. Double precision floating point computations are not enough for many applications like climate modelling, computational physics, etc. Efficient design of quadruple precision floating point adder is needed for these applications. The proposed multi-mode quadruple precision floating point adder architecture supports four single precision operations in parallel, as well as two double precision operations in parallel and also supports one quadruple precision operation. Compared to existing Quadruple precision floating point adders and Dual mode Quadruple precision floating point adder, the proposed architecture can perform more computations with less area because of resource sharing among different precision operands. The proposed Multi-mode quadruple precision adder supports both normal and subnormal operations and also the exceptional case handling such as infinity, Not a Number (NaN) and zero cases. The proposed adder has been designed and implemented in both ASIC and FPGA. During ASIC implementation with 90 nm technology using the synopsis tool, the proposed Multi-mode quadruple precision floating point adder has a 38.57% smaller area compared to the existing quadruple precision floating point adder. Similarly, the proposed design reduces the area by 29.28% and 35.68% when implemented on Virtex 4 and Virtex 5 FPGAs respectively.     

基于CORDIC算法的高速基-4FFT处理器设计

针对目前数字信号处理中对高速傅里叶变换(FFT)的要求,进行了FFT算法研究,采用基-4算法来实现FFT处理器;设计了对称乒乓RAM结构,提高了FFT处理器的连续运算能力和运算速度;采用CORDIC算法代替复数乘法器,用移位加法实现了复数乘法运算,减小了系统资源占用,提高了系统速度,设计了防溢出控制结构,在不增加系统延时的基础上,提高了运算精度;采用AL-TERA公司FPGA进行了验证,仿真结果表明该FFT处理器最大工作频率可达168.86 MHz,能满足高速实时处理的要求。     

Efficient 3D stencil computations using CUDA

We present an efficient implementation of 7-point and 27-point stencils on high-end Nvidia GPUs. A new method of reading the data from the global memory to the shared memory of thread blocks is developed. The method avoids conditional statements and requires only two coalesced instructions to load the tile data with the halo (ghost zone). Additional optimizations include storing only one XY tile of data at a time in the shared memory to lower shared memory requirements, common subexpression elimination to reduce the number of instructions, and software prefetching to overlap arithmetic and memory instructions, and enhance latency hiding. The efficiency of our implementation is analyzed using a simple stencil memory footprint model that takes into account the actual halo overhead due to the minimum memory transaction size on the GPUs. Through experiments we demonstrate that in our implementation the memory overhead due to the halos is largely eliminated by good reuse of the halo data in the memory caches, and that our method of reading the data is close to optimal in terms of memory bandwidth usage. Detailed performance analysis for single precision stencil computations, and performance results for single and double precision arithmetic on two Tesla cards are presented. Our stencil implementations are more efficient than any other implementation described in the literature to date. On Tesla C2050 with single and double precision arithmetic our 7-point stencil achieves an average throughput of 12.3 and 6.5 Gpts/s, respectively (98 GFLOP/s and 52 GFLOP/s, respectively). The symmetric 27-point stencil sustains a throughput of 10.9 and 5.8 Gpts/s, respectively.     

基于FPGA的片内并行机网络模型优化策略分析

针对基-2 FFT 处理算法,采用分块存储思想,将存储器、处理机数据交换网络模型进行优化。优化后的网络模型数据通路数仅为20,降低为原来的4%以下,且不随 FFT 计算点数增多而增加。整个设计在 Virtex 系统芯片 XCV800上实现。     

Ultrahigh-performance FFTs for the CRAY-2 and CRAY Y-MP supercomputers

In this paper a set of techniques for improving the performance of the fast Fourier transform (FFT) algorithm on modern vector-oriented supercomputers is presented. Single-processor FFT implementations based on these techniques are developed for the CRAY-2 and the CRAY Y-MP, and it is shown that they achieve higher performance than previously measured on these machines. The techniques include (1) using gather/scatter operations to maintain optimum length vectors throughout all stages of small-to medium-sized FFTs, (2) using efficient radix-8 and radix-16 inner loops, which allow a large number of vector loads/stores to be overlapped, and (3) prefetching twiddle factors as vectors so that on the CRAY-2 they can later be fetched from local memory in parallel with common memory accesses. Performance results for Fortran implementations using these techniques demonstrate that they are faster than Cray's library FFT routine CFFT2. The actual speedups obtained, which depend on the size of the FFT being computed and the supercomputer being used, range from about 5 to over 300%.     

Architectural design and FPGA implementation of radix-4 CORDIC processor

A new scaled radix-4 CORDIC architecture that incorporates pipelining and parallelism is presented. The latency of the architecture is n/2 clock cycles and throughput rate is one valid result per n/2 clocks for n bit precision. A 16 bit radix-4 CORDIC architecture is implemented on the available FPGA platform. The corresponding latency of the architecture is eight clock cycles and throughput rate is one valid result per eight clock cycles. The entire scaled architecture operates at 56.96 MHz of clock rate with a power consumption of 380 mW. The speed can be enhanced with the upgraded version of FPGA device. A speed-area optimized processor is obtained through this architecture and is suitable for real time applications.     

Design and analysis of high-speed 8-bit ALU using 18 nm FinFET technology

All modern computational devices consist of ALU. With increase in complexity of software and the consistent shift of software towards parallelism, high speed processors with hardware support for time consuming operations such as multiplication would benefit. Smaller, compact devices such as IoT devices need to run software such as security software and be able to offload computation cost from the cloud. In this paper, a high speed 8-bit ALU using 18 nm FinFET technology is proposed. The arithmetic and logical unit consists of fast compute units such as Kogge Stone fast adder and Dadda multiplier along with basic logic gates. In this paper, an ALU with each compute unit optimized for speed is proposed, while responsibly consuming area. Dadda multiplier is of 8 × 8 architecture as opposed to conventional approach of 4 × 4 making it a true 8-bit ALU. Simulation and analysis is done using Cadence Virtuoso in Analog Design Environment. The transistor count of proposed design is 5298, the power consumption is 219 µW and maximum delay is 166.8 ps. The design is also expected to consume a maximum of one clock cycle for any computation.

     

Area and delay efficient GDI based accuracy configurable adder design

Adders are one of the basic fundamental critical arithmetic circuits in a system and their performances affect the overall performance of the system. Traditional n-bit adders provide precise results, whereas the lower bound of their critical path delay of n bit adder is Ὠ(log n). To achieve a minimum critical path delay lower than Ὠ(log n), many inaccurate adders have been proposed. These inaccurate adders decrease the overall critical path delay and improve the speed of computation by sacrificing the accuracy or predicting the computation results. In this work, a fast reconfigurable approximate ripple carry adder has been proposed using GDI (Gate Diffusion Logic) passing cell. Here, GDI cell acts as a reconfigurable cell to be either connected with the previous carry value or approximated value in an adder chain. This adder has greater advantage and it can be configured as an accurate or inaccurate adder by selecting working mode in GDI cell. The implementation results show that, in the approximate working mode, the proposed 64-bit adder provides up to 23%, 34% and 95% reductions in area, power and delay, respectively compared to those of the existing adder.     

低功耗并行的二维离散小波变换的VLSI结构

提出了一种基于提升算法的低功耗并行的二维离散小波变换的VLSI结构。提出结构的同时进行行和列方向的处理,不需要额外的缓存来存储用于列变换的中间变换系数。通过分时复用关键的运算功能模块,该结构同时可以对两行数据进行处理,硬件的利用率达到100%。边界对称扩展通过嵌入式电路实现,大大降低了需要的片上存储器的数量以及对片外存储器的访问,有效地降低了系统的功耗。