A low power-delay-product and robust Isolated-DICE based SEU-tolerant latch circuit design

Soft-error interference is a crucial design challenge in the advanced CMOS VLSI circuit designs. In this paper, we proposed a SEU Isolating DICE latch (Iso-DICE) design by combing the new proposed soft-error isolating technique and the inter-latching technique used in the DICE (Calin et al., 1996 [1]) design. To further enhance SEU-tolerance of DICE design, we keep the storage node pairs having the ability to recover the SEU fault occurring in each other pair but also avoid the storage node to be affected by each other. To mitigate the interference effect between dual storage node pairs, we use the isolation mechanism to resist high energy particle strikes instead of the original interlocking design method. Through isolating the output nodes and the internal circuit nodes, the Iso-DICE latch can possess more superior SEU-tolerance as compared with the DICE design (Calin et al., 1996 [1]). As compared with the FERST design (Fazeli, 2009 [2]) which performs with the same superior SEU-tolerance, the proposed Iso-DICE latch consumes 50% less power with only 45% of power delay product in TSMC 90 nm CMOS technology. Under 22 nm PTM model, the proposed Iso-DICE latch can also perform with 11% power delay product saving as compared with the FERST design (Fazeli, 2009 [2]) that performs with the same superior SEU-tolerance.     

Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology

As a consequence of technology scaling down, gate capacitances and stored charge in sensitive nodes are decreasing rapidly, which makes CMOS circuits more vulnerable to radiation induced soft errors. In this paper, a low cost and highly reliable radiation hardened latch is proposed using 65 nm CMOS commercial technology. The proposed latch can fully tolerate the single event upset (SEU) when particles strike on any one of its single node. Furthermore, it can efficiently mask the input single event transient (SET). A set of HSPICE post-layout simulations are done to evaluate the proposed latch circuit and previous latch circuits designed in the literatures, and the comparison results among the latches of type 4 show that the proposed latch reduces at least 39% power consumption and 67.6% power delay product. Moreover, the proposed latch has a second lowest area overhead and a comparable ability of the single event multiple upsets (SEMUs) tolerance among the latches of type 4. Finally, the impacts of process, supply voltage and temperature variations on our proposed latch and previous latches are investigated.     

Single event double node upset tolerance in MOS/spintronic sequential and combinational logic circuits

Spin-transfer torque random access memory (STT-RAM) is an emerging storage technology that is considered widely thanks to its attractive features such as low power consumption, nonvolatility, scalability and high density. STT-RAMs are comprised of a hybrid design of CMOS and spintronic units. Magnetic tunnel junction (MTJ) as the basic element of such hybrid technology is inherently robust against radiation induced faults. However, the peripheral CMOS component for sensing the resistance of the MTJs are prone to be affected by energetic particles. This paper proposes low power, nonvolatile and radiation hardened latch and lookup table circuits based on hybrid CMOS/MTJ technology for the next generation integrated circuit devices. Simulation results revealed that, the proposed circuits are fully robust against single event upsets (SEU) and also single event double node upsets (SEDU) that are of the main reliability challenging issues in current sub-nanometer CMOS technologies.     

An Efficient 5‐Input Exclusive‐OR Circuit Based on Carbon Nanotube FETs

The integration of digital circuits has a tight relation with the scaling down of silicon technology. The continuous scaling down of the feature size of CMOS devices enters the nanoscale, which results in such destructive effects as short channel effects. Consequently, efforts to replace silicon technology with efficient substitutes have been made. The carbon nanotube field‐effect transistor (CNTFET) is one of the most promising replacements for this purpose because of its essential characteristics. Various digital CNTFET‐based circuits, such as standard logic cells, have been designed and the results demonstrate improvements in the delay and energy consumption of these circuits. In this paper, a new CNTFET‐based 5‐input XOR gate based on a novel design method is proposed and simulated using the HSPICE tool based on the compact SPICE model for the CNTFET at the 32‐nm technology node. The proposed method leads to improvements in performance and device count compared to the conventional CMOS‐style design.     

一种新型的抗辐射加固锁存器

Due to aggressive technology scaling, radiation-induced soft errors have become a serious reliability concern in VLSI chip design. This paper presents a novel radiation hardened by design latch with high single-eventupset （SEU） immunity. The proposed latch can effectively mitigate SEU by internal dual interlocked scheme. The propagation delay, power dissipation and power delay product of the presented latch are evaluated by detailed SPICE simulations. Compared with previous SEU-hardening solutions such as TMR-Latch, the presented latch is more area efficient, delay and power efficient. Fault injection simulations also demonstrate the robustness of the presented latch even under high energy particle strikes.     

A novel radiation hardened by design latch

Due to aggressive technology scaling, radiation-induced soft errors have become a serious reliability concern in VLSI chip design. This paper presents a novel radiation hardened by design latch with high single-event-upset (SEU) immunity. The proposed latch can effectively mitigate SEU by internal dual interlocked scheme. The propagation delay, power dissipation and power delay product of the presented latch are evaluated by detailed SPICE simulations. Compared with previous SEU-hardening solutions such as TMR-Latch, the presented latch is more area efficient, delay and power efficient. Fault injection simulations also demonstrate the robustness of the presented latch even under high energy particle strikes.     

Graphene nanoribbon crossbar architecture for low power and dense circuit implementations

Crossbar array is a promising nanoscale architecture which can be used for logic circuit implementation. In this work, a graphene nanoribbon (GNR) based crossbar architecture is proposed. This design uses parallel GNRs as device channel and metal as gate, source and drain contacts. Schottky-barrier type graphene nanoribbon field-effect transistors (SB-GNRFETs) are formed at the cross points of the GNRs and the metallic gates. Benchmark circuits are implemented using the proposed crossbar, Si-CMOS and multi-gate Si-CMOS approaches to evaluate the performance of the crossbar architecture compared to the conventional CMOS logic design. The compact SPICE model of SB-GNRFET was used to simulate crossbar-based circuits. The CMOS circuits are also simulated using 16 nm technology parameters. Simulation results of benchmark circuits using SIS synthesis tool indicate that the GNR-based crossbar circuits outperform conventional CMOS circuits in low power applications. Area optimized cell libraries are implemented based on the asymmetric crossbar architecture. The area of the circuit can be more reduced using this architecture at the expense of higher delay. The crossbar cells can be combined with CMOS cells to exhibit better performance in terms of EDP.     

Radiation Hardened by Design Latches — A Review and SEU Fault Simulations

There are many Radiation Hardened by Design (RHBD) architectures presented in the literature to mitigate Single Event Upset (SEU) in a storage element, a latch. Nevertheless, the design of a SEU hardened latch is being continuously improved with respect to reliability, performance, power consumption and area overhead. SEU mitigating techniques by design focus on reducing criticality of sensitive nodes in a latch. Sensitive node(s) in a latch could be an active and/or a high impedance node(s). In this paper, we have classified previously presented SEU hardened by design latch architectures and reviewed SEU mechanisms in selected RHBD latch architectures on Complementary Metal Oxide Semiconductor (CMOS) technology models. Simulation studies using latest fault simulation model have been carried out. Simulation results have revealed some interesting observations described in this paper. Our findings, based on analyses, will provide valuable design inputs for futuristic RHBD latches with advanced technology nodes.     

Low cost and highly reliable hardened latch design for nanoscale CMOS technology

With technology node shrinking, the susceptibility of a single chip to soft errors increases. Hence, the critical charge (Qcrit) of circuit decreases and this decrease is expected to continue with further technology scaling. In this paper previous hardened latch circuits are analyzed and it is found that previous designs offer limited protection against soft error especially for soft error caused by high energy particles and not all the nodes are under soft error protection. Therefore, in this paper we propose a low cost hardened latch design in 45 nm CMOS technology with full protection for all internal nodes as well as output node against soft error. Moreover, the proposed hardened approach is technology independent. Compared to previous hardened latch designs, the proposed design reduces cost in terms of power delay product (PDP) 59% on average.     

Reliable ultra-low-voltage low-power probabilistic-based noise-tolerant latch design

In this paper, we proposed a reliable ultra-low-voltage low-power latch design based on the probabilistic-based Markov random field (MRF) theory ,  and  to greatly improve the ability of noise-tolerance. Through MRF mapping decomposition, we map the previous state and the current state compatible logic function of the latch into the MRF network separately. In this way, we can overcome the challenge of applying Markov random field theory to sequential noise-tolerant circuits. In order to further lower the hardware cost and circuit complexity of the chip, we apply the absorption law and H-tree logic combination techniques [4] to simplify the circuit complexity of the MRF noise-tolerant latch circuit. To preserve the noise tolerant capability of MRF latch, we utilize the cross-coupled latching mechanism in the output of MRF latch. Finally, we apply the proposed MRF latch design in a 16-bit carry-lookahead adder circuit. In TSMC 90 nm CMOS process, our proposed circuit can operate reliably under a lower supply voltage of 0.55 V with superior noise tolerance and consumes only 31 μW power, which is 59.2% lower as compared with the conventional CMOS latch design.     

PVT variations aware low leakage INDEP approach for nanoscale CMOS circuits

Increasing in device parameter variations is the critical issue in very deep sub-micron regime due to continue scaling of the transistor dimensions. The overall performance yield of the logic circuit is diminished by raising leakage current and variability issues in scaled devices. In this article; we have proposed an approach called INDEP, based on Boolean logic calculation for the input signals of the extra inserted transistors between the pull-up and pull-down network of the CMOS logic. INDEP approach is not only reduces the leakage current but also mitigates the variability issues with minimum susceptible delay paths. Various process, voltage and temperature (PVT) variations are analyzed at 22 nm BSIM4 bulk CMOS PTM technology node for chain of 5-inverters using HSPICE tool. Several guidelines are provided to design the variability aware CMOS circuits in nanoscale regime by considering the leakage current variation. INDEP approach works effectively in both active as well as standby state of the circuit and keeping the modal performance characteristics of the CMOS gate. The electrical simulation results show that our proposed INDEP approach is less susceptible to PVT variations as compared to conventional circuit. The Monte-Carlo simulation results confirm that average INDEP leakage current reduction is 62.31% at ±20% PVT variations under 3σ Gaussian distribution for chain of 5-inverters.     

INDEP approach for leakage reduction in nanoscale CMOS circuits

Complementary metal oxide semiconductor (CMOS) technology scaling for improving speed and functionality turns leakage power one of the major concerns for nanoscale circuits design. The minimization of leakage power is a rising challenge for the design of the existing and future nanoscale CMOS circuits. This paper presents a novel, input-dependent, transistor-level, low leakage and reliable INput DEPendent (INDEP) approach for nanoscale CMOS circuits. INDEP approach is based on Boolean logic calculations for the input signals of the extra inserted transistors within the logic circuit. The gate terminals of extra inserted transistors depend on the primary input combinations of the logic circuits. The appropriate selection of input gate voltages of INDEP transistors are reducing the leakage current efficiently along with rail to rail output voltage swing. The important characteristic of INDEP approach is that it works well in both active as well as standby modes of the circuits. This approach overcomes the limitations created by the prevalent current leakage reduction techniques. The simulation results indicate that INDEP approach mitigates 41.6% and 35% leakage power for 1-bit full adder and ISCAS-85 c17 benchmark circuit, respectively, at 32 nm bulk CMOS technology node.     

New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration

A predictive MOSFET model is critical for early circuit design research. To accurately predict the characteristics of nanoscale CMOS, emerging physical effects, such as process variations and correlations among model parameters, must be included. In this paper, a new generation of predictive technology model (PTM) is developed to accomplish this goal. Based on physical models and early-stage silicon data, the PTM of bulk CMOS is successfully generated for 130- to 32-nm technology nodes, with an L_eff of as low as 13 nm. The accuracy of PTM predictions is comprehensively verified: The error of I _on is below 10% for both n-channel MOS and p-channel MOS. By tuning only ten primary parameters, the PTM can be easily customized to cover a wide range of process uncertainties. Furthermore, the new PTM correctly captures process sensitivities in the nanometer regime, particularly the interactions among L_eff, V_th, mobility, and saturation velocity. A website has been established for the release of PTM: http://www.eas.asu.edu/~ptm     

High Performance Process Variations Aware Technique for Sub-threshold 8T-SRAM Cell

The demand of low power high density integrated circuits is increasing in modern battery operated portable systems. Sub-threshold region of MOS transistors is the most desirable region for energy efficient circuit design. The operating ultra-low power supply voltage is the key design constraint with accurate output performance in sub-threshold region. Degrading of the performance metrics in Static random access memory (SRAM) cell with process variation effects are of major concern in sub-threshold region. In this paper, a bootstrapped driver circuit and a bootstrapped driver dynamic body biasing technique is proposed to assist write operation which improves the write-ability of sub-threshold 8T-SRAM cell under process variations. The bootstrapped driver circuit minimizes the write delay of SRAM cell. The bootstrapped driver dynamic body bias increases the output voltage levels by boosting factor therefore increasing in switching threshold voltage of MOS devices during hold and read operation of SRAM latch. The increment in threshold voltage improves the static noise margin and minimizing the process variation effects. Monte-Carlo simulation results with 3 \(\sigma \) Gaussian distributions show the improvements in write delay by 11.25 %, read SNM by 12.20 % and write SNM by 12.57 % in 8T-SRAM cell under process variations at 32 nm bulk CMOS process technology node.     

An SEU resilient,SET filterable and cost effective latch in presence of PVT variations

This paper presents a single event upset (SEU) resilient, single event transient (SET) filterable and cost effective latch (referred to as RFEL) using 45 nm CMOS commercial technology. By means of triple mutual feedback CMOS structures, one of which is an input-split Schmitt trigger, and two of which are Muller C-elements, the internal nodes and output node of the latch are self-recoverable from single event upset regardless of the energy of a striking particle. The latch filters a much wider spectrum of single event transient on account of hysteresis property of the embedded input-split Schmitt trigger, and temporal redundancy in the grouped inputs of the Muller C-element at output stage. The latch performs with lower overheads regarding area, power, and delay than most of the single event upset and single event transient simultaneously tolerated latches as well. Simulation results show that the area-power-delay-pulse product of the latch is 65.58% saving on average, and Monte Carlo simulation results demonstrate the equivalent or even less sensitivity of the latch to process, and temperature variations, compared with the previous radiation hardened latches.     

Ultra low power DG FinFET based voltage controlled oscillator circuits

Voltage-controlled oscillator (VCO) significantly influences power and performance in many analog and digital applications. In this era of portable electronics, power consumption has emerged as an important design metric. Intended subthreshold circuits have proven their ability to satisfy this demand of ultra low-power consumption of a multitude of applications such as RFID, microsensors, etc. Double-gate Fin-FET technology is a promising alternative to the CMOS technology for the subthreshold circuits because of its enhanced gate control, improved performance, scalability, and robustness. Therefore, this paper investigates the viability of DG FinFET Current Starved Voltage Controlled Oscillator (CSVCO) in the subthreshold regime. The results indicate the superior performance of DG FinFET-based CSVCO in regard to speed, PDP, EDP, and variability as compared to CMOS-based CSVCO. Seven different CSVCO configurations, viz.. SG, IG, hybrid, hybrid reverse, pignsg, psgnig and MIGFET, designed using different configurations of DG FinFET, are simulated using 32 nm FinFET Predictive Technology Model (PTM) in HSPICE at 150 mv power supply. The proposed pignsg CSVCO shows better results in terms of frequency obtained versus power expended giving least PDP of 1.25E-16J and better immunity to supply voltage and process variations compared to all other CSVCO configurations.     

Ultra-low power FinFET-based domino circuits

Aggressive scaling of single-gate CMOS device face greater challenge in nanometre technology as sub-threshold and gate-oxide leakage currents increase exponentially with reduction of channel length. This paper discusses a double-gate FinFET (DGFET) technology which mitigates leakage current and higher ON state current when scaling is done beyond 32 nm. Here 8 and 16 input OR gate domino logic circuits are simulated on 32 nm FinFET Predictive technology model (PTM) on HSPICE. Simulation results of different 8 input OR gate domino logic circuits like Current-mirror footed domino (CMFD), High-speed clock-delayed (HSCD), Modified-HSCD (M-HSCD), Conditional evaluation domino logic (CEDL) and Conditional stacked keeper domino logic (CSK-DL), all operated in Short Gate (SG) and Low Power (LP) mode, shows tremendous reduction in average power consumption and delay. In this paper, domino logic-based circuit Ultra-Low Power Stack Dual-Phase Clock (ULPS-DPC) is proposed for both CMOS and FinFET (SG and LP modes). Proposed circuit shows maximum reduction in average power consumption of 84.04% when compared with CSK-DL circuit and maximum reduction in delay of 75.4% when compared with M-HSCD circuit at 10 MHz frequency when these circuits are simulated in SG mode.     

Low-Power Resonant Clocking Using Soft Error Robust Energy Recovery Flip-Flops

An energy recovery or resonant clocking scheme is very attractive for saving the clock power in nanoscale ASICs and systems-on-chips, which have increased functionality and die sizes. The technology scaling followed Moore’s law, that lowers node capacitance and supply voltage, making nanoscale integrated circuits more vulnerable to radiation-induced single event upsets (SEUs) or soft errors. In this work, we propose soft-error robust flip-flops (FFs) capable of working with a sinusoidal resonant clock to save the overall chip power. The proposed conditional-pass Quatro (CPQ) FF and true single phase clock energy recovery (TSPCER) FF are based on a unique soft error robust latch, which we refer to as a Quatro latch. The proposed C²-DICE FF is based on a dual interlocked cell (DICE) latch. In addition to the storage cell, each FF consists of a unique input-stage and a two-transistor, two-input output buffer. In each FF with a sinusoidal clock, the transfer unit passes the data to the Quatro and DICE latches. The latches store the data values at two storage nodes and two redundant nodes, the latter enabling recovery from a particle-induced transient with or without multiple-node charge sharing. Post-layout simulations in 65nm CMOS technology show that the FF exhibits as much as 82% lower power-delay product compared to recently reported soft error robust FFs. We implemented 1024 proposed FFs distributed in an H-tree clock network driven by a resonant clock-generator that generates a 1–5 GHz sinusoidal clock signal. The simulation results show a power reduction of 93% on the clock tree and total power saving of up to 74% as compared to the same implementation using the conventional square-wave clocking scheme and FFs.     

Novel radiation hardened latch design considering process, voltage and temperature variations for nanoscale CMOS technology

As CMOS technology is scaled down, the supply voltage and gate capacitance are reduced, which results in the reduction of charge storing capacity at each node and increase of the susceptibility to external noise in radiation environments. The traditional error tolerant circuit design methods provide very limited protection against the environment noise for storage cells such as latches and memories. In this paper, a novel hardened latch design is proposed and compared with the previous hardened latch designs using 32 nm technology node. Extensive simulation results using HSPICE are reported to show that the proposed hardened latch design achieves 15× improvement of critical charge (Qcrit) with comparable cost in terms of speed and power compared to the most up to date hardened latch design. Moreover, PVT variations have great impact on the reliability of hardened circuit. The proposed latch circuit is also evaluated with the presence of PVT variations and demonstrates higher robustness than other considered robust latch under severe PVT variation condition.     

一种基于三联锁结构的单粒子翻转加固锁存器

本文提出了一种基于三联锁结构的单粒子翻转加固锁存器。该锁存器使用保护门和反相器在其内部构建三路反馈,以此获得对发生在任一电路节点上的单粒子效应的自恢复能力,有效抑制由粒子轰击半导体引发的电荷沉积带来的影响。本文在详细分析已报道的三种抗辐射锁存器结构可靠性的基础上,针对其在单粒子效应作用下,或单粒子效应和耦合串扰噪声的共同作用下依然可能发生翻转的问题,指出本文提出的锁存器可通过内部的三联锁结构对上述问题进行有效的消除。所有结论均得到电路级单粒子效应注入仿真结果,以及基于经典串扰模型模拟串扰耦合和单粒子效应共同作用的仿真结果的支持和验证。