共查询到20条相似文献,搜索用时 15 毫秒
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在SoC设计的多种验证方法之中,基于FPGA的原型验证是一种较为贴近实际芯片的验证方法,可以大幅降低流片的风险,提高验证的效率和全面性.以一款基于OR1200的TD-LTE基带芯片为例,从原型验证的硬件平台设计、环境搭建以及验证的实现等方面阐述了基于FPGA原型验证的方法,并结合实际经验对原型验证中的一些问题提出了解决思路. 相似文献
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Timing channels are becoming a critical threat to hardware security. When exploited, secret information can be revealed by analyzing the execution time statistically. There are a variety of methods for detecting timing channels such as statistical analysis, testing and formal verification. However, existing methods cannot guarantee that the timing channels can be identified due to limited test coverage or high performance overhead. In this work, we introduce a novel model for evaluating timing variations of the hardware design. Furthermore, we propose a systematical solution that integrates time label enhanced tracking logic and formally verifies the timing invariant property of hardware designs in order to identify hardware timing channels. We demonstrate our solution on several hardware implementations, including arithmetic units, cryptographic cores and cache. The proof results show that our solution can detect hardware timing channels effectively. 相似文献
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安全芯片使得信息安全性大为增强,其应用正日益广泛地融入到国家安全和百姓生活中。但与此同时针对安全进行的攻击也层出不穷,这使得研究安全芯片的安全防护成为迫切需要。如今专门针对芯片的攻击技术已经不仅仅是解剖与反向提取,已发展到深层次的简单功耗分析SPA、差分功耗分析DPA、故障分析攻击等,其攻击手段还在继续进步。探析了这几种攻击方法的原理,并针对相应的攻击探讨一些可行的防护措施。 相似文献
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Hardware Trojans (HTs) can be implanted in security-weak parts of a chip with various means to steal the internal sensitive data or modify original functionality, which may lead to huge economic losses and great harm to society. Therefore, it is very important to analyze the specific HT threats existing in the whole life cycle of integrated circuits (ICs), and perform protection against hardware Trojans. In this paper, we elaborate an IC market model to illustrate the potential HT threats faced by the parties involved in the model. Then we categorize the recent research advances in the countermeasures against HT attacks. Finally, the challenges and prospects for HT defense are illuminated. 相似文献
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The PCB supply chain has become globally distributed such that PCBs are vulnerable to hardware Trojan attacks. Moreover, attacks on PCBs are possible even after a system is deployed. Various countermeasures have been proposed and efforts to develop board-level Trojan benchmarks are underway, but IC Trojan taxonomies do not capture important characteristics of PCB implants. This work surveys existing PCB countermeasures and examples of board-level Trojans to inform a new taxonomy suited for PCB Trojans. Our taxonomy reflects practically significant characteristics of board-level Trojans to guide development of board-level countermeasures and fair, comprehensive benchmark suites. 相似文献
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随着信息技术的发展,物联网进程逐渐加快,信息安全工作愈加重要。安全芯片可以应用在信息系统安全的各个方面,安全芯片具有更高的安全性和其他方案不可比拟的优点;国家密码管理局颁布的国密算法具有安全性和制度性两方面优势。因此,将国产算法与安全芯片技术相结合,采用国产算法的安全芯片必将在信息社会各领域中得到广泛应用,并具有巨大的市场前景。 相似文献
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在SoC开发过程中,基于FPGA的原型验证是一种有效的验证方法,它不仅能加快SoC的开发,降低SoC应用系统的开发成本,而且提高了流片的成功率.文章主要描述了基于FPGA的SoC原型验证的设计与实现,针对FPGA基验证中存在的问题进行了分析并提出了解决方案. 相似文献
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软硬件协同验证是系统芯片设计的重要组成部分。针对基于32 Bit CPU核的某控制系统芯片的具体要求,提出了一种系统芯片软硬件协同验证策略,构建了一个软硬件协同验证环境。该环境利用处理器内核模型支持内核指令集的特性运行功能测试程序,实现SoC软硬件的同步调试,并能够快速定位软硬件的仿真错误点,有效提高了仿真效率。该SoC软硬件协同验证环境完成了设计目的,并对其他系统芯片设计具有一定的参考价值。 相似文献
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针对SoC的功能验证需求,提出了一种基于32 bit CPU核的SoC功能验证平台.该平台集成了SoC功能验证流程,包括IP模块验证、软硬件协同验证、模数混合验证、验证程序开发、验证程序调试、验证数据生成、验证Testbench、验证配置环境、结果比较和分析及基于FPGA的硬件验证平台等.该验证平台已经成功应用于某混合信号SoC的设计.该芯片在0.18 μm CMOS工艺上进行了实现,工作频率为80 MHz、功耗为450 mW.该验证平台原理清晰,提高了功能验证的效率和自动程度,并对其它混合SoC设计具有一定的参考作用. 相似文献
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网络支付协议的形式化安全需求及验证逻辑 总被引:2,自引:0,他引:2
从整个网络支付协议的安全角度出发,提出网络支付协议的多层安全需求模型,包括以认证和密钥分配为基础的基层需求、网络支付协议固有的中层需求(包括保密性、原子性、公平性、完整性、匿名性、不可否认性、可追究性等)、以及面向具体应用的高层需求。基于一阶逻辑和时序逻辑,提出一种适合描述网络支付协议的形式化安全需求的逻辑,描述了该逻辑的语法结构和推理规则,并用该安全需求逻辑对网络支付协议的多层安全需求进行了形式化描述。最后,以SET协议为例进行需求验证。 相似文献
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SoC是IC设计的发展趋势,而随着SoC的日趋复杂,对系统仿真带来了越来越艰巨的挑战,基于EDA厂商提供的传统仿真环境已经不能充分满足SoC的开发需求,针对此问题提出了基于总线功能模型的仿真加速策略,测试结果表明,提出的技术策略可获得45%的仿真性能提升。 相似文献
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本文结合HTH电路的复杂性等特征分析与实际应用现状,研究了HTH电路的具体检测技术方法并对当前热点技术进行对比分析,探讨了HTH电路检测方法的技术发展趋势。 相似文献
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Analog and mixed signal (AMS) designs are an important part of embedded systems that link digital designs to the analog world. Due to challenges associated with its verification process, AMS designs require a considerable portion of the total design cycle time. In contrast to digital designs, the verification of AMS systems is a challenging task that requires lots of expertise and deep understanding of their behavior. Researchers started lately studying the applicability of formal methods for the verification of AMS systems as a way to tackle the limitations of conventional verification methods like simulation. This paper surveys research activities in the formal verification of AMS designs as well as compares the different proposed approaches. 相似文献