IP over WDM网络最小功耗模型和休眠机制研究

针对IP over WDM网络,建立了整数线性规划(ILP)最小功耗模型,计算了满足峰值业务需要开启的设备数目;对于低峰业务提出休眠机制,分别利用最小光路数算法与最小跳数算法,在保证连接无阻塞的情况下找出空闲设备,对比峰值业务得到不同算法下的设备使用率,确定IP over WDM网络的节能潜力。结果表明,ILP优化模型的网络功耗最小,最小光路数算法次之;低峰业务下利用休眠机制可以关闭设备的比例占40%～60%;采用最小光路数算法的休眠机制节能效果较优。     

Low-cost and low-power unidirectional torus network-on-chip with corner buffer power-gating

Network-on-chip (NoC) is one of critical communication architectures for the scaling of future many-core processors. The challenge for on-chip network is reducing design complexity to save both area and power while providing high performance such as low latency and high throughput. Especially, with increase of network size, both design complexity and power consumption have become the bottlenecks preventing proper network scaling. Moreover, as technology continuously scales down, leakage power takes up a larger fraction of total NoC power. It is increasingly important for a power-efficient NoC design to reduce the increasing leakage power. Power-gating, as a representative low-power technique, can be applied to an on-chip network for mitigating leakage power. In this paper, we propose a low-cost and low-power router architecture for the unidirectional torus network, and adopt an improved corner buffer structure for the inoffensive power-gating, which has minimal impact on network performance. Besides, an explicit starvation avoidance mechanism is introduced to guarantee injection fairness while decreasing its negative impact on network throughput. Simulation results with synthetic traffic show that our design can improve network throughput by 11.3% on average and achieve significant power-saving in low- and medium-load regions. In the SPLASH-2 workload simulation, our design can save on average 27.2% of total power compared to the baseline, and decrease 42.8% average latency compared to the baseline with power-gating.     

An effective state-based predictive approach for leakage energy management on embedded systems

Energy optimization is very important for portable and battery-driven embedded systems. With the shrinking of transistor sizes, reducing leakage power becomes a significant issue. In this paper, we propose a novel prediction approach to predict idleness of functional units for leakage energy management. Using a state-based predictor, historical utilization information of functional units (FUs) is exploited to adjust the state of the predictor so as to enhance the accuracy of prediction; based on it, the idleness of the FUs are predicted and utilized for leakage reduction by applying power gating. We design two prediction algorithms, the prediction with fixed threshold (PFT) and the prediction with dynamic threshold (PDT), respectively. We implement our algorithms based on SimpleScalar and conduct experiments with a suite of fourteen benchmarks from Trimaran. The experimental results show that our algorithms achieve better results compared with the previous work.     

Adaptive power gating of 32-bit Kogge Stone adder

Static power consumes a significant portion of the available power budget. Consequently, leakage current reduction techniques such as power gating have become necessary. Standard global power gating approaches are an effective method to reduce idle leakage current, however, global power gating does not consider partially idle circuits and imposes significant delay and routing constraints. An adaptive power gating technique is applied locally to a 32-bit Kogge Stone adder, and evaluated at the 16 nm FinFET technology node. This high granularity adaptive power gating approach employs a local controller to lower energy use and reduce circuit overhead. The controller conserves additional power when the circuit is partially idle (based on the inputs to the adder) by adaptively powering down inactive blocks. Moreover, the local controller reduces routing complexity since a global power gating signal is not required. The proposed adaptive power gating technique exhibits significant energy savings, ranging from 8% to 21%. This technique targets partially idle circuits, and therefore complements rather than replaces global power gating techniques. A 12% delay overhead results in a 5% area overhead. This delay overhead is reduced to 5% by increasing the area overhead to 16%, and can be further reduced by trading off additional area.     

An Innovative Power-Gating Technique for Leakage and Ground Bounce Control in System-on-a-Chip (SOC)

Leakage has become one of the most dominant factors of power consumption and signal integrity of nanometer-scale integrated circuits. Recently, power-gating structures have proven to be effective in controlling leakage. In this paper an alternative dual-V _th reduced power-gating structure is proposed for better reduction of leakage currents, especially for low-power and high-performance portable devices. The proposed technique maintains an intermediate power-saving state as well as the conventional power cut-off state. The experimental results have demonstrated that the proposed technique can significantly reduce leakage current and associated power consumptions during the HOLD and CUT-OFF modes. In addition, an analysis of ground bounce due to power-mode transition in power-gating structures is presented. It is demonstrated that the proposed technique provides a way to control ground bounce during power-mode transition. Due to the presence of the intermediate state, its stepwise turning on feature will provide higher reduction of the magnitudes of peak current and voltage glitches in the power distribution network as well as the minimum time required to stabilize power and ground as compared to other similar techniques.     

Design and optimization of dual-threshold circuits for low-voltagelow-power applications

Reduction in leakage power has become an important concern in low-voltage, low-power, and high-performance applications. In this paper, we use the dual-threshold technique to reduce leakage power by assigning a high-threshold voltage to some transistors in noncritical paths, and using low-threshold transistors in critical path(s). In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high-threshold voltage. A general leakage current model which has been verified by HSPICE simulations is used to estimate leakage power. Results show that the dual-threshold technique is good for leakage power reduction during both standby and active modes. For some ISCAS benchmark circuits, the leakage power can be reduced by more than 80%. The total active power saving can be around 50% and 20% at low- and high-switching activities, respectively     

Enhanced ground bounce noise reduction in a low-leakage CMOS multiplier

In this paper, various parameters are used to reduce leakage power, leakage current and noise margin of circuits to enhance their performance. A multiplier is proposed with low-leakage current and low ground bounce noise for the microprocessor, digital signal processors (DSP) and graphics engines. The ground bounce noise problem appears when a conventional power-gating circuit transits from sleep-to-active mode. This paper discusses a reduction in leakage current in the stacking power-gating technique by three modes – sleep, active and sleep-to-active. The simulation results are performed on a 4 × 4 carry-save multiplier for leakage current, active power, leakage power and ground bounce noise, and comparison made for different nanoscales. Ground bounce noise is limited to 90%. The leakage current of the circuit is decimated up to 80% and the active power is reduced to 31%. We performed simulations using cadence virtuoso 180 and 45 nm at room temperature at various supply voltages.     

云计算数据中心服务器数量动态配置策略

云计算数据中心由通过高速网络连接的大量服务器构成,一种有效的节能措施是维持与系统负载成比例的活跃服务器数量同时切换剩余服务器到空闲模式,由此分别产生操作能耗和切换能耗。该文研究如何动态配置活跃服务器数量以最小化数据中心能耗(操作与切换能耗之和)的问题。首先,建立了问题的NP数学模型,并分析了无切换能耗情况下最优解的特性;其次,通过消除整数动态规划的递推过程,推导具有多项式复杂度的最优静态算法;最后,采用对未来负载的最坏预测结果作为约束制定了优化在线策略。仿真结果表明,所提出的静态最优和动态优化策略能够适应外界负载的剧烈变化趋势始终谨慎调整活跃服务器和休眠服务器的比例,以接近最优的能耗代价维持数据中心的平稳运行。     

PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. Only p-channel sleep transistors and a dual-threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high-threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by up to 77% and 97% as compared to the standard dual-threshold voltage domino logic circuits at the high and low die temperatures, respectively. Similarly, a 22% to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45-nm CMOS technology. The energy overhead of the circuit technique is low, justifying the activation of the proposed sleep scheme by providing a net savings in total energy consumption during short idle periods.     

Sleep switch dual threshold Voltage domino logic with reduced standby leakage current

A circuit technique is presented for reducing the subthreshold leakage energy consumption of domino logic circuits. Sleep switch transistors are proposed to place an idle dual threshold voltage domino logic circuit into a low leakage state. The circuit technique enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. The sleep switch circuit technique significantly reduces the subthreshold leakage energy as compared to both standard low-threshold voltage and dual threshold voltage domino logic circuits. A domino adder enters and leaves a low leakage sleep mode within a single clock cycle. The energy overhead of the circuit technique is low, justifying the activation of the proposed sleep scheme by providing a net savings in total power consumption during short idle periods.     

Simultaneous spectrum sensing,data transmission and Energy harvesting in multi‐channel cognitive sensor Networks with imperfect signal cancellation

In multichannel cognitive sensor networks, the sensor users which have limited energy budgets sense the spectrum to determine the activity of the primary user. If the spectrum is idle, the sensor user can access the licensed spectrum. However, during the spectrum sensing, no data transmits. For improving the network throughput and saving more energy consumption, we propose the simultaneous spectrum sensing and data transmission scheme where the sensor receiver decodes the received signal, and from the remaining signal, the status of the channel (idle/busy) is determined. We also consider that the sensor users are powered by a radio‐frequency (RF) energy harvester. In this case, energy harvesting, data transmission, and spectrum sensing are done simultaneously. On the other hand, we select the proper sensor users for spectrum sensing and energy harvesting. We also allocate the best channels for data transmission simultaneously so that the network throughput maximizes and the constraints on the energy consumption and the detection performance are satisfied for each band. We formulate the problem and model it as a coalition game in which sensors act as game players and decide to make coalitions. Each coalition selects one of the channels to sense and transmit data, while the necessary detection probability and false alarm probability and also the energy consumption constraints are satisfied. The utility function of a coalition is proposed based on the energy consumption, false alarm probability, detection probability, and the network throughput. This paper proposes an efficient algorithm to reach a Nash‐stable coalition structure. It is demonstrated that the proposed method maximizes the network throughput and reduces the energy consumption while it provides sufficient detection quality, in comparison to other existent methods.     

Safe and efficient power management of hard real-time networks-on-chip

The power overhead of Networks-on-Chip (NoCs) becomes tremendous in high density Multiprocessor Systems-on-Chip (MPSoCs). Especially in hard real-time and safety-critical systems, power management mechanisms must be developed and efficiently adhered to real-time requirements. However, state-of-the-art solution typically induces a high timing overhead, thus challenging safety, or has limited power saving capabilities. Additionally, current power-gating mechanisms do not provide an upper bound of the latency overhead, and thus no timing guarantees. We propose a safe and enhanced approach for power-gating that allows a global and dynamic power management under timing guarantees, i.e., all deadlines of critical tasks are met. It introduces a control-layer to save power on the NoC data layer using multiple Power-Aware Traffic-Monitor (PATM) units, which apply knowledge of the global state of the system to efficiently save power on NoC routers even at high NoCs utilizations. To safely apply the PATMs in hard real-time systems while meeting the deadlines, we provide a formal worst-case timing analysis to derive PATMs upper bound latency overhead. Experimental results show that our approach efficiently reduces static power consumption, and provides scalability inducing very small area overhead.     

Efficient subthreshold leakage current optimization - Leakage current optimization and layout migration for 90- and 65- nm ASIC libraries

Leakage current is of great concern for designs in nanometer technologies. In 90- and 65-nm technologies, subthreshold leakage current dominates total leakage current. For a typical ASIC circuit running at several hundred megahertz frequencies, the subthreshold leakage power can be as high as 60% of total power. An important method for minimizing power in ASIC libraries is reducing leakage current. In this article, a complete automated leakage optimization flow that changes channel lengths and widths with cell delay and active area constraints was discussed. Optimization results show that there is ~30% leakage current reduction with a few percent active area and delay increase. There is increase in dynamic power, but the net total power reduction is significant. A uniform increase of 10% in gate length results in ~35% leakage reduction at the cost of ~12% delay degradation. The total cell area changes are minimal in both cases. The optimization flow begins with SPICE net lists from an existing library, optimizes leakage currents subject to performance metrics and active area increase constraints, and finishes with new layout generation and characterization. Investigations indicate that the leakage optimization has little impact on cell noise margin and layout parasitic modifications do not affect optimization results. The efficient automatic layout-to-layout cell leakage optimization flow is most suitable for leakage minimization and library migration for 90- and 65-nm ASIC libraries. Future work includes applying the flow to situations where layout-dependent DFM and process variation objective functions are also optimized     

Leakage power analysis and reduction during behavioral synthesis

This paper presents a high-level leakage power analysis and reduction algorithm. The algorithm uses device-level models for leakage to precharacterize a given register-transfer level module library. This is used to estimate the power consumption of a circuit due to leakage. The algorithm can also identify and extract the frequently idle modules in the datapath, which may be targeted for low-leakage optimization. Leakage optimization is based on the use of dual threshold voltage (V/sub T/) technology. The algorithm prioritizes modules giving a high-level synthesis system an indication of where most gains for leakage reduction may be found. We tested our algorithm using a number of benchmarks from various sources. We ran a series of experiments by integrating our algorithm into a low-power high-level synthesis system. In addition to reducing the power consumption due to switching activity, our algorithm provides the high-level synthesis system with the ability to detect and reduce leakage power consumption, hence, further reducing total power consumption. This is shown over a number of technology generations. The trend in these generations indicates that leakage becomes the dominant component of power at smaller feature size and lower supply voltages. Results show that using a dual-V/sub T/ library during high-level synthesis can reduce leakage power by an average of 58% for the different technology generations. Total power can be reduced by an average of 15.0%-45.0% for 0.18-0.07 /spl mu/m technologies, respectively. The contribution of leakage power to overall power consumption ranges from 22.6% to 56.2%. Our approach reduced these values to 11.7%-26.9%.     

基于可重构网络的节能方法的研究

针对当前IP网络的节能算法实用性不强的问题,根据可重构网络路由配置由中心服务器统一管理的架构特点,基于网络中的OSPF协议探测结果,提出了可重构网络下的节能方法。该方法首先运用改进的OSPF协议的路由算法定位出可被关闭的候选链路集合,接着应用多商品流模型重映射该集合中某些链路的流量到其他的物理路径,从而能够关闭候选链路集合中的空负荷链路实现网络的节能。通过实验模拟验证了该算法的节能效益,并给出了可重构网络中的节能算法与认可度极高的节能方法——GreenTE异同点。     

嵌入式系统动态电源管理预测算法研究

针对目前在嵌入式系统中动态电源管理普遍采用超时算法节能效率低的缺点,采用预测的方法进行动态电源管理.提出一个动态电源管理预测算法,该算法通过利用设备空闲状态的历史信息对未来的空闲时间进行预测,预测结果作为动态电源管理的依据.实验结果说明该算法对工作状态平稳的系统空闲预测效果比较理想,适用于动态电源管理.     

基于Prophet人工智能算法的网络潮汐效应预测研究

本文使用Prophet人工智能算法研究与预测移动通信网络“潮汐效应”现象，探索网络“潮汐效应”在优化网络资源配置实现网络降本增效的作用。Prophet人工智能算法是一种简单、有效，且易于实现的人工智能算法。通过facebook的人工智能开源框架fbprophet，研究4G网络PRB利用率等网络资源指标的“潮汐效应”，并预测这些网络资源指标在未来的变化趋势，用来指导当前4G网络减容、扩容和4/5G节电节能等，实现优化网络资源配置达到降本增效的目的。     

IP over WDM网络中能耗自感知的混合疏导专有保护算法

针对绿色生存性IP over WDM网络中资源开销大、网络阻塞率高的问题,提出一种能耗自感知的混合疏导专有保护(HG-PA-DPP)算法。首先在IP层的核心路由器对低粒度业务请求集中疏导;然后通过实时感知WDM层的链路负载和双层器件带来的链路能耗状态定义链路权值,基于分层图在不同波长平面上为各业务请求寻找权值小且链路分离的工作路径和保护路径,同时在业务的中间节点处对不需要光-电-光转换的光路进行光旁路处理;最后,将空闲或保护资源设置为休眠模式以实现节能。仿真结果表明,所提算法在高负载时有着更好的节能效果,且在大网络拓扑下资源开销(RO)为传统算法的76.5%,阻塞率(BP)仅为传统算法的61.1%。     

Resource allocation optimization algorithm based on double populations differential evolution in WSN

A resource allocation algorithm was proposed for improving the network performance through jointing channel allocation,power control and timeslot allocation in multi-radio multi-channel wireless sensor network.More specifically,the network was modeled as a multi-objective optimization problem where the energy efficient,resource allocation balanced,networks capacity maximized were considered under the link interference and link conflict constraints.Due to the problem was NP-Hardness,a simple centralized algorithm——differential evolution based on double populations was used to solve the constrained multi-objective optimization problem.The simulation results show that the proposed algorithm significantly improves the network capacity and energy efficiency and guarantees the resource allocation balancing while reducing link interference and avoiding link conflict.     

Characterization of a Novel Nine-Transistor SRAM Cell

Data stability of SRAM cells has become an important issue with the scaling of CMOS technology. Memory banks are also important sources of leakage since the majority of transistors are utilized for on-chip caches in today's high performance microprocessors. A new nine-transistor (9T) SRAM cell is proposed in this paper for simultaneously reducing leakage power and enhancing data stability. The proposed 9T SRAM cell completely isolates the data from the bit lines during a read operation. The read static-noise-margin of the proposed circuit is thereby enhanced by 2 X as compared to a conventional six-transistor (6T) SRAM cell. The idle 9T SRAM cells are placed into a super cutoff sleep mode, thereby reducing the leakage power consumption by 22.9% as compared to the standard 6T SRAM cells in a 65-nm CMOS technology. The leakage power reduction and read stability enhancement provided with the new circuit technique are also verified under process parameter variations.