A study of parasitic resistance effects in thin-channel polycrystalline silicon TFTs with tungsten-clad source/drain

With selectively-deposited tungsten film grown on source/drain regions, the parasitic source/drain resistance of thin-channel polycrystalline silicon (poly-Si) thin film transistors can be greatly reduced, leading to the improvement of device driving ability. After extracting the parasitic resistance from characteristics of devices with different channel length, the influences of parasitic resistance on device performances were discussed. A physically-based equation containing the parasitic resistance effects was derived to explain the behavior of linear transconductance under high gate voltage. Good agreements were found between calculated and measured data for both the thin-channel devices with or without tungsten-clad source/drain structure.     

Geometric effect of nickel source on low-temperature polycrystalline silicon TFTs by metal-induced lateral crystallization

Low-temperature polycrystalline silicon thin-film transistors were fabricated by nickel-induced lateral crystallization of amorphous silicon. Line and oval-shaped nickel source patterns were compared. The oval-shaped nickel source was found to render better device performance, including lower leakage current and higher on/off current ratio. The observation is interpreted by the crystallization and nickel diffusion behavior. The oval-shaped nickel source introduces less nickel in the channels, which is the physical mechanism responsible for the improved performance.     

New selfalignment processes for amorphous silicon thin film transistors with polysilicon source and drain

New fabrication processes for selfaligned amorphous silicon TFTs are proposed. The TFTs have a polysilicon source and drain which are formed by ArF excimer laser annealing. They exhibit a field-effect mobility of 0.8 cm/sup 2//Vs, threshold voltage of 11 V, and on/off current ratio of higher than 10/sup 6/.<>     

Parasitic source and drain resistance in high-electron-mobility transistors

The parasitic source and drain resistances of a high-electron-mobility transistor were analyzed in terms of a two layer transmission line model. The analysis showed that a highly conductive cap layer can function as an extension of the alloyed contact provided that tunneling between the cap layer and the channel is significant. The tunneling between the cap layer and the channel was analyzed in terms of a thermionic-field emission model in which a one dimensional time-dependent WKB transmission probability for the barrier was considered as well as Maxwell-Boltzman statistics for the tunneling carrier distribution. The GaAs cap, GaAlAs layer and 2-DEG channel can then be treated as a distributed resistance element with a characteristic coupling length. A reduction of the parasitic resistance can be obtained for a device structure with a short characteristic coupling length even if there exists an ideal alloyed contact to the 2-DEG channel. A multilayer cap consisting of an undoped GaAs layer inserted between the n-type GaAs and n-type GaAlAs is also proposed to reduce the barrier height for tunneling between the cap layer and the channel. The multilayer cap structure is predicted to appreciably reduce the parasitic resistance at room temperature and still be effective at 77 K.     

An investigation of drain pulse induced hot carrier degradation in n-type low temperature polycrystalline silicon thin film transistors

Degradation of n-type low temperature polycrystalline silicon thin film transistors under drain pulse stress is first investigated. Stress parameters are pulse amplitude, frequency and transition time. Device degradation is found to be dominated by a dynamic hot carrier effect, which is independent of pulse falling time but depends on pulse rising time. Shorter rising time brings larger device degradation. Based on experimental results and device simulation, a PN junction degradation model taking trap related carrier emission and trapping into account is proposed.     

Inkjet printed copper source/drain metallization for amorphoussilicon thin-film transistors

Source/drain metallization to amorphous silicon thin-film transistors has been made by inkjet printing. Contact pads of a metal organic copper precursor were inkjet printed, and then converted to copper metal at a maximum process temperature of 200°C. The copper contacts were used as the mask for back-channel etch. Laser printed toner was used for all other mask levels in a photoresist-free fabrication process. The inkjet printing of copper contacts represents a further step toward an all-printed thin-film transistor technology     

The effects of electrical stress and temperature on the propertiesof polycrystalline silicon thin-film transistors fabricated by metalinduced lateral crystallization

An asymmetric Ni-offset method was proposed to improve the electrical properties of poly-Si thin-film transistors (TFTs) fabricated by metal-induced lateral crystallization (MILC). The MILC/MILC boundary, which was inevitably located within the channel when formed by symmetric Ni-offset, could be successfully extracted from channel region by new asymmetric Ni-offset method. Therefore, thus fabricated TFTs showed lower leakage current and better thermal stability than symmetric Ni-offset TFTs. In addition, the effects of electrical stress and temperature on the electrical properties of symmetric/asymmetric Ni-offset TFTs were investigated     

Nonlinear source and drain resistance in recessed-gateheterostructure field-effect transistors

We have profiled the parasitic source and drain resistances versus current in recessed-gate HFET's with heavily-doped caps, using an InAlAs/n⁺-InP HFET as a vehicle. We observe a dramatic reduction in the parasitic resistances at moderate-to-high currents as significant current passes through the cap. Consequently, we note very little dependence in g, on the length of the extrinsic gate-source region. This is an experimental verification of predictions of two-layer models in the literature     

Thin-film inverters based on high mobility microcrystalline silicon thin-film transistors

Thin-film inverters based on high mobility microcrystalline silicon thin-film transistors (TFTs) with different channel lengths were realized. The NMOS enhancement load saturation mode (NELS) inverters were prepared by plasma-enhanced chemical vapor deposition at temperatures below 200 °C. The realization of microcrystalline silicon thin-film inverters facilitates the direct integration of column and row drivers and circuitry on display backpanels. The influence of the transistor properties and underlying contact effects on the performance of the inverters will be discussed.     

On the conduction mechanism in polycrystalline silicon thin-film transistors

Physical and electrical analyses were carried out on n-channel polycrystalline silicon thin-film transistors (nTFTs) with active regions as thin as approximately 6 nm. Such thin active regions extinguish the dominating effects of anomalous leakage and allow the conduction energy barrier height to be analyzed as a function of gate voltage in the femtoampere source/drain current regime. Grain size statistics were determined using plan view transmission electron microscopy. It is shown for the first time that in the absence of anomalous leakage, the barrier height does not decrease with decreasing gate voltage. In addition, the maximum measured barrier height is almost independent of active region thickness and grain size statistics. The source/drain current at low lateral field and high vertical field is also independent of channel length for all devices with length varied over an order of magnitude. These important discrepancies with existing TFT conduction theory are discussed within a physics-based model that addresses the effects of disorder-induced localized electron states in the bandgap. Besides describing existing data and well-known TFT behavioral trends, the model predicts a previously unknown relationship between threshold voltage variation, average threshold voltage and the number of grains in the channel. Analysis of data gathered from hundreds of devices of different dimensions across three different grain size distributions not only leads to agreement with the model but also to a remarkable universal behavior linking electrical and physical properties. This study shows the physics of polycrystalline silicon TFT conduction to be of the same form as amorphous and single crystal devices with the degree of disorder as the sliding scale between the two extremes.     

Fabrication of thin film transistors by chemical mechanicalpolished polycrystalline silicon films

A top-gate p-channel polycrystalline thin film transistor (TFT) has been fabricated using the polycrystalline silicon (poly-Si) film as-deposited by ultrahigh vacuum chemical vapor deposition (UHV/CVD) and polished by chemical mechanical polishing (CMP). In this process, long-term recrystallization in channel films is not needed. A maximum field effect mobility of 58 cm²/V-s, ON/OFF current ratio of 1.1 10⁷, and threshold voltage of -0.54 V were obtained. The characteristics are not poor. In this work, therefore, we have demonstrated a new method to fabricate poly-Si TFT's     

Simple source/drain contact structure for solution-processed n-channel fullerene thin-film transistors

This paper describes a simple approach for reducing the contact resistances at the source/drain (S/D) contacts in solution-processed n-channel organic thin-film transistors (OTFTs). Blending poly(ethylene glycol) (PEG) into the fullerene semiconducting layer significantly improved the device performance. The PEG molecules in the blends underwent chemical reactions with the Al atoms of the electrodes, thereby forming a better organic-metal interface. Further, the rougher surface obtained after the addition of PEG could also increase the effective contact area, thereby reducing the resistance. As a result, the electrical properties of the devices were significantly improved. Unlike conventional bilayer structures, this approach allows the ready preparation of OTFTs with a low electron injection barrier at the S/D contacts.     

Thin-film transistors on plastic and glass substrates using silicon deposited by microwave plasma ECR-CVD

Thin-film transistors (TFTs) were fabricated on polyimide and glass substrates at low temperatures using microwave ECR-CVD deposited amorphous and nanocrystalline silicon as active layers. The amorphous Si TFT fabricated at 200 /spl deg/C on the polyimide foil had a saturation region field effect mobility of 4.5 cm/sup 2//V-s, a linear region mobility of 5.1 cm/sup 2//V-s, a threshold voltage of 3.7 V, a subthreshold swing of 0.69 V/decade, and an ON/OFF current ratio of 7.9 /spl times/ 10/sup 6/. This large mobility and high ON/OFF current ratio were attributed to the high-quality channel materials with less dangling bond defect states. Nanocrystalline Si TFTs fabricated on glass substrates at 400 /spl deg/C showed a saturation region mobility of 14.1 cm/sup 2//V-s, a linear region mobility of 15.3 cm/sup 2//V-s, a threshold voltage of 3.6 V, and an ON/OFF current ratio of 6.7 /spl times/ 10/sup 6/. TFT performance was mostly independent of substrate type when fabrication conditions were the same.     

Air-gap polycrystalline silicon thin-film transistors for fully integrated sensors

Air gap thin-film transistors (TFTs) were fabricated using a solid phase crystallization process. Undoped polycrystalline silicon (polysilicon) was used as the active layer and a highly doped polysilicon bridge was used as the gate, which promotes the air gap. These TFTs have comparable threshold voltage (V/sub T/) and subthreshold slope characteristics to TFTs fabricated using pulsed laser crystallization, and using silicon dioxide as gate insulator. The low value of V/sub T/ is very important for low power consumption. Moreover, the air-gap TFT fabrication process is compatible with low-temperature glass substrate technology, which allows the integration of sensors and electronics circuits.     

Inkjet printed silver source/drain electrodes for low-cost polymer thin film transistors

Silver tracks for source/drain (S/D) electrodes in low-cost polymer thin film transistors (TFTs) have been realized through inkjet printing technique, using heavily n-doped silicon wafer with thermally grown silicon dioxide as the substrate and poly(3-hexylthiophene) (P3HT) as the channel material. Spin coating a layer of poly-4-vinylphenol (PVPh) onto the substrate was found to enhance the silver track uniformity and lower the cure temperature (from 300 to 210 °C). The surface roughness of the PVPh film was optimized to improve the device performance. The fabricated P3HT TFT with a channel length of 20 μm exhibited a saturation mobility of 3.5 × 10⁻2 cm²/V/s which was three times higher than that obtained in P3HT TFTs with gold S/D electrodes.     

Reduction of source/drain series resistance and its impact ondevice performance for PMOS transistors with raised Si1-xGex source/drain

P-channel MOS transistors with raised Si_1-xGe_x and Si source/drain (S/D) structure selectively grown by ultra high vacuum chemical vapor deposition (UHVCVD) were fabricated for the first time. The impact of Si_1-xGe_x and Si epitaxial S/D layers on S/D series resistance and drain current of p-channel transistors were studied. Our results show that devices with the raised Si_1-xGe_x S/D layer display only half the value of the specific contact resistivity and S/D series resistance (R_SD), compared with those with a Si raised S/D layer. The improvement is even more dramatic when comparing with conventional devices without any raised S/D layer, i.e., R_SD of devices with Si_1-xGe_x raised S/D is only about one fourth that of conventional devices. Moreover, the raised SiGe S/D structure produces a 29% improvement in transconductance (g_m) at an effective channel length of 0.16 μm. These performance improvements, together with several inherent advantages, such as self-aligned selective epitaxial growth (SEG) and the resultant T-shaped gate structure, make the new device with raised Si_1-xGe_x S/D structure very attractive for future sub-0.1 μm p-channel MOS transistors     

High performance of pentacene organic thin film transistors by doping of iodine on source/drain regions

Contact doping was conducted by iodine in a top contact configuration in a pentacene organic thin film transistor (OTFT), to investigate its effects on contact resistance and the resulting electrical performance. Iodine doping in the pentacene film caused the change of pentacene structure, thus leading to an increase in electrical anisotropy, i.e. ratio of lateral to vertical resistivity. The two resistive components of doped pentacene film underneath the Au contacts were major contributors to the contact resistance, and a model to explain the dependence of contact resistance on iodine doping was presented. Finally, OTFTs fabricated on iodine doped source/drain contacts exhibited high mobility of 1.078 cm²/V s, two times that of OTFTs with undoped contacts, due to the low contact resistance.     

Improving hydrogenation efficiency of polycrystalline silicon thin film transistors by a new approach

In this paper, a new hydrogenation process of poly-Si thin film for the fabrication of poly-Si thin film transistors (TFTs) is proposed. In the new approach, the hydrogenation of TFTs is performed before deposition of contact metal. N-channel and p-channel poly-Si TFTs with various channel lengths and widths were fabricated with the new and conventional processes for comparison. The results verified that the efficiency of hydrogenation has been improved remarkably by the new process. The field-effect mobility of carriers, the on state current, threshold voltage and the on/off states current ratio have been greatly improved, and the trap state density has been reduced significantly.