一种快速瞬态响应片上LDO电路

基于双有源反馈米勒补偿结构设计了一种单极点系统的无电容片上低压差线性稳压器,该线性稳压器中误差放大器采用全差分结构,两个并联的前馈通路可在提升电路瞬态响应性能的同时额外在功率管栅端构成推挽驱动级,最终电路在轻重载时具有对称的瞬态响应特性。基于TSMC 0.18μm BCD工艺仿真结果表明,在2 V～4 V电源电压下,输入输出最小压差为200 mV,最大负载电流为120 mA,瞬态响应恢复时间≤0.7μs,相位裕度≥60°。     

锁相环中一种新型的前置放大器的设计

对一种应用于锁相环分频器中的前置放大电路模块进行分析和设计,使得该模块具有由单端输入到双端差分输出,电源噪声抑制性能好,频率范围广以及电源输入范围宽等特点.采用TSMC的0.35um的工艺模型仿真,测试结果表明,其电源输入的范围为2.5V-6.5V,锁相环的最高工作频率可以达到1.3GHz.     

一种基于CLASS-AB类运放的无片外电容LDO设计

介绍了一种基于CLASS-AB类运放无片外电容的低压差线性稳压器（LDO）。电路在高摆率误差放大器（EA）的基础上,通过构建动态偏置电路反馈到EA内部动态偏置管,大幅改善了LDO的瞬态响应能力,且动态偏置电路引入的左半平面零点保证了LDO的环路稳定性。同时,EA采用过冲检测电路减小了输出过冲,缩短了环路稳定时间。电路基于65 nm CMOS工艺设计和仿真。仿真结果表明,在负载电流10μA～50 mA、输出电容0～50 pF条件下,LDO输出稳定无振荡。在LDO输入2.5 V、输出1.2 V、无片外电容条件下,控制负载在10μA和50 mA间跳变,LDO输出恢复时间为0.7μs和0.8μs,下冲和上冲电压为58 mV和15 mV。     

基于LDO线性稳压器的误差放大器设计

提出了一种功耗低、转换速率高且工作电压范围宽（2．5～5．5V）的高性能误差放大器。采用HSPICE对电路进行模拟，结果表明当工作电压为2．5V时，该放大器的转换速率约为29.4V／us，而静态电流低至16．6uA；在5．5V的工作电压下，放大器的转换速率可高达38.5V／us，静态电流却不超过20uA。     

一种高稳定性、快速瞬态响应低压差LDO

基于上华0.5 μm工艺设计了用于DC/DC的CMOS低压差线性稳压器,其输入电压为3.3 V,输出电压为1.2V,最大输出电流为100 mA;提出了一种补偿网络,保证负载电流发生变化时,LDO具有高稳定性.此外,还设计了一种瞬态响应改善电路来提高负载瞬态响应.仿真结果表明,该LDO在不同负载情况下的相位裕度均为80°,流片测试结果显示瞬态响应良好.     

一种高性能误差放大器的设计

给出了一种运用于高压DC-DC BUCK转换器的新型高性能误差放大器的设计方案。其核心模块采用差分运算跨导(OTA)三级放大结构来实现高增益,低时延等性能,同时采用0.6μm BCD HSPICE模型进行了仿真。结果表明:不同条件下的共模抑制比(CMRR)、电源抑制比(PSRR)分别在120 dB和70 dB左右,瞬态上升和下降时延均在百纳秒级,且变化范围很小。     

一种新型低功耗两级运算放大器的实现

针对目前低功耗设计的问题,讨论了一种有效的低成本的实现方式.介绍了准浮栅技术晶体管的工作原理,并运用此技术对传统的两级运算放大器进行改进.采用了Chartered 0.35um CMOS工艺来实现电路,在CADENCE Spectre的仿真结果表明,在一个工作电压为1.2V的情况下,最大开环增益可达到72.6db,相位裕度为54度,单位增益带宽为1.8MHZ,功耗仅为8.75uW,充分体现了这种技术的优越性.     

一种输出可调、低电压、高稳定性的LDO线性稳压器

该文提出了一种低电压、高稳定性低压差(LDO)线性稳压器,该LDO线性稳压器可输出6种可调电压(2.0V、1.8V、1.6V、1.4V、1.2V、1.0V).LDO的基本功能是优化便携设备的电池使用寿命,并且为电路系统提供稳定的输出电压.芯片设计基于CSMC公司的0.18微米CMOS混合信号模型.仿真结果表明,该稳压器的线性调整和负载调整的典型值分别为0.7mV和5mV;输出的最大电流为90mA;其输出压差在90mA输出电流,1.8V输出电压下为170mV.     

CMOS低压差稳压器设计

介绍了一种低功耗、低压差集成稳压器。该稳压器主要由基准电压源、误差放大器、限流保护电路、输出调整管和取样电阻组成。当输入电压从4到10V变化时,输出电压一直稳定在4V。输入电压为5V时,静态电流为2.3μA,实现了低功耗;负载为40Ω、20Ω时,最小压差分别可以达到80mV和180mV,实现了低压差。利用Hspice对稳压器电路进行了仿真,结果表明该稳压器具备较好的性能指标。集成稳压器采用0.5μm硅栅P阱CMOS工艺实现,具有很高的实用价值。     

A low offset chopper amplifier with three-stage nested Miller configuration

A low offset,low noise chopper amplifier for sensor system application is presented.Low 1/f noise is achieved by employing chopper technique,and low offset is achieved by employing residual offset suppression circuit.The open-loop gain is extended using three-stage nested Miller configuration.The chip was implemented in 0.5μm 2P3M CMOS process.The amplifier is featured by an open-loop gain of 135 dB and a GBW of3 MHz.The measured offset voltage is 3μV,and the equivalent input noise power spectrum density at 1 Hz is96 nV/√Hz.     

多频段功率可控的CMOS开关类功率放大器设计

开关类功率放大器相对于传统的线性功率放大器有更高的效率,其中E类开关功率放大器由于其高效、易于实现等特点被广泛运用,但在低频率时E类功率放大器难以达到足够的输出功率和效率。设计实现的多频段开关功率放大器在高频段（433 MHz）采用E类匹配方式,在较低的频段（315 MHz、230 MHz）采用新颖的方波匹配。在Cadence软件平台下进行仿真及版图绘制,结果显示该多频段开关功率放大器各频段都实现了20 dBm的输出功率,漏极效率均达到40%,同时,通过控制晶体管尺寸,可以对输出功率进行数字控制。     

CMOS analogue amplifier circuits optimisation using hybrid backtracking search algorithm with differential evolution

This paper proposes a novel hybrid optimisation algorithm which combines the recently proposed evolutionary algorithm Backtracking Search Algorithm (BSA) with another widely accepted evolutionary algorithm, namely, Differential Evolution (DE). The proposed algorithm called BSA-DE is employed for the optimal designs of two commonly used analogue circuits, namely Complementary Metal Oxide Semiconductor (CMOS) differential amplifier circuit with current mirror load and CMOS two-stage operational amplifier (op-amp) circuit. BSA has a simple structure that is effective, fast and capable of solving multimodal problems. DE is a stochastic, population-based heuristic approach, having the capability to solve global optimisation problems. In this paper, the transistors’ sizes are optimised using the proposed BSA-DE to minimise the areas occupied by the circuits and to improve the performances of the circuits. The simulation results justify the superiority of BSA-DE in global convergence properties and fine tuning ability, and prove it to be a promising candidate for the optimal design of the analogue CMOS amplifier circuits. The simulation results obtained for both the amplifier circuits prove the effectiveness of the proposed BSA-DE-based approach over DE, harmony search (HS), artificial bee colony (ABC) and PSO in terms of convergence speed, design specifications and design parameters of the optimal design of the analogue CMOS amplifier circuits. It is shown that BSA-DE-based design technique for each amplifier circuit yields the least MOS transistor area, and each designed circuit is shown to have the best performance parameters such as gain, power dissipation, etc., as compared with those of other recently reported literature.     

一种适用于射频数字功放的量化策略

为了提升射频数字功放整体效率,需要降低前端△∑调制器(DSM)输出的平均切换频率,以减少功放的切换损耗。基于滞环比较思想在DSM中提出了一种可变门限量化策略,并通过理论和仿真分析了该策略下DSM输出的平均切换速率以及带内SNR性能。结果表明,采用所提出的量化策略,在带内SNR减少有限的情况下,能够有效降低DSM输出的平均切换频率。     

一种高线性调整率无电容型LDO的设计

提出了一种1.8 V、70 mA片上集成的低功耗无电容型LDO(Low Dropout)电路。电路中采用了一级增益自举运放作为误差放大器,通过消除零点的密勒补偿技术提高了环路稳定性;带隙基准源(BGR)采用了线性化VBE技术进行高阶补偿,可以获得温度稳定性更好的BGR,降低了BGR对线性调整率的影响。该设计采用HHNEC 0.13μm CMOS工艺(其中VTHN≈0.78 V、VTHP≈-0.9 V),整个芯片面积为0.33 mm×0.34 mm。测试结果显示:在2.5 V-5.5 V电源供电下,LDO输出的线性调整率小于2.14 mV/V,负载调整率小于1.56 mV/mA;在正常工作模式下,整个LDO消耗56μA静态电流(其中测试用的放大器消耗电流约18μA)。     

一种改进的数字PWM发生器非线性误差预校正方法

本文针对数字D类功放中数字脉冲宽度调制（Pulse Width Modulation,PWM）发生器本身含有的非线性,提出一种改进的数字PWM发生器非线性误差预校正方法。该方法利用∑-Δ调制器特性对原方法校正因子的计算公式进行改进,使其可在校正数字PWM发生器产生的非线性误差的同时,解决了原方法由于对∑-Δ调制器加入的校正因子能量往往过大导致积分器输出饱和甚至震荡从而造成系统性能下降的问题。在所提方法基础上设计了一个数字D类音频功放系统,实验结果表明使用该方法得到的校正因子能量远小于使用原有数字PWM发生器非线性误差预校正方法得到的校正因子能量,且基本消除了数字PWM发生器产生的非线性误差。     

A two-stage information criterion for stochastic systems revisited

Two-stage information criteria for model selection are constructed by properly penalizing the maximized likelihood. A well known criterion is due to Hannan and Quinn (HQ). The applicability of HQ to multivariable, non-Gaussian, linear stochastic systems has been established by Hannan and Deistler deriving an asymptotic result for the maximized quasi-likelihood function. The objective of the paper is to provide a new, transparent and structured proof of the latter result, based on explicitly stated known techniques, under conditions only slightly stronger than those used by Hannan and Deistler. The advantage of our approach is that it naturally lends itself to the analysis of other models, such as Markov or Hidden Markov Models.     

A broadband hybrid GaN cascode low noise amplifier for WiMax applications

This article reports a Microstrip design for low noise amplifier (LNA) using a packaged commercial GaN‐on‐SiC high electron mobility transistor (HEMT). A cascode configuration with an inter‐stage matching and an independent biasing technique was used. A lumped elements design was first developed, analyzed, and simulated in ADS. Then the design was implemented using microstrip technology and simulated using the momentum EM simulation in ADS. The LNA is easy to fabricate, has a low cost, and can be easily modified for other applications. The proposed GaN LNA showed a gain of 13.5 dB with a noise figure (NF) of 3 dB from 2.8 to 3.8 GHz.     

一款3.5 GHz高效率F类功率放大器的研究与设计

根据F类功率放大器的电路结构特点,给出用LC匹配电路设计输出端的三阶谐波抑制网络的方法,设计了一款工作频率为3.5GHz的F类功率放大器。仿真结果输出功率为37dBm,功率附加效率为68%,谐波失真得到很好抑制,效率得到提高。     

A miniature low‐power ultra‐wideband low noise amplifier in 0.18 μm CMOS

A 0.18‐μm CMOS low‐noise amplifier (LNA) operating over the entire ultra‐wideband (UWB) frequency range of 3.1–10.6 GHz, has been designed, fabricated, and tested. The UWB LNA achieves the measured power gain of 7.5 ± 2.5 dB, minimum input matching of ?8 dB, noise figure from 3.9 to 6.3 dB, and IIP3 from ?8 to ?1.9 dBm, while consuming only 9 mW over 3–10 GHz. It occupies only 0.55 × 0.4 mm² without RF and DC pads. The design uses only two on‐chip inductors, one of which is such small that could be replaced by a bonding wire. The gain, noise figure, and matching of the amplifier are also analyzed. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE , 2011.