Threshold logic functions in programmable logic arrays

Methods of implementing threshold-logic functions in programmable logic arrays are described. Use is made of the properties of the threshold functions to achieve a more efficient implementation, in terms of silicon area required, than a previously described cellular array.     

Testing AND-EXOR programmable logic arrays

Diagnostic testing of programmable logic arrays that directly implement Boolean functions specified in a polynomial form (i.e., as a combination of AND and EXOR arrays) is considered. Mathematical models for possible faults are constructed, test conditions are formulated, and the fault-detection-test generation problem is solved. Test interchangeability is analyzed in order to optimize and minimize the tests.     

Optimization of programmable logic arrays

We describe two techniques for the minimization of the area of a Programmable Logic Array (PLA). Based on the logic functions to be implemented an assignment of the inputs and outputs to the columns of a PLA is determined that is especially suited for row segmentation. An upper bound and a lower bound for the number of rows in the segmented PLA are derived. Furthermore, it is shown how the result can be improved upon by the duplication of some of the inputs.     

High-speed programmable logic arrays in ESFI SOS technology

Exploratory MOS programmable logic array (PLA's) operating up to a clock frequency of 22 MHz have been realized and successfully operated. These PLA's used dynamic logic gates and are built in epitaxial-silicon films on insulators (ESFI) silicon-on-sapphire (SOS) technology. The problems arising with the use of these dynamic gates in a two-stage logic array are discussed and different circuits are presented. The advantage of these circuits, in addition to their high speeds, is reduced power consumption, and the possibility to determine the number of feedback loops when the array is personalized. The features of the circuits are compared with each other with a complete PLA described in an earlier paper (see ibid., vol. SC-10, p.331 (1975)). The results gained from computer simulations agree reasonably well with the experimental results.     

A function-independent self-test for large programmable logic arrays

It has been shown that small PLAs can be made self-testing. The proposed methods however fail to handle large functions fast or result in a large overhead. Here a method is shown that can be implemented efficiently at large PLAs. The test only needs a system clock and an initialization signal, producing a go/no-go signal after an AND plane size-dependent delay.     

Structure and applications of field programmable logic arrays

The recent surge in design activity involving microprocessors and microprogramming techniques reflects the growing trend to replace hardwired logic with microcode for gaining system flexibility at lower cost. In this respect, designers have come to rely on ever larger and denser PROMs to fit the demands of their applications, and today PROMs as large as 4K-bits, organized as 512X8 or 1KX4 are readily available. However, a PROM solution in general forces the user to allocate storage for all possible logic combinations of the input variables, whether needed or not. As a result, when dealing with the type of problem requiring the manipulation of more than about 10 logic variables (or Addresses), several IC packages are usually necessary. This quickly renders a PROM solution marginal at best in terms of speed, power, and cost, and in most cases impractical.Fortunately, many combinational and sequential logic designs involve logic functions which are True for only a small subset of the total logic states generated by the controlling variables. It is here that we step in the basic domain of Field Programmable Logic Arrays which, when viewed as Associative memories, exhibit Selective, Concurrent and Multiple addressing modes that enable compressing a set of logic functions to the minimum required states, at substantial savings in hardware. Also, since FPLAs can be programmed in the field by the user, they are more economical and easier to use than mask programmable PLAs, and should find their way quickly in a wider variety of design situations     

The OR-k method for on-line checking of programmable logic arrays

A programmable logic array (PLA) is nonconcurrent if every input pattern selects exactly one product term. We relax this requirement to limited concurrency where all product terms selected by the same input pattern must have identical output parts. A new testing method, OR-k testability, is developed for the on-line (concurrent) checking of limited concurrency PLAs. OR-k testing detects errors due to the selection of one or more extra product terms, and a conventional two-rail parity check on the outputs detects the other errors from single stuck-at, bridging, cross-point and broken line faults. The output patterns of an OR-k testable PLA must be unordered. For such PLAs, certain subsets of the outputs take on an all 1's pattern only in the presence of an extra product term error condition. A limited concurrency PLA tested by OR-k testability is strongly fault secure.This work was supported in part by the Natural Sciences and Engineering Research Council of Canada.     

Fault detection in RNS systolic arrays

The letter discusses simple techniques for the implementation of fault detection in residue number system (RNS) arithmetic modules used in systolic arrays. The technique centres around a recently developed linear systolic structure, and does not require a redundant residue system for the detection process. It is shown that this structure can be used as the detection process in a fault-correcting RNS system.     

Concurrent error detection in highly structured logic arrays

Two strategies for encoding the inputs and outputs of highly structured logic arrays (HSLAs) are introduced. The two schemes are particularly relevant for concurrent error detection of both permanent and nonpermanent errors in programmable logic arrays (PLAs) and read-only memories (ROMs). The first method of concurrent error detection (CED) is based on a comprehensive fault model and relies on detection of unidirection errors. The second approach relies on a detailed examined of decoder layouts resulting in fault avoidance through layout rules, which avoid failures causing unidirectional errors. Efficient parity techniques are shown to provide a low-overhead solution to concurrent error detection when coupled with appropriate fault-avoidance techniques.     

使用可编程逻辑器件的压控振荡器

VCO(压控振荡器)是一种模拟电路,所以在数字可编程芯片设计库中找不到VCO。当需要用这种电路来实现同步或时钟频率倍增时,必须找到一种可与标准数字功能元件(如“与”门和“与非”门)一起使用的电路。制作可变频率振荡器的方法有好几种。例如,你可以用变容二极管来改变振荡器频率。遗憾的是,这种变容二极管的每伏频率的变化量很小。所以,采用一个倒相器和几只电容器的标准皮尔斯振荡器不适用于这样的场合。另一种方法是使用一个施密特触发器倒相器和改变充电的电阻器。这种方法可能适用,但该IC滞后性的容差通常很大,所以选用的倒相器芯片会对频率产生很     

Evaluating programmable logic devices

The use of the combinational/register coordinate system as a graphical way of measuring programmable logic devices (PLDs) in terms of gates and registers is reviewed. It is assumed that the I/O resources of the PLD, which constitute a third axis, are adequate. This allows the analysis to be restricted to an x-y plane fixed along the z-axis. The device's application area, which is the area bounded by its combinational and register capability, is discussed, and methods for calculating the application range are described. Three brief examples demonstrate the ways in which the coordinate system might be used in CAD tools that automate the PLD design process     

Field programmable gate arrays in space

The use of field programmable gate arrays (FPGAs) in satellite and other spacecraft is on the rise. They are increasingly competitive when compared to traditional application-specific integrated circuits (ASICs). However, exposure to space radiation produces the same physical effects on both FPGAs and ASICs. How these radiation effects can translate to circuit malfunctions and how these problems can be prevented or mitigated is a complex, multifaceted issue that depends on the specific technology and the device's internal architecture. First and foremost, designers should implement a reliable ASIC/FPGA development methodology for the definition, design, verification, physical implementation and validation phases of any ASIC/FPGA to be flown as part of the spacecraft platform or critical payload. This should be contractually enforced. The European Space Agency (ESA) will continue to make available its own internal standard or any other equivalent methodology proposed by the contractor. As soon as the new ECSS standard on this subject is available, ESA will start using it as an applicable document in all projects where ASICs or FPGAs are to be developed.     

Antifuse field programmable gate arrays

An antifuse is an electrically programmable two-terminal device with small area and low parasitic resistance and capacitance. Field-programmable gate arrays (FPGAs) using antifuses in a segmented channel routing architecture now offer the digital logic capabilities of an 8000-gate conventional gate array and system speeds of 40-60 MHz. A brief survey of antifuse technologies is provided. the antifuse technology, routing architecture, logic module, design automation, programming, testing and use of ACT antifuse FPGAs are described. Some inherent tradeoffs involving the antifuse characteristics, routing architecture and logic module are illustrated     

Fault detection for multiple-valued logic circuits with fanout-free

The single fault and multiple fault detections for multiple-valued logic circuits are studied in this paper. Firstly, it is shown that the cardinality of optimal single fault test set for fanout-free m-valued circuits with n primary inputs is not more than n + 1, for linear tree circuits is two, and for multiplication modulo circuits is two if n is an odd number or if n is an even number and m > 3, where the optimal test set of a circuit has minimal number of test vectors. Secondly, it is indicated that the cardinality of optimal multiple fault test set for linear tree circuits with n primary inputs is 1 + [n/(m - 1)], for multiplication modulo circuits is n + 1, for fanout-free circuits that consist of 2-input linear tree circuits and 2-input multiplication modulo circuits is not greater than n+ 1, where [x] denotes the smallest integer greater than or equal to x. Finally, the single fault location approaches of linear tree circuits and multiplication modulo circuits are presented, and all faults in th     

High-speed static programmable logic array in LOCMOS

A large static programmable logic array (PLA) with 20 inputs, 94 product terms, and 24 outputs, designed and realized in LOCMOS, the complementary MOS technology with isolation by local oxidation of silicon. Layout and physical parameters of this technology resulted in a simple, dense, and low-capacity design. The dc and transient features of different realization possibilities have been simulated. Design automation tools have been developed to ensure error-free personalization of the PLA. A density of 160 gates per mm/SUP 2/ has been achieved. Samples show average propagation delays of 100 ns, while dissipation is typically 120 mW.     

Fault detection in combinational circuits using Gunn effect logic devices

It is shown that certain realisations of combinational switching functions using Gunn effect logic gates can be tested for single or multiple stuck-type faults by using two tests only. This result is achieved by exploiting the fact that the function of Gunn effect logic gates is sensitive to bias voltage