On circuit clustering for area/delay tradeoff under capacity andpin constraints

In this paper, we propose an iterative area/delay tradeoff algorithm to solve the circuit clustering problem under the capacity constraint. It first finds an initial delay-considered area-optimized clustering solution by a delay-oriented depth first-search procedure. Then, an iterative procedure consisting of several reclustering techniques is applied to gradually trade the area for the performance. We then show that this algorithm can be easily extended to solve the clustering problem subject to both capacity and pin constraints. Experimental results show that our algorithm can provide a complete set of clustering solutions from the area-optimized one to the delay-optimized one for a given circuit. Furthermore, compared to the existing delay-optimized algorithms, this algorithm achieves almost the same performance but with much less area overhead. Therefore, this algorithm is very useful for solving the timing-driven circuit clustering problem     

On area/depth trade-off in LUT-based FPGA technology mapping

In this paper, we study the area and depth trade-off in lookup-table (LUT) based FPGA technology mapping. Starting from a depth-optimal mapping solution, we perform a sequence of depth relaxation operations and area-minimizing mapping procedures to produce a set of mapping solutions for a given design with smooth area and depth trade-off. As the core of the area minimization step, we have developed a polynomial time optimal algorithm for computing an area-minimum mapping solution without node duplication for a K-bounded general Boolean network, which makes a significant step towards complete understanding of the general area minimization problem in FPGA technology mapping. The experimental results on MCNC benchmark circuits show that our solution sets outperform the solutions produced by most existing mapping algorithms in terms of both area and depth minimization     

Efficient Realization of Parity Prediction Functions in FPGAs

In this paper, we propose an AND/XOR-based technology mapping method for efficient realization of parity prediction functions in field programmable gate arrays (FPGAs). Due to the fixed size of the programmable blocks in an FPGA, decomposing a circuit into sub-circuits with appropriate number of inputs can achieve an excellent implementation efficiency. Specifically, the proposed technology mapping method is based on Davio expansion theorem. The AND/XOR nature of the proposed method allows it to operate on XOR intensive circuits, such as parity prediction functions, efficiently. We conduct experiments using the parity prediction functions with respect to MCNC benchmark circuits. With the proposed approach, the number of configurable logic blocks (CLBs) is reduced by 67.6% (compared to speed-optimized results) and 57.7% (compared to area-optimized results), respectively. The total equivalent gate counts are reduced by 65.5%, maximum combinational path delay is reduced by 56.7%, and maximum net delay is reduced by 80.5% compared to conventional methods.     

一体化标识网络映射缓存DoS攻击防范方法研究

为了抵御一体化标识网络中接入路由器可能遭受的映射缓存DoS攻击,本文提出了一种基于双门限机制的映射缓存DoS攻击防范方法.该方法设计了一种基于迭代思想的谜题机制降低映射缓存中映射信息条目的增加速率,并采用了映射信息可信度算法识别和过滤映射缓存中恶意的映射信息条目.仿真实验与性能分析表明,该方法能够有效地抵御映射缓存DoS攻击,防止映射缓存溢出.     

Heuristic Loop-Based Scheduling and Allocation for DSP Synthesis with Heterogeneous Functional Units

This paper presents a new heuristic, concurrent, iterative loop-based scheduling and allocation algorithm for high-level synthesis of digital signal processing (DSP) architectures using heterogeneous functional units. In a heterogeneous architecture, functional units could be either bit-serial or digit-serial or bit-parallel. We assume that a library of functional units based on heterogeneous implementation style is available. Experiments show that this new heuristic synthesis approach generates optimal and near-optimal area solutions. Although optimum synthesis of such architectures were proposed recently using an integer linear programming (ILP) model, our method can produce similar solutions in one to two orders of magnitude less time, at the expense of sacrificing the cost optimality. We compare the solutions generated by the proposed algorithm with the optimal solutions generated by the ILP approach and other recent techniques. We have incorporated this new algorithm into the Minnesota ARchitecture Synthesis (MARS-II) system.     

5G低轨卫星两步随机接入方案及其FPGA实现

为了实现低轨卫星通信系统高效率低时延的用户接入,提出了适用于低轨卫星系统的两步随机接入方案,对随机接入信道的数据发送、信道结构、前导码设计以及映射关系进行了设计,并进行了现场可编程门阵列（Field Programmable Gate Array,FPGA)实现。针对传统MAX-LOG-MPA算法FPGA处理时延长的问题,提出了一种节点并行迭代更新的FPGA接收机设计来降低处理时延。仿真结果验证了所设计的信道结构以及FPGA实现的可行性,相比传统接入方式可接入的用户数量更多,同时采用并行节点迭代更新的接收机将迭代处理时延降低为1/6。     

Hardware implementation of fault tolerance NoC core mapping

Due to performance and reliability, network on chip (NoC) is considered to be the future generation interconnect technique for multiple cores in a chip. This paper proposes a system level core mapping technique which improves the performance of the whole system, while rectifying the temporary faults and permanent faults in the system using error correcting codes and spare core. This technique mainly focuses on the core mapping and faults on the system. This results in reliable core mapping and improved performance when a fault-related error occurs on an NoC. At last, the proposed core mapping technique is simulated and verified on FPGA board (Kintex-7 FPGA KC705 Evaluation Kit).     

Simultaneous area and delay minimum K-LUT mapping for K-exact networks

We address the technology mapping problem for lookup table FPGAs. The area minimization problem, for mapping K-bounded networks, consisting of nodes with at most K inputs, using K-input lookup tables, is known to be NP-complete for K 5. The complexity was unknown for K = 2, 3, and 4. The corresponding delay minimization problem (under the constant delay model) was solved in polynomial time by the flow-map algorithm, for arbitrary values of K. We study the class of K-bounded networks, where all nodes have exactly K inputs. We call such networks K-exact. We give a characterization of mapping solutions for such networks. This leads to a polynomial time algorithm for computing the simultaneous area and delay minimum mapping for such networks using K-input lookup tables. We also show that the flow-map algorithm computes the same mapping solution as our algorithm. We then show that for K = 2 the mapping solution for a 2-bounded network, minimizing the area and delay simultaneously, can be easily obtained from that of a 2-exact network derived from it by eliminating single input nodes. Thus the area minimization problem for 2-input lookup tables can be solved in polynomial time, resolving an open problem.     

Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect

We present a technology mapping algorithm for implementing a random logic gate network in domino logic. The target technology of implementation is silicon-on-insulator (SOI). SOI devices exhibit an effect known as parasitic bipolar effect (PBE), which can lead to incorrect logic values in the circuit. Our algorithm solves the technology mapping problem by permitting several transformations during the mapping process in order to avoid PBE, such as transistor reordering, altering the way that transistors are organized into gates, and adding pMOS discharge transistors. We minimize the total cost of implementation, which includes discharge transistors required for correct functioning. Our algorithm generates solutions that reduce the number of discharge transistors required by 53% and reduces the size of the final solution by 6.3% on average. We compare our results with a modification of a current technology mapping algorithm for bulk CMOS domino logic that reduces the cost of the final solution and find that our algorithm outperforms this method.     

Iterative resource pooling for bandwidth allocation in TDM-PON: algorithm, convergence and experimental evaluation

In this paper, we propose a new dynamic bandwidth allocation technique, SLIding Cycle Time (SLICT) for TDM-PON, specifically focused on ethernet passive optical network (EPON). Based on the sliding cycle time constraint, the proposed algorithm guarantees the maximum polling interval, an essential property for delay-sensitive applications and interactive services. We then introduce an iterative resource pooling that processes bursty best-effort traffic and achieves high throughput even under non-uniform upstream traffic distribution. We prove that greedy iterative resource pooling converges to equal resource allocation exponentially fast. Extensive numerical simulations show that SLICT outperforms existing techniques in all aspects: throughput, delay, packet loss and average queue size. Finally, SLICT has been implemented on an EPON FPGA board and the performance is confirmed under real traffic.     

无线传感器网络数据的迭代凸优化重构

为提高弱相关性网络数据压缩感知的可靠性和有效性,提出一种基于迭代凸优化的网络数据重构方法.该方法利用多次凸优化算法共同重构相关性较弱的网络数据,在每次运行凸优化算法后,对已重构出的数据向量元素进行加权以降低权值,而使其他的数据向量元素在下次凸优化中得到重构.与以往的压缩感知重构方法相比,迭代凸优化重构可在网络数据相关性较弱的情况下保证重构准确度.仿真实验验证了所提方法的正确性.     

Robust Transceiver Design for Multicell MIMO Downlink Systems

The robust linear transceiver design for the more general model of multicell MIMO downlink system with imperfect channel state information is discussed in this paper. Our aim is to minimize the total power of the network while the quality of service (QoS) in terms of mean-square error (MSE) for every user should be strictly guaranteed for every channel realization in the uncertain region. Unfortunately, this problem may be infeasible due to the MSE constraints. Therefore, we provide a complete analysis of this problem by dividing the solutions into two phases. In phase I, a novel approach is devised to check the feasibility of this problem by considering one alternative problem which is always feasible. This alternative problem is troublesome due to infinite nonconvex MSE constraints. To handle this, we propose an iterative algorithm that performs optimization alternatively by switching between the precoders and decoders. The two subproblems in the algorithm can be recast as semidefinite programming problems which can be efficiently solved. In phase II, one novel iterative algorithm is proposed to solve the original robust problem. Finally, simulation results show that our proposed algorithms converge rapidly and can provide guaranteed QoS for all users. Moreover, we also show that, the more antennas at the users, the more power savings it can provide.     

Placement and routing tools for the Triptych FPGA

Field-programmable gate arrays (FPGAs) are becoming an increasingly important implementation medium for digital logic. One of the most important keys to using FPGAs effectively is a complete, automated software system for mapping onto the FPGA architecture. Unfortunately, many of the tools necessary require different techniques than traditional circuit implementation options, and these techniques are often developed specifically for only a single FPGA architecture. In this paper we describe automatic mapping tools for Triptych, an FPGA architecture with improved logic density and performance over commercial FPGAs. These tools include a simulated-annealing placement algorithm that handles the routability issues of fine-grained FPGAs, and an architecture-adaptive routing algorithm that can easily be retargeted to other FPGAs. We also describe extensions to these algorithms for mapping asynchronous circuits to Montage, the first FPGA architecture to completely support asynchronous and synchronous interface applications     

RAPID PROTOTYPING - Area efficient FIR filters for high speed FPGA implementation

A new algorithm that synthesises multiplier blocks with low hardware requirement suitable for implementation as part of full-parallel finite impulse response (FIR) filters is presented. Although the techniques in use are applicable to implementation on application-specific integrated circuit (ASIC) and Structured ASIC technologies, analysis is performed using field programmable gate array (FPGA) hardware. Fully pipelined, full-parallel transposed-form FIR filters with multiplier block were generated using the new and previous algorithms, implemented on an FPGA target and the results compared. Previous research in this field has concentrated on minimising multiplier block adder cost but the results presented here demonstrate that this optimisation goal does not minimise FPGA hardware. Minimising multiplier block logic depth and pipeline registers is shown to have the greatest influence in reducing FPGA area cost. In addition to providing lower area solutions than existing algorithms, comparisons with equivalent filters generated using the distributed arithmetic technique demonstrate further area advantages of the new algorithm     

FPGA面积限制下延时最小化工艺映射

工艺射是ＦＰＧＡ设计中的关键技术，目前的研究目标是面积最小经，延时最小化和延时限制下面积最小化。     

基于FPGA的误差校正神经网络算法设计与实现

为了能够在真实硬件平台上进行实现,本文对原有的误差校正构造性神经网络算法进行了优化,并对优化后的误差修正算法进行了FPGA设计与实现。提出算法通过在自动生成一个合适的神经架构的同时对二个参数进行设置来提高算法性能。本文对这种算法实现的所有步骤进行了全面的描述并利用两种基准问题对结果进行了深入分析。结果显示,与标准的基于个人计算机（PC）的实现相比,本文提出的神经网络算法FPGA实现在计算速度方面有着明显的提高,由此证明了FPGA在误差校正算法神经计算任务中的实用性及适用性。     

Noninvasive myocardial activation time imaging: a novel inverse algorithm applied to clinical ECG mapping data

Linear approaches like the minimum-norm least-square algorithm show insufficient performance when it comes to estimating the activation time map on the surface of the heart from electrocardiographic (ECG) mapping data. Additional regularization has to be considered leading to a nonlinear problem formulation. The Gauss-Newton approach is one of the standard mathematical tools capable of solving this kind of problem. To our experience, this algorithm has specific drawbacks which are caused by the applied regularization procedure. In particular, under clinical conditions the amount of regularization cannot be determined clearly. For this reason, we have developed an iterative algorithm solving this nonlinear problem by a sequence of regularized linear problems. At each step of iteration, an individual L-curve is computed. Subsequent iteration steps are performed with the individual optimal regularization parameter. This novel approach is compared with the standard Gauss-Newton approach. Both methods are applied to simulated ECG mapping data as well as to single beat sinus rhythm data from two patients recorded in the catheter laboratory. The proposed approach shows excellent numerical and computational performance, even under clinical conditions at which the Gauss-Newton approach begins to break down.     

Optimal Dynamic Routing in Single Commodity Networks by Iterative Methods

In this paper, we present iterative methods for finding optimal state-dependent routing strategies in single commodity networks. The key to our method is to show that there exists a family of optimization problems with convex cost and linear constraints that have solutions that can be converted into an optimal routing strategy by way of a flow relaxation transformation. These problems, when solved by certain iterative algorithms, lead to different convergence rates. In particular, one of the problems has quadratic cost. To solve one of these optimization problems, we use an iterative projected descent direction algorithm due to Bertsekas. We present an alternative to the Armijo-like step size rule of the algorithm, which we believe is more robust. Also included are Newton-like descent directions that take a reasonable amount of time to compute. Finally, some results of our computer experiments are summarized.     

SVM‐Based Speaker Verification System for Match‐on‐Card and Its Hardware Implementation

Using biometrics to verify a person's identity has several advantages over the present practice of personal identification numbers (PINs) and passwords. To gain maximum security in a verification system using biometrics, the computation of the verification as well as the storing of the biometric pattern has to take place in a smart card. However, there is an open issue of integrating biometrics into a smart card because of its limited resources (processing power and memory space). In this paper, we propose a speaker verification algorithm using a support vector machine (SVM) with a very few features, and implemented it on a 32‐bit smart card. The proposed algorithm can reduce the required memory space by a factor of more than 100 and can be executed in real‐time. Also, we propose a hardware design for the algorithm on a field‐programmable gate array (FPGA)‐based platform. Based on the experimental results, our SVM solution can provide superior performance over typical speaker verification solutions. Furthermore, our FPGA‐based solution can achieve a speed‐up of 50 times over a software‐based solution.     

An efficient framework for dynamic reconfiguration of instruction-set customization

We present an efficient framework for dynamic reconfiguration of application-specific custom instructions. A key component of this framework is an iterative algorithm for temporal and spatial partitioning of the loop kernels. Our algorithm maximizes the performance gain of an application while taking into consideration the dynamic reconfiguration cost. It selects the appropriate custom instructions for the loops and clubs them into one or more configurations. We model the temporal partitioning problem as a k-way graph partitioning problem. A dynamic programming based solution is used for the spatial partitioning. Comprehensive experimental results indicate that our iterative partitioning algorithm is highly scalable while producing optimal or near-optimal (99% of the optimal) performance gain.