Novel interface nitridation process for thin gate oxides

A thin (100-200-Å) gate dielectric film which exhibits improved properties as compared to control pure thermal oxides is discussed. The film is obtained by thermal nitridation of the silicon wafers in pure ammonia, followed by high temperature oxide (HTO) deposition, and an anneal in oxygen ambient (reoxidation). It was found that these dielectrics exhibit excellent electrical characteristics under Fowler-Nordheim tunneling stress, such as a relatively large charge-to-breakdown considerable reduction in charge trapping, reduction of interface state generation, and a significantly improved resistance to transconductance degradation. The dielectric layer is of potential use for the fabrication of reliable ultrathin gate oxide films for standard CMOS technology and particularly for nonvolatile programmable memories     

Extraction and evolution of Fowler-Nordheim tunneling parameters of thin gate oxides under EEPROM-like dynamic degradation

A new method is presented for the extraction of the Fowler-Nordheim (FN) tunneling parameters of thin gate oxides from experimental current-voltage characteristics of Metal-Oxide-Semiconductor (MOS) capacitors. In this technique, the classical low temperature FN current model is considered but an improved numerical procedure has been implemented for the calculation of the oxide electric field — gate voltage relationship. It is shown that this iterative method leads to an excellent fit of experimental data with theoretical curves for both p-type and n-type substrates, even in the case of high doping levels. The procedure allows the determination of both FN tunneling parameters and potential barrier heights at silicon and polysilicon interfaces with a systematic estimation of the statistical fitting errors on each parameter. It is applied here to the study of the variations of the FN tunneling parameters of thin oxides submitted to EEPROM-like dynamic degradation.     

Effect of nitridation on the reliability of thick gate oxides

In this work the effect of nitridation on the reliability of thick (60 nm) gate oxides used in discrete power MOSFETs is investigated. Nitridation was carried out by post-oxidation anneal in N₂O at 1000 °C. Secondary ion mass spectroscopy characterization did show that the nitrogen resulting from N₂O nitridation piles up in the oxide at the Si–SiO₂ interface regardless of nitridation time. The results obtained show improved breakdown field (E_bd), and charge-to-breakdown (Q_bd) characteristics for nitrided thick oxides. Also, lower mid-bandgap interface trap density (D_it) was observed in the case of nitrided oxides. Key conclusion from this experiment is that nitridation of thick (>50 nm) gate oxide performed to suppress boron penetration into the MOSFET channel region is not having an adverse effect on its electrical characteristics.     

Effects of Fowler-Nordheim stress on interface trap density andemission cross sections in n-MOSFETs studied by three-level chargepumping

High field Fowler-Nordheim (F-N) stress effects on interface-trap density and emission cross sections in n-MOSFETs have been studied using three-level charge pumping (3LCP). The results show that 3LCP is sensitive to changes in trap cross section as a function of energy in the bandgap. An asymmetric change in electron and hole emission cross sections following F-N tunneling injection is found. The work also provides further insight into the influence of hot electrons on interface trap generation in MOSFETs in both the upper and lower bandgap following electrical stress     

The effect of hydrogen on trap generation, positive chargetrapping, and time-dependent dielectric breakdown of gate oxides

The effect of high-temperature (≈900°C) hydrogen on the gate oxides of MOS devices is studied. Hydrogen is introduced into devices by either high-temperature anneal or conventional process steps such as low-pressure chemical vapor deposition (LPCVD) of Si₃N₄. In all cases, measurements of high-field stress behavior show that high-temperature hydrogen steps reduce time to breakdown and increase bulk and interface trap generation, but do not affect the generation of positive charge. These results indicate that the wear-out mechanism of gate oxides at high fields is related to trap generation rather than to accumulation of positive charge     

A new model for the post-stress interface trap generation inhot-carrier stressed p-MOSFETs

A new insight into the post-stress interface trap (N_it) generation in hot-electron stressed p-MOSFETs is presented. N_it generation is suppressed for positive oxide field but enhanced for negative oxide field. This observation provides strong support for a two-carrier model, involving the recombination between trapped electrons and inversion holes. While post-stress interface instability has generally been associated with hole trapping and hydrogen transport, our results clearly show the importance of electron traps on the long term stability of the Si-SiO₂ interface, and that the two-carrier model provides a consistent explanation for post-stress N_it generation in p-MOSFETs stressed under hot-electron injection     

Post-stress interface trap generation induced by oxide-field stresswith FN injection

Interface trap generation in nMOS transistors during both stressing and post-stress periods under the conditions of oxide field (dynamic and dc) stress with FN injection is investigated with charge pumping technique. In contrast to the post-stress interface trap generation induced by hot carrier stress which is a logarithmical function of post-stress time, the post-stress interface trap generation induced by oxide-field stress with FN injection first increases with post-stress time but then becomes saturated. The mechanisms for the interface trap generation in both stressing and post-stress periods are described     

Analytic model for the post-breakdown conductance of sub-5-nm SiO/sub 2/ gate oxides

A new model for the post-breakdown conductance of ultrathin gate oxides based on the generalized diode equation is presented. The model is expressed in terms of the Lambert W function, that is, the inverse of the function w/spl rarr/we/sup w/. We show that this alternative formulation improves a previous one, the quantum point contact model, especially in the low bias range, where the role played by the semiconductor electrodes cannot be overlooked. The practical implementation of the proposed equations is discussed.     

Process dependence of interface state generation due to irradiation and hot carrier stress in rapid thermally nitrided thin gate oxides

A study of the effects of nitridation time and temperature on the interface state generation in MOS devices with thin rapid thermally nitrided gate oxides is reported. A different process dependence was observed for interface state generation caused by X-ray irradiation and hot carrier stress. The discrepancy is explained using the structural changes at the interface during nitridation and some of the earlier defect generation models.<>     

Comparison of neutral electron trap generation by hot-carrierstress in n-MOSFET's with oxide and oxynitride gate dielectrics

A comparative study of neutral electron-trap generation due to hot-carrier stress in n-MOSFETs with pure oxide, NH₃-nitrided oxide (RTN), and reoxidized nitrided oxide (RTN/RTO) as gate dielectrics is reported. Results show that neutral electron trap generation is considerably suppressed by nitridation and reoxidation. The nature of neutral traps is described based on the kinetics of trap filling by electron injection into the gate dielectrics immediately after channel hot-electron stress (CHES). Improved endurance of the RTN and RTN/RTO oxides is explained using physical models related to interfacial strain relaxation     

Evidence for bulk trap generation during NBTI phenomenon in pMOSFETs with ultrathin SiON gate dielectrics

Negative bias temperature instability (NBTI) of pMOSFETs with direct-tunneling SiON gate dielectrics was studied in detail. By investigating the effects of applying positive gate bias on pMOSFETs after exposure to NBT stress, the generation of bulk charge traps in the gate dielectrics during NBTI was clearly demonstrated. In particular, it was found that a positive charge generated by negative bias temperature stress (NBT stress) can be neutralized and that the neutralized site can return to the positive state. We consider that the bulk trap is due to hydrogen atoms released from the interface between the SiON gate dielectric and the Si substrate (and this is what has conventionally been considered a positive fixed charge). Moreover, the bulk trap generation was shown to give rise to stress-induced leakage current.     

A comparative study of gate direct tunneling and drain leakagecurrents in n-MOSFET's with sub-2 nm gate oxides

This work examines different components of leakage current in scaled n-MOSFET's with ultrathin gate oxides (1.4-2.0 nm). Both gate direct tunneling and drain leakage currents are studied by theoretical modeling and experiments, and their effects on the drain current are investigated and compared. It concludes that the source and drain extension to the gate overlap regions have strong effects on device performance in terms of gate tunneling and off-state drain currents     

Transient isothermal generation at the silicon-silicon oxide interface and the direct determination of interface trap distribution

The theory of transient isothermal generation through the interface traps at the semiconductor-insulator interface is presented. The generation current (I_g) vs time (t) characteristic is obtained in terms of the interface trap distribution throughout the bandgap. It is shown that a plot of I_et vs log_et is a direct image of the energy distribution of the traps in the upper-half of the bandgap (in the case of an n-type semiconductor) and a plot of I_gt vs log_et is a direct image of the trap distribution in the lower-half of the bandgap.     

Enhancement of tbd of mos gate oxides with a single-step pre-stress prior to a CVS in the Fowler-Nordheim regime

This work demonstrates that a pre-stressing step can enhance oxide reliability. Single-step pre-stresses were performed with a wide range of parameters prior to a constant voltage stress. It was found that the tbd increase due to the pre-stress has two limits and is dependent on both: pre-stress bias level and pre-stress time. A power law relation has been established between t_bd and the charge injected during the pre-stress. It was found that the charge threshold for the onset of the t_bd increase is much higher than the initially trapped positive charge.     

Current limited stresses of SiO/sub 2/ gate oxides with conductive atomic force microscope

Current limitation effects on the breakdown (BD) of ultrathin SiO/sub 2/ layers have been analyzed at a nanometric scale with a conductive atomic force microscope (C-AFM). Bare oxide regions have been stressed and broken down using the tip of the C-AFM as the metal electrode of a metal-oxide-semiconductor (MOS) structure. BD induced negative charge (BINC) has been observed at the BD location, which has been related to the structural damage generated by the BD event. Moreover, BD, although triggered at one point, is electrically propagated to neighbor regions. The area affected by BD and the amount of BINC (the structural damage) depend on the breakdown hardness. In particular, it is shown that both magnitudes are smaller when the current through the structure is limited during BD transient. Based on the results, a qualitative picture of the breakdown process is presented, which accounts for the current limitation effects.     

Synchrotron x-ray irradiation effects on the device characteristics and the resistance to hot-carrier damage of MOSFETs with 4 nm thick gate oxides

The effects of synchrotron x-ray irradiation on the device characteristics and hot-carrier resistance of n- and p-channel metal oxide semiconductor field effect transistors (MOSFETs) with 4 nm thick gate oxides are investigated. In p-channel MOSFETs, device characteristics were significantly affected by the x-ray irradiation but completely recovered after annealing, while the device characteristics in n-channel MOSFETs were not noticeably affected by the irradiation. This difference appears to be due to a difference in interface-state generation. In p-channel MOSFETs, defects caused by boron-ion penetration through the gate oxides may be sensitive to x-ray irradiation, causing the generation of many interface states. These interface states are completely eliminated after annealing in hydrogen gas. The effects of irradiation on the resistance to hot-carrier degradation in annealed 4 nm thick gate-oxide MOSFETs were negligible even at an x-ray dose of 6000 mJ/cm².     

A dual-metal gate integration process for CMOS with sub-1-nm EOT HfO/sub 2/ by using HfN replacement gate

A replacement gate process employing a HfN dummy gate and sub-1-nm equivalent oxide thickness (EOT) HfO/sub 2/ gate dielectric is demonstrated. The excellent thermal stability of the HfN-HfO/sub 2/ gate stack enables its use in high temperature CMOS processes. The replacement of HfN with other metal gate materials with work functions adequate for n- and pMOS is facilitated by a high etch selectivity of HfN with respect to HfO/sub 2/, without any degradation to the EOT, gate leakage, or time-dependent dielectric breakdown characteristics of HfO/sub 2/. By replacing the HfN dummy gate with Ta and Ni in nMOS and pMOS devices, respectively, a work function difference of /spl sim/0.8 eV between nMOS and pMOS gate electrodes is achieved. This process could be applicable to sub-50-nm CMOS technology employing ultrathin HfO/sub 2/ gate dielectric.     

A model to study the effect of selective anodic oxidation on ultrathin gate oxides

We have studied the effect of selective anodic oxidation on ultrathin (22-31 /spl Aring/) silicon dioxide grown at different temperatures ranging from 600/spl deg/C to 875/spl deg/C, on both p- and n-type substrates. A model based on the concept of filling of pinholes by selective anodic oxidation is presented to quantitatively explain the reduction in the gate leakage current of the MOS capacitors after selective anodic oxidation.     

On the mechanism for interface trap generation in MOS transistorsdue to channel hot carrier stressing

The classical concept and theory suggest that the degradation of MOS transistors is caused by interface trap generation resulting from “hot carrier injection.” We report three new experiments that use the deuterium isotope effect to probe the mechanism for interface trap generation in n-MOS transistors in the presence of hot hole and electron injection. These experiments show clearly that hot carrier injection into the gate oxide exhibits essentially no isotope effect, whereas channel hot electrons at the interface exhibit a large isotope effect. This leads to the conclusion that channel hot electrons, not carriers injected into the gate oxide, are primarily responsible for interface trap generation for standard hot carrier stressing     

A new technique for determining long-term TDDB accelerationparameters of thin gate oxides

A new technique, the dual voltage versus time curve (V-t) integration technique, is presented as a much faster method to obtain time-dependent dielectric breakdown (TDDB) acceleration parameters (α and τ) of ultrathin gate oxides compared to conventional long-term constant voltage stress tests. The technique uses V-t curves measured during highly accelerated constant or ramped current injection breakdown tests. It is demonstrated that the technique yields acceleration parameters that are statistically identical to values obtained from long-term constant voltage TDDB tests. In contrast to traditional TDDB tests, the proposed technique requires over an order of magnitude less testing time, a smaller sample size, and can be used during production monitoring