"Bipolar-mode" transistors on a voltage-controlled scheme

A buried-gate vertical JFET (BVFET) operated under forward gate bias shows saturating or nonsaturating drain current characteristics simply by Changing the channel cross section area. BVFET with a proper channel cross section has similar characteristics to a "bipolar-mode" SIT (BSIT) or a depleted base transistor (DBT). A generalized picture is derived relating these forward-biased JFET's to the conventional bipolar transistor (BPT). Analysis of BVFET has proved that the operation of BSIT is completely the same as that of BPT with its base voltage controlled. The current saturation mechanism is discussed in detail in this paper.     

双极模式静电感应晶体管及其复合管的原理

静电感应器件通过控制漏和栅的电压来改变沟道中的势垒高度,从而控制来自源区的多数载流子量,并通过静电式控制沟道中的电势分布,来控制电流。本文说明了BSIT单管及大电流高增益复合管的主要工艺过程和工作原理,特别是BSIT由小电流区域变到大电流区域的过程中Ⅰ-Ⅴ曲线的变化及机理。为了更好地了解BSIT的工作原理,针对DX421型BSIT器件作了计算机模拟,最后对其单管和大电流高增益复合管的一些参数如电流放大系数、阻断电压和饱和压降进行了讨论。     

A high power MOSFET with a vertical drain electrode and a meshed gate structure

A MOSFET with a maximum power of 200 W in a 5/spl times/5 mm/SUP 2/ chip which exhibits 20-A current, 3000-millimho transconductance and 100-V breakdown voltage has been developed. The features of the device structure are a vertical drain electrode which makes it possible to use most of the surface area for the source electrode, and a meshed gate structure which realizes an increase in the channel width per unit area. The p-channel device with an offset gate structure was fabricated from an n on p/SUP +/ epitaxial wafer by using polysilicon gate and ion implantation processes. The device can be operated stably at ambient temperatures up to 180/spl deg/C. While the bipolar transistor is a suitable power device in the low voltage region, the MOSFET looks more promising in the high voltage region than the V-FET and the bipolar transistor.     

Frequency doubling in GaAs/AlGaAs field effect transistor usingreal space transfer

A modified field effect transistor (FET) topology is used which enhances the real space transfer of carrier out of the channel toward a special collector terminal. The drain current rises, peaks, and then reduces as gate voltage is increased due to a steep rise in collector current with gate voltage. When biased near the peak, the AC drain current induced by the gate is folded over becoming frequency doubled. The device exhibits functional multiplexing being operable as either a positive transconductance, negative transconductance, or frequency doubling element setable via quiescent gate voltage     

基于硅衬底静电感应晶体管器件仿真与研究

针对静电感应晶体管理论研究迟滞于实践过程,文中利用软件Silvaco Tcad,从器件仿真入手,对影响硅基表面栅静电感应晶体管器件电学性能进行了理论研究。仿真得到了反偏栅压约为0 V、漏电压＜20 V时,器件表现类五极管饱和特性曲线,器件电流约为10-5 A,此时沟道状态为预夹断。当反偏栅压为-1.5 V、漏电压逐渐增大到300 V时,器件表现为类三极管不饱和特性曲线,器件电流约为10-6 A,此时沟道状态为完全夹断,研究结果静电感应晶体管工艺实践提供了参考。     

Cut-off frequency and transit time analysis in short geometry polysilicon thin-film transistors

An accurate model for the drain characteristics, transconductance, cut-off frequency and transit time of a short geometry polysilicon thin film transistor (poly-Si TFT) is presented. An accurate threshold voltage and field dependent mobility are the key parameters in determining the above-threshold characteristics. The current-voltage characteristics of the device show an excellent agreement with experimental results. The transconductance for both linear and saturation regions is calculated and its variation with channel length, drain and gate voltages is studied. The total gate capacitance including the geometric capacitance and the fringing capacitance is also evaluated and simple closed form expressions for the cut-off frequency and transit time are obtained. A high cut-off frequency is achieved, which is important in realizing the device for millimetre and microwave frequency applications.     

用二维全带组合Monte Carlo方法模拟纤锌矿相GaN静电感应晶体管(SIT)特性

报告了用二维全带组合Monte Carlo方法模拟纤锌矿相GaN静电感应晶体管(SITs)交直流特性的结果.SIT的栅极长度为0.13μm,源极和漏极之间距离为0.5μm.模拟得到了SIT的输出特性,跨导和特征频率特性.模拟得到的跨导最大值为140ms/mm(Vgs=-1.5V),器件特征频率最大值为123GHz(I_ds=3.15A/cm).模拟结果表明纤锌矿相GaN SIT具有大功率和高频工作的潜力.     

InGaP/InGaAs doped-channel direct-coupled field-effect transistors logic with low supply voltage

InGaP/InGaAs doped-channel direct-coupled field-effect transistor logic (DCFL) with relatively low supple voltage is demonstrated by two-dimensional analysis. In the integrated enhancement/depletion-mode transistors, subband and two-dimensional electron gas (2DEG) are formed in the InGaAs strain channels, which substantially increase the channel concentration and decrease the drain-to-source saturation voltage. The integrated devices show high turn-on voltage, high transconductance, broad gate voltage swing, and excellent high frequency performance, simultaneously. Furthermore, the integrated devices exhibit large noise margins for DCFL application with low supply voltage of 1.5 V attributed from the relatively small saturation voltages of the studied integrated devices.     

Microwave-Rectification RFI Response in Field-Effect Transistors

This paper discusses the rectification of microwave energy in low-medium frequency feld-effect transistors (FET's) and develops a small-signal model for RHI noise analysis in low-frequency linear circuitry. The modeling procedure centers on a Taylor series expansion of the gate voltage-drain current characteristic which shows a small increase in drain current due to a nicrowave voltage at the gate. The increase in drain current is proportional to the variation in transconductance with gate voltage, and the square of the microwave voltage. Analysis of the microwave power in the transistor shows that critical parameters in determnination of the sensitivity are the gate capacitance and the real part ofthe device input impedance, which ultimately is limited by the parasitic resistance between the active channel and contacts.     

Mechanism of negative transconductance in heterostructurefield-effect transistors

In most heterostructure field-effect transistors the drain current at very large gate voltages drops with an increase of the gate voltage leading to a negative device transconductance. Based on the analysis of the gate and channel current distributions in such devices, it is shown that the negative transconductance at large gate currents is related to the dramatic change in the electric field distribution in the channel and to the saturation of the density of the two-dimensional electron gas in the channel. Under such conditions the electric field increases at the source side of the channel where the gate current primarily flows. When the electric field at the source side exceeds the electric field at the drain side of the channel, the device transconductance becomes negative. This is related to a higher voltage drop near the source side of the channel causing a partial depletion in the channel     

A high-performance δ-dopedGaAs/InxGa1-xAs pseudomorphic high electronmobility transistor utilizing a graded InxGa1-xAschannel

A δ-doped GaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (HEMT) utilizing a graded In composition InGaAs channel grown by low-pressure metalorganic chemical vapor deposition was demonstrated. This structure had an extrinsic transconductance as high as 175 (245) mS/mm and a saturation current density a high as 500 (690) mA/mm at 300 (77) K for a gate length of 2 μm. The maximum transconductance versus gate bias extended over a broad and flat region of more than 2 V at 300 K. A low gate leakage current (<10 μA at -7 V) at 300 K was obtained     

Characterization of the frequency dispersion of transconductance and drain conductance of GaAs MESFET

Frequency dispersions of the transconductance and the drain conductance of ion-implanted gallium arsenide (GaAs) metal-semiconductor field-effect transistors (MESFETs) are measured and analyzed. In the linear region of the MESFET (low drain voltage), a positive transconductance dispersion is observed, which is caused by the deep-level traps at the surface between the source and the gate. In the saturation region (high drain voltage), however, a negative transconductance dispersion becomes dominant. The drain conductance does not show a dispersion in the linear region, while a distinct positive dispersion is observed in the saturation region with the same activation energy as the negative transconductance dispersion. The difference of the dispersion activation energy of the MESFET with and without the p-buried layer beneath the channel indicates that the negative transconductance and the drain conductance dispersion are caused by the deep-level traps at the channel-substrate interface. Because there exists the high electric field at the drain edge of the gate and an electron accumulation layer is formed, the potential in the channel becomes lower when the drain current is larger with high gate voltage. The emission of electrons from electron traps with lower potential is the cause of the negative frequency dispersion.     

On the improvement of gate voltage swings in δ-doped GaAs/InxGa1-xAs/GaAs pseudomorphic heterostructures

Significant improvements in gate voltage swings in heterostructures prepared by low-pressure metalorganic chemical vapor deposition are discussed. Structures utilizing a compositionally graded In_xGa_1-xAs channel exhibited a very flat transconductance region of 2 V. The gate voltage swings of single and double δ-doped GaAs/In_0.25Ga_0.75As/GaAs structures were 2.5 and 2.8 V, respectively. All structures also exhibited high extrinsic transconductance as well as high saturation current densities     

The resonant-tunneling field-effect transistor: A new negative transconductance device

A new field-effect transistor with a resonant-tunneling barrier in the gate is presented. The gate and the drain currents versus gate voltage exhibit peaks when the resonant-tunneling gate current is quenched. Thus, in addition to negative differential resistance, this structure also exhibits negative transconductance, a unique feature in an n-channel device. Also, by proper gate bias, the same resonance of the double barrier can be used to produce two peaks in the drain current versus drain voltage characteristic at nearly the same current level. This is a very desirable feature for many applications.     

Pulse-doped diamond p-channel metal semiconductor field-effecttransistor

A p-type diamond metal semiconductor field-effect transistor (MESFET) structure, utilizing a boron pulse-doped layer as the conducting channel, has been successfully fabricated. The pulse-doped structure consists of an undoped diamond buffer layer, a highly doped thin diamond active layer, and an undoped diamond cap layer grown by the microwave plasma assisted chemical vapor deposition method. It is shown that this field-effect transistor with a gate length of 4 μm and the gate width of 39 μm exhibits an extrinsic transconductance of 116 μS/mm with both pinch-off characteristics and current saturation     

Self-aligned metal-SiO2-InP based MISFETS having modulation doped channels

A novel metal-SiO₂-InP MISFET (metal-insulator-semiconductor field effect transistor) structure is proposed. This device incorporates a modulation doped channel and the self-aligned gate feature of Si MOSFETs. The modulation doping provides very high electron mobility and the self-alignment of gate, source and drain provides high packing density. Analytical results on current-voltage and transconductance characteristics are presented. Significant enhancement in high frequency performance over conventional MISFETs, employing SiO₂ as an insulator, is reported.     

Transconductance degradation in VVMOS power transistors due to thermal and field effects

A relatively simple transconductance equation for the VVMOS power transistor is presented in this paper. Temperature and gate voltage dependent surface mobility as well as temperature dependent surface saturation velocity are shown to be responsible for transconductance degradfation. Theoretical results are in very good agreement with experimental measurements over a wide range of gate voltages.     

Nonlinear distortion and mixing processes in field-effect transistors

From the transfer characteristic of the junction-type field effect transistor, nonlinear distortion effects can be evaluated without difficulty. It is shown how the conversion transconductance can be calculated as a function of the operating point, the local oscillator voltage and the oscillator output resistance. A new method has been derived which permits a very precise evaluation of the conversion transconductance even if the operating point is chosen in the cutoff region. The investigations deal with the influence of the signal amplitude upon nonlinear distortion in mixer stages and also treat the generation of whistles. The conversion transconductance exhibits a flat maximum as a function of the gate bias voltage. Thus, an optimum operating range can be indicated where the ratio between mixing current and distortion product currents is most favorable. Finally, it is shown how the operating point can be preserved in stabilized mixer stages and some reference details for the behavior of FET stages at very high frequencies are given.     

Enhancement-Mode Metamorphic HEMT on GaAs Substrate With 2 S/mm $g_{m}$ and 490 GHz $f_{T}$

This letter presents the results of an enhancement mode metamorphic high-electron-mobility transistor device on a GaAs substrate with a 70% indium composition channel. A 35-nm gate length device exhibits a 490-GHz current gain cutoff frequency (f_T), a transconductance (g_m) of 2 S/mm, a threshold voltage (V_th) of 0.11 V (enhancement mode) and a low on- resistance of 0.37 Omega mm. These attributes make the device well- suited for millimeter-wave circuit applications.     

Some CMOS device constraints at low temperatures

Two of the CMOS device constraints at low temperatures have been identified, namely, the transconductance and the breakdown voltage roll-off. In the short channel devices, the transconductance first increases then decreases with the decreasing temperature. This transconductance roll-off phenomenon is likely caused by the parasitic series resistance in the source and drain regions. The breakdown voltage of the MOSFET's due to the parasitic bipolar transistor action decreases with the decreasing temperature, which is caused by the increase of the impact ionization rate at low temperatures.